ADC-HS12B

ADC-HS12B
12-Bit A/D Converter with Sample-Hold
FEATURES
„ 12-Bit resolution
„ Internal sample and hold
„ 6 Microseconds acquisition time
„ 9 Microseconds conversion time
„ Programmable input ranges
„ Parallel output
Typical unit
PRODUCT OVERVIEW
MECHANICAL DIMENSIONS
The ADC-HS12B is a high performance 12-bit hybrid AID converter with a
self-contained sample-hold. It is specifically designed for systems applications where the sample-hold is an integral part of the conversion process. The
internal sample-hold has a 6 microseconds acquisition time for a full 10V dc
input change; the AID converter has a fast 9 microseconds conversion time.
Five input voltage ranges are programmable by external pin connection; 0 to
+5V, 0 to+10V, ±2.5V, ±5V, and ±10V. Input impedance to the sample-hold is
100 megohms. Output coding is complementary binary for unipolar operation
and complimentary offset binary for bipolar operation.
The ADC-HS12B uses a fast 12-bit monolithic DAC which includes a precision zener reference source. The circuit also contains a fast monolithic 12-bit
successive approximation register, a clock and a monolithic sample-hold.
0.235 MAX
(5.969)
0.190 MAX
(4.826)
0.035/0.015
(0.889/0.381)
PIN #1 INDEX
0.021/0.016
(0.534/0.406)
0.045/0.035
(1.143/0.889)
0.100 BSC
(2.54)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1.72/1.69
(43.69/42.92
0.11/0.09
(2.80/2.28)
1.11/1.08
(28.20/27.43)
0.200/0.175
(5.08/4.44)
SEATING PLANE
SIMPLIFIED SCHEMATIC
CH
SAMPLE BIPOLAR REF
CONTROL OFFSET OUT
17
32
23
+15Vdc -15Vdc
18
28
0.015/0.009
(0.381/0.228)
+5Vdc
31
16
0.920/0.890
(23.37/22.60)
6.3K
PRECISION
REFERENCE
CIRCUIT
SAMPLE
HOLD
ANALOG 30
IN
Dimensions in inches (mm)
S.H. 29
OUT
12-BIT
D/A CONVERTER
27
GAIN
ADJUST
15
DIGITAL
COMMON
COMPARATOR
COMPAR 22
IN
14
5K
10V 24
RANGE
20V
RANGE 25
SUCCESSIVE
APPROXIMATION
REGISTER
5K
20
SHORT
CYCLE
E.O.C.
STATUS
Pin
CLOCK
ANALOG 26
COMMON
4
5
6
7
8
9 10 11 12
12 11 10 9
8
7
6
5
4
1
LSB
2
3
BIT NO.
3
2
1
MSB
13
SERIAL
DATA
OUT
CLOCK
OUT
START
CONVERT
19 21
PARALLEL DATA OUT
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
INPUT/OUTPUT CONNECTIONS
Function
Pin
Function
1
BIT 12 OUT (LSB)
17
2
BIT 11 0UT
18
CH
REF
3
BIT 10 OUT
19
DO NOT CONNECT
4
BIT 9 OUT
20
E.O.C. (STATUS)
5
BIT 8 OUT
21
START CONVERT
6
BIT 7 OUT
22
COMPAR INPUT
7
BIT 6 OUT
23
BIPOLAR OFFSET
8
BIT 5 OUT
24
10V RANGE
9
BIT 4 OUT
25
20V RANGE
10
BIT 3 OUT
26
ANALOG COM
11
BIT 2 OUT
27
GAIN ADJ
12
BIT 1 OUT (MSB)
28
+ 15V POWER
13
DO NOT CONNECT
29
S.H. OUTPUT
14
SHORT CYCLE
30
ANALOG IN
15
DIGITAL COM
31
-15V POWER
16
+5V POWER
32
SAMPLE CONTROL
•
www.datel.com
•
e-mail: [email protected]
09 Jul 2015
MDA_ADCHS-12B.B03 Page 1 of 4
ADC-HS12B
12-Bit A/D Converter with Sample-Hold
Functional Specifications
Typical at 25°C, ± 15V and + 5V supplies unless otherwise noted.
Inputs
Analog Input Ranges, unipolar
0 to + 5V, 0 to + 10V
Analog Input Ranges, bipolar
± 2.5V, ± 5V, ± 10V
Physical/Environmental
Operating Temp. Range, Case
O°C to 70°C (BMC, BMC-C)
-40°C to +100°C (BME, BME-C)
-55°C to +125°C (BMM, BMM-QL)
Input Impedance1
100 megohms
Input Bias Current1
50 nA typical, 200 nA max.
Storage Temperature Range
2V min. to + 5.5V max. positive pulse with 100
nsec. duration min. Rise and fall times <30
nsec. Logic high to low transition resets
converter and initiates next conversion.
Loading: 2 TIL loads
Package Type
32 pin ceramic
Pins
0.010 x 0.018 inch Kovar
Weight
0.5 ounces (14 grams)
Start Conversion
Sample Control Input
Logic high = hold
Logic low = sample
Loading: 1 TTL load
-65°C to +150°C
FOOTNOTES:
1.
For sample-hold input
2.
All digital outputs can drive 2 TTL loads
3.
For 1000 pF external hold capacitor
Outputs2
Parallel Output Data
Absolute Maximum Ratings
12 parallel lines of data held until
next conversion command.
VOUT ("O")≤ +0.4V
VOUT ("1")≥ +2.4V
Coding, unipolar
Complementary Binary
Coding, bipolar
Complementary Offset Binary
End of Conversion (status)
Conversion status signal. Output is logic high
during reset and conversion and low when
conversion is complete.
Sample-Hold Performance3
Input Offset Drift
25 μV/°C
AcquisitionTime,10V to 0.01%
6 μsec.
Bandwidth
1 MHz
Aperture Delay Time
100 nsec.
Aperture Uncertainty Time
10 nsec.
Sample to Hold Error
2.5 mV max.
Hold Mode Droop
200 nV/μsec. max.
Hold Mode Feedthrough
0.01% max.
± ½ LSB max.
Differential Nonlinearity
± ¾ LSB max.
Temp. Coefficient of Gain
± 20 ppm/°C max.
Temp. Coefficient of Zero, unipolar
± 5 ppm/°C of FSR max.
Temp. Coefficient of Offset, bipolar
± 10 ppm/°C of FSR max.
Differential Nonlinearity Tempco
± 2 ppm/°C of FSR
MIssing Codes
None over oper. temp. range
Conversion Time
9 μsec. max.
Power Supply Rejection
0.004%/% max.
Power Requirements
Power Suppy Voltage
+ 15V dc ±0.5V at 20 mA
-15V dc ± 0.5V at 25 mA
+5V dc ±0.25V at 85 mA
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
Negative Supply, pin 31
- 18V
Logic Supply Voltage, pin 16
+ 5.5V
Digital Input Voltage, pins 14, 21, 32
+5.5V
Analog Input Voltage, pin 30
± 15V
1.
It is recommended that the ±15V power input pins both be bypassed to ground with a 0.01 μF ceramic capacitor in parallel with a 1 μF electrolytic capacitor and the +5V power input pin be bypassed to ground with a 1 μF
electrolytic capacitor as shown in the connection diagrams. In addition, pin 27 should be bypassed to ground
with a 0.01 μF ceramic capacitor. These precautions will assure noise free operation of the converter.
2.
Digital Common (pin 15) and Analog Common (pin 26) are not connected together internally, and therefore must
be connected as directly as possible externally. It is recommended that a ground plane be run underneath the
case between the two commons. Analog ground and ±15V power ground should be run to pin 26 whereas
digital ground and +5V dc ground should be run to pin 15.
3.
External adjustment of zero or offset and gain are provided for by trimming potentiometers connected as shown
in the connection diagrams. The potentiometer values can be between 10K and 100K ohms and should be
100 ppm/ °C, cermet types. The adjustment range is ±0.5% of FSR for zero or offset and ±0.3% for gain. The
trimming pots should be located as close as possible to the converter to avoid noise pickup. Calibration of the
ADC-HS12B is performed with the sample-hold connected and operating dynamically. This results in adjusting
out the sample-hold errors along with the A/D converter. For slow throughput applications it is recommended
that a 0.01 μF hold capacitor be used for best accuracy. With this value the acquisition time becomes 25
microseconds and the external timing must be adjusted accordingly.
4.
The recommended timing shown in the Timing Diagram allows 6 microseconds for the sample-hold acquisition
and then 1 microsecond after the sample-hold goes into the hold mode to allow for output settling before the
A/D begins its conversion cycle.
5.
Short cycled operation results in shorter conversion times where the conversion can be truncated to less than
12 bits. This is done by connecting pin 14 to the output bit following the last bit desired. For example, for an
8-bit conversion, pin 14 is connected to bit 9 output. Maximum conversion times are given for short-cycled
conversions in the Table.
6.
Note that output coding is complementary coding. For unipolar operation it is complementary binary and for
bipolar operation it is complementary offset binary. In cases where bipolar coding of offset binary is required, this
can be achieved by inverting the analog input to the converter (using an operational amplifier connected for gain
of -1.0000). The converter is then calibrated so that - FS analog input gives an output code of 0000 0000 0000,
and + FS - 1 LSB gives 1111 1111 1111.
7.
These converters dissipate 1.81 watts maximum of power. The case to ambient thermal resistance is approximately 25°C per watt. For ambient temperatures above 50°C, care should be taken not to restrict air circulation
in the vicinity of the converter.
8.
These converters can be operated with an external clock. To accomplish this, a negative pulse train is applied
to START CONVERT (Pin 21). The rate of the external clock must be lower than the rate of the internal clock.
The pulse width of the external clock should be between 100 nanoseconds and 300 nanoseconds. Each N bit
conversion cycle requires a pulse train of N + 1 clock pulses for completion, e.g., an 8-bit conversion requires
9 clock pulses for completion. A continuous pulse train may be used for consecutive conversions, resulting in
an N bit conversion every N + 1 pulses, or the E.O.C. output may be used to gate a continuous pulse train for
single conversions.
12 bits (1 part in 4096)
Nonlinearity
+ 18V
TECHNICAL NOTES
Converter Performance
Resolution
Positive Supply, pin 28
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
09 Jul 2015
MDA_ADCHS-12B.B03 Page 2 of 4
ADC-HS12B
12-Bit A/D Converter with Sample-Hold
TRIGGER
100 nsec MIN
SAMPLE
CONTROL
6 μsec
START
CONVERT
1 μsec
60 nsec
E.O.C.
(STATUS)
PARALLEL DATA
NOW VALID
9 μsec MAX
40 nsec
0
BIT 1
OUT (MSB)
1
0
BIT 2
OUT
1
0
BIT 3
OUT
1
0
BIT 12
OUT (LSB)
1
NOTE: TRIGGER, SAMPLE CONTROL, AND START CONVERT
TIMING DIAGRAM FOR ADC·HS12B
-15V +15V
1 μF
+5V
1 μF
+
+
-15V +15V
1 μF
+
+5V
1 μF
1 μF
+
0.01
μF
0.01
μF
+
1 μF
+
+15V
0.01
μF
31 28
ANALOG IN
(0 TO +10V)
+15V
0.01
μF
16 14
31 28
15
30
1.5 MEG
ANALOG
GND
26
22
24
50K
OFFSET
ADJUST
2.8 MEG
ADC-HS12B
29
50K
27
23
ANALOG IN
(+5V)
30
ANALOG
GND
26
24
CH*
10000 pF
32
SAMPLE
CONTROL
0.01 μF
GAIN
ADJUST
50K
21
START
CONVERT
50K
27
23
1.5 MEG
17
22
ADC-HS12B
2.8 MEG
GAIN
ADJUST
0.01 μF
15
29
+15V
16 14
OFFSET
ADJUST
*POLYSTYRENE OR
TEFLON TYPE
-15V
17
32
21
-15V
CH*
10000 pF
UNIPOLAR OPERATION, 0 TO + 10V
SAMPLE
CONTROL
START
CONVERT
*POLYSTYRENE OR
TEFLON TYPE
-15V
BIPOLAR OPERATION, ±5V
CODING TABLES
UNIPOLAR OPERATION
INPUT RANGE
BIPOLAR OPERATION
COMP. BINARY CODING
MSB
LSB
INPUT VOLTAGE RANGE
COMP. BINARY CODING
0 TO +10V
0 TO +5V
+10V
+5V
+2.5V
+9.9976V
+4.9988V
0000 0000 0000
+9.9951V
+4.9976V
+ 2.4988V
MSB
0000 0000 0000
LSB
+8.7500
+4.3750
0001 1111 1111
+7.5000
+3.7500
+ 1.8750
0001 1111 1111
+ 7.5000
+3.7500
0011 1111 1111
+5.0000
+2.5000
+ 1.2500
0011 1111 1111
+5.0000
+2.5000
0111 1111 1111
0.0000
0.0000
0.0000
0111 1111 1111
+2.5000
+ 1.2500
1011 1111 1111
-5.0000
-2.5000
-1.2500
1011 1111 1111
+ 1.2500
+0.6250
1101 1111 1111
-7.5000
-3.7500
-1.8750
1101 1111 1111
+0.0024
+ 0.0012
1111 1111 1110
-9.9951
-4.9976
-2.4988
1111 1111 1110
0.0000
0.0000
1111 1111 1111
-10.0000
-5.0000
-2.5000
1111 1111 1111
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
• Tel: (508) 339-3000
•
www.datel.com
•
e-mail: [email protected]
09 Jul 2015
MDA_ADCHS-12B.B03 Page 3 of 4
ADC-HS12B
12-Bit A/D Converter with Sample-Hold
CALIBRATION PROCEDURE
1. Connect the ADC-HS12B as shown in one of the connection diagrams. The
sample-hold and AID converter should be timed as shown in the timing
diagram. The trigger pulse should be applied at a rate of 70 kHz or less
and should be 100 nanoseconds minimum width.
2. Zero and Offset Adjustments
Apply a precision voltage reference source between the selected analog
input and ground. Adjust the output of the reference source to the value
shown in the Calibration Table for the unipolar zero adjustment (zero +%
LSB) or the bipolar offset adjustment (- FS + % LSB). Adjust the trimming
potentiometer so that the output code flickers equally between 1111 1111
1111 and 1111 1111 1110.
3. Full Scale Adjustment
Change the output of the precision voltage reference source to the value
shown in the Calibration Table for the unipolar or bipolar gain adjustment
(+ FS - 1% LSB). Adjust the gain trimming potentiometer so that the output
code flickers equally between 0000 0000 0001 and 0000 0000 0000.
CALIBRATION TABLE
ADJUST.
INPUT VOLTAGE
0 to + 5V
ZERO
GAIN
+ 0.6 mV
+ 4.9982V
0 to + 10V
ZERO
GAIN
+ 1.2 mV
+ 9.9963V
± 2.5V
OFFSET
GAIN
-2.4994V
+ 2.4982V
± 5V
OFFSET
GAIN
– 4.9988V
+ 4.9963V
± 10V
OFFSET
GAIN
– 9.9976V
+ 9.9927V
UNIPOLAR RANGE
BIPOLAR RANGE
14
PIN 14 CONNECTION FOR SHORT CYCLE OPERATION
RES. (BITS)
PIN 14 TO
CONV. TIME
1
PIN 11
O.7 μsec
2
PIN 10
1.3
3
PIN 9
2.0
4
PIN 8
2.6
5
PIN 7
3.3
6
PIN 6
4.0
7
PIN 5
4.6
8
PIN 4
5.3
9
PIN 3
6.0
10
PIN 2
6.6
11
PIN 1
7.3
12
PIN 16
9.0
INPUT VOLTAGE RANGE
5
6
7
8
9
10
11
12
9
8
7
6
5
4
3
2
1
BIT
FOR CONVERSION TO N BITS
CONNECT THE N+1 BIT OUTPUT
TO THE SHORT CYCLING
TERMINAL, PIN 14.
ORDERING GUIDE SUMMARY
INPUT CONNECTIONS
CONNECT THESE PINS TOGETHER
0 to +5V
29 & 24
22 & 25
23 & 26
O to +10V
29 & 24
–
23 & 26
±2.5V
29 & 24
22 & 25
23 & 22
±5V
29 & 24
–
23 & 22
±10V
29 & 25
–
23 & 22
DATEL is a registered trademark of DATEL, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
4
MODEL
TEMP. RANGE
RoHS COMPLIANCE
ADC-HS12BMC
ADC-HS12BMC-C
ADC-HS12BME
ADC-HS12BME-C
ADC-HS12BMM
ADC-HS12BMM-C
ADC-HS12BMM-QL
ADC-HS12BMM-QL-C
0 to +70 °C
0 to +70 °C
-40 to +100 °C
-40 to +100 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
-55 to +125 °C
Non-RoHS
RoHS
Non-RoHS
RoHS
Non-RoHS
RoHS
Non-RoHS
RoHS
DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information
contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of
licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice.
ITAR and ISO 9001/14001 REGISTERED
© 2015 DATEL, Inc.
www.datel.com • e-mail: [email protected]
09 Jul 2015
MDA_ADCHS-12B.B03 Page 4 of 4