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This IC can directly drive the MOS-FET with fast rise and fast fall output pulse. Type M51995A has the functions of not only high frequency OSC and fast output drive but also current limit with fast response and high sensibility so the true “fast switching regulator” can be realized. It has another big feature of current protection to short and over current, owing to the integrated timer-type protection circuit, if few parts are added to the primary side. The M51995A is equivalent to the M51977 with externally re-settable OVP (over voltage protection) circuit. Features • 500 kHz operation to MOS FET Output current : ±2 A Output rise time 60 ns, fall time 40 ns Modified totempole output method with small through current • Compact and light-weight power supply Small start-up current : 90 µA typ. Big difference between “start-up voltage” and “stop voltage” makes the smoothing capacitor of the power input section small. Start-up threshold 16 V, stop voltage 10 V Packages with high power dissipation are used to with-stand the heat generated by the gate-drive current of MOS FET. 16-pin DIP, 20-pin SOP 1.5 W (at 25°C) • Simplified peripheral circuit with protection circuit and built-in large-capacity totempole output High-speed current limiting circuit using pulse-by-pulse method (Two system of CLM+pin, CLM−pin) Protection by intermittent operation of output over current : Timer protection circuit Over-voltage protection circuit with an externally re-settable latch (OVP) Protection circuit for output miss action at low supply voltage (UVLO) • High-performance and highly functional power supply Triangular wave oscillator for easy dead time setting Application Feed forward regulator, fly-back regulator REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 1 of 40 M51995AP/AFP Recommended Operating Conditions • Supply voltage range: 12 to 36 V • Operating frequency: less than 500 kHz • Oscillator frequency setting resistance T-ON pin resistance RON: 10 k to 75 kΩ T-OFF pin resistance ROFF: 2 k to 30 kΩ Block Diagram VCC F/B DET GND 7.1 V 5.8 V ON/OFF Under voltage lockout 3k 15.2 k Voltage regulator 1S 500 6S − OP AMP 1S OVP (shut down) + 1S 2.5 V Latch Collector PWM Comparator PWM latch VOUT Emitter Oscillator capacitance CF Oscillator resistance T-ON (ON duty) Oscillator (triangle) +Current limit latch −Current limit latch CLM+ +Current limit CLM− −Current limit Oscillator resistance T-OFF (OFF duty) Intermittent action and OSC control Intermittent action VF REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 2 of 40 CT Intermittent operation determine capacitance M51995AP/AFP Pin Arrangement M51995AP Collector 1 16 VCC VOUT 2 15 CLM+ Emitter 3 14 CLM− VF 4 13 GND ON/OFF 5 12 CT OVP 6 11 T-OFF DET 7 10 CF F/B 8 9 T-ON (Top view) Outline: PRDP0016AA-A (16P4) M51995AFP Collector 1 20 VCC VOUT 2 19 CLM+ Emitter 3 18 CLM− VF 4 17 GND 5 16 6 15 ON/OFF 7 14 CT OVP 8 13 T-OFF DET 9 12 CF F/B 10 11 T-ON Heat sink pin Heat sink pin (Top view) Outline: PRSP0020DA-A (20P2N-A) Note: Connect the heat sink pin to GND. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 3 of 40 M51995AP/AFP Absolute Maximum Ratings Item Supply voltage Collector voltage Output current VCC VC IO Symbol VF terminal voltage ON/OFF terminal voltage CLM−terminal voltage CLM+terminal voltage OVP terminal current DET terminal voltage DET terminal input current F/B terminal voltage T-ON terminal input current T-OFF terminal input current Power dissipation Thermal derating factor Operating temperature Storage temperature Junction temperature VVF VON/OFF VCLM− VCLM+ IOVP VDET IDET VFB ITON ITOFF Pd Kθ Topr Tstg Tj Ratings 36 36 ±2 ±0.15 VCC VCC −4.0 to +4.0 −0.3 to +4.0 8 6 5 0 to 10 −1 −2 1.5 12 −30 to +85 −40 to +125 150 Unit V V A V V V V mA V mA V mA mA W mW/°C °C °C °C Conditions Peak Continuous Ta = 25°C Ta > 25°C Notes: 1. “+” sign shows the direction of current flow into the IC and “−” sign shows the current flow from the IC. 2. This terminal has the constant voltage characteristic of 6 to 8 V, when current is supplied from outside. The maximum allowable voltage is 6 V when the constant voltage is applied to this terminal. And maximum allowable current into this terminal is 5 mA. 3. The low impedance voltage supply should not be applied to the OVP terminal. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 4 of 40 M51995AP/AFP Electrical Characteristics (VCC = 18 V, Ta = 25°C, unless otherwise noted) Block Supply voltage circuit current Item Operating supply voltage range Operation start-up voltage Operation stop voltage Difference voltage between operation start and stop Stand-by current ON/OFF F/B Detection OVP Symbol VCC VCC(START) VCC(STOP) ∆VCC ICCL Limits Typ. Max. Unit VCC(STOP) — 35 V 15.2 9.0 5.0 16.2 9.9 6.3 17.2 10.9 7.6 V V V 50 90 140 µA VCC = 14.5V, Ta = 25°C 40 90 190 µA 15 1.31 90 1.35 160 2.0 21 5.0 140 2.0 240 3.0 mA mA µA mA µA mA VCC = 14.5V, −30 ≤ Ta ≤ 85°C VCC = 30V VCC = 25V VCC = 14V VCC = 25V VCC = 14V VCC = 25V Min. Test Conditions ∆VCC = VCC(START) − VCC(STOP) Operating circuit current Circuit current in OFF state ICCO ICC OFF Circuit current in timer OFF state ICC CT Circuit current in OVP state ICC OVP 10 0.95 50 0.95 — 1.3 ON/OFF terminal high threshold voltage VTHH ON/OFF 125 2.1 200 2.6 310 3.1 µA V ON/OFF terminal low threshold voltage VTHL ON/OFF 1.9 2.4 2.9 V ON/OFF terminal hysteresis voltage Current at 0% duty ∆VTHON/OFF 0.1 0.2 3.0 V IFBMIND −2.1 −1.54 −1.0 mA F/B terminal input current Current at maximum duty IFBMAXD −0.90 −0.55 −0.40 mA F/B terminal input current Current difference between max and 0% duty Terminal voltage ∆IFB −1.35 −0.99 −0.70 mA ∆IFB = IFBMIND − IFBMAXD VFB 4.9 5.9 7.1 V 600 2.5 1.0 780 2.6 3.0 Ω V µA Terminal resistance RFB Detection voltage VDET Input current of detection amp IINDET 420 2.4 — Voltage gain of detection amp GAVDET 30 40 — dB OVP terminal H threshold voltage VTHOVPH 540 750 960 mV OVP terminal hysteresis voltage ∆VTHOVP — 30 — mV OVP terminal threshold current OVP terminal input current OVP reset supply voltage ITHOVP 80 150 250 µA IINOVP VCCOVPC 80 7.5 150 9.0 250 10.0 µA V Difference supply voltage between operation stop and OVP reset VCC(STOP) – VCCOVPC 0.55 1.20 — V Current from OVP terminal for OVP reset ITHOVPC −480 −210 –320 −140 –213 −93 µA REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 5 of 40 VCC = 9.5V F/B terminal input current = 0.95mA VDET = 2.5V ∆VTHOVP = VTHOVPH − VTHOVPL VOVP = 400mV OVP terminal is open. (high impedance) VCC = 30V VCC = 18V M51995AP/AFP (VCC = 18 V, Ta = 25°C, unless otherwise noted) Block Timer CLM− CLM+ Oscillator VF Item fTIMER ITIMECH Min. Max. Unit 0.27 −193 0.40 −138 0.60 −102 Hz µA −178 −147 −127 −105 −94 −78 7.0 −220 8.7 −200 11.0 −180 — mV −125 120 −90 — µA ns VCLM– = −0.1V Test Conditions CT = 4.7µF VCT = 3.3V, Ta = −5°C Ta = 25°C Ta = 85°C OFF time/ON time ratio TIMEOFF/ON CLM−terminal threshold voltage CLM−terminal current VTHCLM− Delay time from CLM− to VOUT TPDCLM− −170 — CLM+ terminal threshold voltage CLM+ terminal current VTHCLM+ 180 200 220 mV −5 ≤ Ta ≤ 85°C IINCLM+ TPDCLM+ −270 — −205 90 −140 — µA ns VCLM+ = 0V Delay time from CLM+ to VOUT Oscillating frequency Maximum ON duty fosc TDUTY 170 47.0 188 50.0 207 53.0 kHz % Upper limit voltage of oscillation waveform VOSCH 3.97 4.37 4.77 V RON = 20kΩ, ROFF = 17kΩ CF = 220pF, −5 ≤ Ta ≤ 85°C fOSC = 188kHz Lower limit voltage of oscillation waveform VOSCL 1.76 1.96 2.16 V fOSC = 188kHz Voltage difference between upper limit and lower limit of OSC waveform ∆VOSC 2.11 2.41 2.71 V fOSC = 188kHz fOSCVF 170 188 207 kHz 108 124 143 TVFDUTY 11.0 13.7 22.0 — VTHTIME 2.7 3.0 3.3 V IVF VOL1 VOL2 — — — 2 0.05 0.7 6 0.4 1.4 µA V V VOL3 VOL4 VOH1 — — 16.0 0.69 1.3 16.5 1.0 2.0 — V V V VOH2 15.5 16.0 — V TRISE TFALL — — 50 35 — — ns ns OSC frequency in CLM operating state Duty in CLM operating state Output Symbol Timer frequency Timer charge current Limits Typ. VF = 5V IINCLM− VF = 2V VF = 0.2V VF voltage at timer operating start VF terminal input current Output low voltage Output high voltage Output voltage rise time Output voltage fall time REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 6 of 40 −5 ≤ Ta ≤ 85°C RON = 20kΩ, ROFF = 17kΩ CF = 220pF Min off duty/Max on duty Source current VCC = 18V, IO = 10mA VCC = 18V, IO = 100mA VCC = 5V, IO = 1mA VCC = 5V, IO = 100mA VCC = 18V, IO = −10mA VCC = 18V, IO = −100mA No load No load M51995AP/AFP Main Characteristics Thermal Derating (Maximum Rating) Circuit Current vs. Supply Voltage (Normal Operation) 22 m 1500 Circuit Current ICC (mA) Power Dissipation Pd (mW) 1800 1200 900 600 300 0 25 50 75 85 100 125 16 m 14 m 12 m fOSC = 100 kHz 10 m 100 µ Ta = 25 °C Ta = 85 °C Ta = −30 °C 50 µ 0 150 10 Circuit Current vs. Supply Voltage (OFF State) Circuit Current ICC (mA) Ta = 25 °C Ta = 85 °C Ta = −30 °C 5.0 4.0 40 Circuit Current vs. Supply Voltage (OVP Operation) 3.2 6.0 30 Supply Voltage VCC (V) OVP reset point 8.87 V (−30 °C) 8.94 V (25 °C) 9.23 V (85 °C) 7.0 20 Ambient Temperature Ta (°C) 8.0 Circuit Current ICC (mA) fOSC = 500 kHz 0 0 3.0 2.0 1.0 Ta = 25 °C Ta = 85 °C Ta = −30 °C 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 0 0 3.2 10 20 30 40 20 30 40 Circuit Current vs. Supply Voltage (Timer OFF State) OVP Terminal Threshold Voltage vs. Ambient Temperature 1.1 2.4 2.0 1.6 1.2 0.8 0.4 1.0 0.9 10 20 30 Supply Voltage VCC (V) REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 7 of 40 40 H threshold voltage (VTHOVPH) 0.8 0.7 0.6 0.5 L threshold voltage (VTHOVPL) 0.4 0.3 0 0 10 Supply Voltage VCC (V) Ta = 25 °C Ta = 85 °C Ta = −30 °C 2.8 0 Supply Voltage VCC (V) OVP Terminal Threshold Voltage VTHOVP (V) Circuit Current ICC (mA) RON = 18 kΩ 18 m ROFF = 20 kΩ −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) 3.2 3.0 ON→OFF 2.8 2.6 2.4 OFF→ON 2.2 2.0 1.8 −60 −40 −20 20 40 60 80 100 20.0 15.0 OFF→ON 5.0 0 −60 −40 −20 0 20 40 60 80 100 Input Current of VF Terminal vs. Input Voltage Discharge Current of Timer vs. Ambient Temperature −9 −8 −7 −6 −5 −4 −3 −2 −1 0 −200 ON→OFF Ambient Temperature Ta (°C) Ta = 25 °C Ta = 85 °C Ta = −30 °C 0 25.0 Ambient Temperature Ta (°C) 1 2 3 4 5 6 7 8 9 10 Discharge Current of Timer ITIMEOFF (µA) −10 0 Threshold Current of ON/OFF Terminal vs. Ambient Temperature 18 17 16 15 14 13 12 11 10 −60 −40 −20 0 20 40 60 80 100 VF Terminal Voltage VVF (V) Ambient Temperature Ta (°C) Charge Current of Timer vs. Ambient Temperature ON and OFF Duration of Timer vs. Ambient Temperature (Intermittent Operation) 1.4 175 −180 −160 −140 −120 −100 −80 −60 −40 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 8 of 40 Timer ON…Circuit operation ON Timer OFF…Circuit operation OFF 1.3 150 Timer ON 1.2 125 Timer OFF 100 75 −60 −40 −20 0 20 40 1.1 60 1.0 80 100 Ambient Temperature Ta (°C) OFF Duration of Timer TOFF (s) 3.4 Threshold Current of ON/OFF Terminal ITHON/OFF (µA) Threshold Voltage of ON/OFF Terminal vs. Ambient Temperature ON Duration of Timer TON (ms) Charge Current of Timer ITIMEON (µA) Input Current of VF Terminal IVF (µA) Threshold Voltage of ON/OFF Terminal VTHON/OFF (V) M51995AP/AFP M51995AP/AFP Threshold Voltage of CLM+ Terminal VTHCLM+ (mV) 4.0 3.5 3.0 2.5 2.0 −60 −40 −20 Threshold Voltage of CLM+ Terminal vs. Ambient Temperature 0 20 40 60 80 100 210 205 200 195 190 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) Threshold Voltage of CLM− Terminal vs. Ambient Temperature CLM+ Terminal Current vs. CLM+ Terminal Voltage −210 −205 −200 −195 −190 −60 −40 −20 −500 0 20 40 60 300 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 CLM+ Terminal Voltage VCLM+ (V) CLM− Terminal Current vs. CLM− Terminal Voltage Output High Voltage vs. Output Source Current −200 −100 0 Ta = 25 °C Ta = 85 °C Ta = −30 °C Ambient Temperature Ta (°C) −300 0 400 80 100 Ta = 25 °C Ta = 85 °C Ta = −30 °C −400 CLM+ Terminal Current IINCLM+ (µA) Ambient Temperature Ta (°C) Output High Voltage VCC-VOH (V) CLM− Terminal Current IINCLM− (µA) Threshold Voltage of CLM− Terminal VTHCLM− (mV) VF Threshold Voltage for Timer (V) VF Threshold Voltage for Timer vs. Ambient Temperature −0.2 −0.4 −0.6 −0.8 −1.0 CLM− Terminal Voltage VCLM− (V) REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 9 of 40 2.6 VCC = 18 V 2.4 Ta = 25°C 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 1m 10 m 100 m 1 Output Source Current IOH (A) 10 M51995AP/AFP Output Low Voltage vs. Output Sink Current Detection Voltage VDET (V) 4.0 3.0 VCC = 18 V VCC = 5 V 2.0 1.0 0 1m Input Current of Detection AMP IINDET (µA) 2.56 Ta = 25°C 10 m 100 m 1 2.54 2.52 2.50 2.48 2.46 2.44 2.42 2.40 −60 −40 −20 10 20 40 60 80 100 Ambient Temperature Ta (°C) Input Current of Detection AMP vs. Ambient Temperature Detection AMP Voltage Gain vs. Frequency 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 −60 −40 −20 0 20 40 60 80 100 50.0 40.0 30.0 20.0 10.0 0 100 1k 10 k 100 k 1M 10 M Frequency f (Hz) Ambient Temperature Ta (°C) ON Duty vs. F/B Terminal Input Current ON Duty vs. F/B Terminal Input Current 50 50 30 20 10 (fOSC = 200 kHz) RON = 18 kΩ ROFF = 20 kΩ Ta = 25 °C Ta = 85 °C Ta = −30 °C 40 ON Duty (%) (fOSC = 100 kHz) RON = 18 kΩ ROFF = 20 kΩ Ta = 25 °C Ta = 85 °C Ta = −30 °C 40 ON Duty (%) 0 Output Sink Current IOL (A) Detection AMP Voltage Gain GDET (dB) Output Low Voltage VOL (V) 5.0 Detection Voltage vs. Ambient Temperature 30 20 10 0 0 0 0.5 1.0 1.5 2.0 2.5 F/B Terminal Input Current IF/B (mA) REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 10 of 40 0 0.5 1.0 1.5 2.0 2.5 F/B Terminal Input Current IF/B (mA) M51995AP/AFP 50 (fOSC = 500 kHz) RON = 18 kΩ ROFF = 20 kΩ Ta = 25 °C Ta = 85 °C Ta = −30 °C 40 ON Duty (%) Upper & Lower Limit Voltage of OSC vs. Ambient Temperature 30 20 10 0 0 0.5 1.0 1.5 2.0 Upper & Lower Limit Voltage of OSC VOSCH, VOSCL (V) ON Duty vs. F/B Terminal Input Current 2.5 5.4 RON = 18 kΩ 5.2 ROFF = 20 kΩ 4.8 4.4 4.0 fOSC = 100 kHz fOSC = 200 kHz fOSC = 500 kHz 2.2 2.0 1.8 1.6 −60 −40 −20 F/B Terminal Input Current IF/B (mA) 20 40 60 80 100 ON Duty vs. ROFF 10000 100 90 80 ON Duty (%) 1000 RON = 22 kΩ 100 ROFF = 12 kΩ RON = 36 kΩ ROFF = 6.2 kΩ RON = 24 kΩ ROFF = 20 kΩ 10 RON = 75 kΩ 70 60 51 kΩ 50 36 kΩ 24 kΩ 22 kΩ 18 kΩ 15 kΩ 40 30 10 kΩ 20 10 1 1 3 10 3 100 3 0 1000 3 10000 1 3 5 7 10 3 5 7 100 CF Terminal Capacity (pF) ROFF (kΩ) Oscillating Frequency vs. Ambient Temperature Oscillating Frequency vs. Ambient Temperature 120 RON = 24 kΩ ROFF = 20 kΩ CF = 330 pF 110 100 90 80 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 11 of 40 Oscillating Frequency fOSC (kHz) Oscillating Frequency fOSC (kHz) 0 Ambient Temperature Ta (°C) Oscillating Frequency vs. CF Terminal Capacity Oscillating Frequency fOSC (kHz) fOSC = 500 kHz fOSC = 200 kHz fOSC = 100 kHz 700 RON = 24 kΩ ROFF = 20 kΩ CF = 47 pF 600 500 400 300 200 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) M51995AP/AFP ON Duty vs. Ambient Temperature ON Duty vs. Ambient Temperature 100 100 (fOSC = 100 kHz) 90 RON = 24 kΩ, ROFF = 20 kΩ 50 40 30 RON = 22 kΩ, ROFF = 22 kΩ 0 20 40 60 30 RON = 22 kΩ, ROFF = 22 kΩ RON = 18 kΩ, ROFF = 24 kΩ RON = 15 kΩ, ROFF = 27 kΩ 0 20 40 60 80 100 ON Duty vs. Ambient Temperature Input Voltage of Terminal vs. Expansion Rate of Period 80 RON = 36 kΩ, ROFF = 6.2 kΩ 70 RON = 22 kΩ, ROFF = 12 kΩ 60 RON = 24 kΩ, ROFF = 20 kΩ 50 40 30 RON = 22 kΩ, ROFF = 22 kΩ RON = 18 kΩ, ROFF = 24 kΩ RON = 15 kΩ, ROFF = 27 kΩ 0 −60 −40 −20 0 20 40 60 Input Voltage of Terminal VVF (V) Ambient Temperature Ta (°C) 90 80 100 5.0 (fOSC = 100 kHz) (1) RON = 15 kΩ, ROFF = 27 kΩ (2) RON = 18 kΩ, ROFF = 24 kΩ (3) RON = 22 kΩ, ROFF = 22 kΩ (4) RON = 24 kΩ, ROFF = 20 kΩ (5) RON = 22 kΩ, ROFF = 12 kΩ (6) RON = 36 kΩ, ROFF = 6.2 kΩ 4.0 3.0 2.0 1.0 (2) 0 0 (1) 2 4 (3) (4) (5) 6 (6) 8 10 12 14 16 18 20 Ambient Temperature Ta (°C) Expansion Rate of Period (Times) Input Voltage of Terminal vs. Expansion Rate of Period OVP Terminal Input Current vs. Input Voltage 5.0 (fOSC = 500 kHz) (1) RON = 15 kΩ, ROFF = 27 kΩ (2) RON = 18 kΩ, ROFF = 24 kΩ (3) RON = 22 kΩ, ROFF = 22 kΩ (4) RON = 24 kΩ, ROFF = 20 kΩ (5) RON = 22 kΩ, ROFF = 12 kΩ (6) RON = 36 kΩ, ROFF = 6.2 kΩ 4.0 3.0 2.0 1.0 (2) (1) 0 0 40 0 −60 −40 −20 80 100 (fOSC = 500 kHz) 10 RON = 24 kΩ, ROFF = 20 kΩ 50 Ambient Temperature Ta (°C) 100 20 RON = 22 kΩ, ROFF = 12 kΩ 60 10 RON = 15 kΩ, ROFF = 27 kΩ 0 −60 −40 −20 RON = 36 kΩ, ROFF = 6.2 kΩ 70 20 RON = 18 kΩ, ROFF = 24 kΩ 10 ON Duty (%) ON Duty (%) RON = 22 kΩ, ROFF = 12 kΩ 60 20 Input Voltage of Terminal VVF (V) 80 RON = 36 kΩ, ROFF = 6.2 kΩ 70 2 4 (3) (4) (5) 6 (6) 8 10 12 14 16 18 20 Expansion Rate of Period (Times) REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 12 of 40 OVP Terminal Input Current IOVP (A) ON Duty (%) 80 (fOSC = 200 kHz) 90 1m Ta = 25 °C Ta = 85 °C Ta = −30 °C 100 µ 10 µ 1µ 0.2 0.4 0.6 0.8 1.0 OVP Terminal Input Voltage VOVP (V) Current from OVP Terminal for OVP Reset ITHOVPC (µA) M51995AP/AFP Current from OVP Terminal for OVP Reset vs. Supply Voltage 800 Ta = 25 °C Ta = 85 °C Ta = −30 °C 700 600 500 400 300 200 100 0 0 5 10 15 20 25 30 35 40 Supply Voltage VCC (V) Output Through Current Waveform at Rising Edge of Output Pulse Output Through Current Waveform at Falling Edge of Output Pulse Horizontal-axis: 20 ns/div Vertical-axis: 50 mA/div Horizontal-axis: 20 ns/div Vertical-axis: 10 mA/div REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 13 of 40 M51995AP/AFP Application Example (1) Example application circuit diagram of feed forward regulator + + VOUT2 AC + C FIN R1 A 1 + 16 2 + M51995AP 4 CVCC 5 3 14 13 15 9 10 11 12 8 6 R2 7 OVP + + CT CF VOUT1 F/B A RON ROFF ON/OFF Note: Pin No. is related with M51995AP (2) Example application circuit diagram of fly-back regulator +C R1 FIN AC + 1 2 16 M51995AP R21 4 VOUT OVP F/B + CVCC 5 3 14 13 15 9 10 11 12 8 6 R22 CF RON REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 14 of 40 7 ROFF Note: Pin No. is related with M51995AP M51995AP/AFP (3) Feed forward types SMPS with multi-output + + VOUT2 AC + R1 CFIN A Collector VCC VOUT R2 CVCC VOUT1 DET OVP F/B + + ON/OFF CT T-ON CF T-OFF CLM+ GND CLM− VF Emitter M51995AP + CF CT OVP + F/B A REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 15 of 40 RON ROFF ON/OFF M51995AP/AFP Function Description Type M51995AP and M51995AFP are especially designed for off-line primary PWM control IC of switching mode power supply (SMPS) to get DC voltage from AC power supply. Using this IC, smart SMPS can be realized with reasonable cost and compact size as the number of external electric parts can be reduced and also parts can be replaced by reasonable one. In the following circuit diagram, MOS FET is used for output transistor, however bipolar transistor can be used with no problem. Start-up Circuit Section The start-up current is such low current level as typical 90 µA, as shown in figure 1, when the VCC voltage is increased from low level to start-up voltage VCC(START). Circuit Current ICC (mA) In this voltage range, only a few parts in this IC, which has the function to make the output voltage low level, is alive and ICC current is used to keep output low level. The large voltage difference between VCC(START) and VCC(STOP) makes start-up easy, because it takes rather long duration from VCC(START) to VCC(STOP). ICCO ≈ 14 mA ICCL ≈ 90 µA VCC VCC (STOP) (START) ≈ 9.9 V ≈ 16.2 V Supply Voltage VCC (V) Figure 1 Circuit Current vs. Supply Voltage REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 16 of 40 M51995AP/AFP Oscillator Section The oscillation waveform is the triangle one. The ON-duration of output pulse depends on the rising duration of the triangle waveform and dead-time is decided by the falling duration. The rising duration is determined by the product of external resistor RON and capacitor CF and the falling duration is mainly determined by the product of resistor ROFF and capacitor CF. VOSCH ≈ 4.4 V Waveform of CF terminal VOSCL ≈ 2.0 V Waveform of VOUT terminal in Max ON dutycondition VOH VOL Figure 2 OSC Waveform at Normal Condition (no-operation of intermittent action and OSC control circuit) 1. Oscillator operation when intermittent action and OSC control circuit does not operate Figure 3 shows the equivalent charging and discharging circuit diagram of oscillator when the current limiting circuit does not operate. It means that intermittent action and OSC control circuit does not operate. The current flows through RON from the constant voltage source of 5.8 V. CF is charged up by the same amplitude as RON current, when internal switch SW1 is switched to “charging side”. The rise rate of CF terminal is given as ≈ VT-ON RON × CF (V/s) ………………………………………… (1) where VT-ON ≈ 4.5 V The maximum on duration is approximately given as ≈ (VOSCH − VOSCL) × RON × CF (s) ………………… (2) VT-ON where VOSCH ≈ 4.4 V VOSCL ≈ 2.0 V CF is discharged by the summed-up of ROFF current and one sixteenth (1/16) of RON current by the function of Q2, Q3 and Q4 when SW1, SW2 are switched to “discharge side”. So fall rate of CF terminal is given as ≈ VT-OFF ROFF × CF + VT-ON 16 × RON × CF (V/s) ………………… (3) The minimum off duration approximately is given as ≈ (VOSCH − VOSCL) × CF VT-OFF ROFF + VT-ON (s) …………………… (4) 16 × RON where VT−OFF ≈ 3.5 V The cycle time of oscillation is given by the summation of equations 2 and 4. The frequency including the dead-time is not influenced by the temperature because of the built-in temperature compensating circuit. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 17 of 40 M51995AP/AFP 5.8 V Q4 1/16 T-ON Q1 Charging SW1 Q3 RON T-OFF From VF signal Vz = 4.2 V ROFF SW2 CF Switched by charging and discharging signal CF Q2 Discharging M51995A Figure 3 Schematic Diagram of Charging and Discharging Control Circuit for OSC Capacitor CF 2. Oscillator operation when intermittent action and OSC control circuit operates. When over current signal is applied to CLM+ or CLM− terminal, and the current limiting circuit, intermittent action and OSC control circuit starts to operate. In this case T-OFF terminal voltage depends on VF terminal voltage, so the oscillation frequency decreases and dead-time spreads. The rise rate of oscillation waveform is given as ≈ VT-ON RON × CF (V/s) ………………………………………… (5) The fall rate of oscillation waveform is given as ≈ VVF − VVFO ROFF × CF + VT-ON 16 × RON × CF (V/s) ………………… (6) where VT-ON ≈ 4.5 V VVF ; VF terminal voltage VVFO ≈ 0.4 V VVF − VFO = 0 if VVF − VVFO < 0 VVF − VVFO = VT-OFF if VVF – VVFO > VT−OFF ≈ 3.5 V So when VVF > 3.5 V, the operation is just same as that in the no current limiting operation state. The maximum on-duration is just same as that in the no-operation state of intermittent and oscillation control circuit and is given as follows; ≈ (VOSCH − VOSCL) × ROFF × CF VT-ON (s) ………………… (7) The minimum off-duration is approximately given as; ≈ (VOSCH − VOSCL) × CF VVF − VVFO ROFF × CF + VT-ON (s) ………………… (8) 16 × RON × CF The oscillation period is given by the summation of equation (7) and (8). REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 18 of 40 M51995AP/AFP As shown in figure 5, the internal circuit kills the first output pulse in the output waveform. The output waveform will appear from the second pulse cycle because the duration of first cycle takes CF charging time longer comparing with that at the stable operating state. Usually the applied voltage to VF terminal must be proportional the output voltage of the regulator. So when the over current occurs and the output voltage of the regulator becomes low, the off-duration becomes wide. There are two methods to get the control voltage, which depends on the output voltage, on primary side. For the fly back type regulator application, the induced voltage on the third or bias winding is dependent on output voltage. On the other hand, for the feed forward type regulator application, it can be used that the output voltage depends on the product of induced voltage and “on-duty”, as the current of choke coil will continue at over load condition, it means the “continuous current” condition. Figure 6 shows one of the examples for VF terminal application for the feed forward type regulator. VOSCH ≈ 4.4 V Voltage waveform of CF terminal VOSCL ≈ 2.0 V Voltage waveform of output terminal at Max ON duty VOH VOL Figure 4 OSC Waveform with Operation of Intermittent and OSC Control Circuit Operation Start from 0 V Voltage waveform of VOSCH CF terminal VOSCL 0 First pulse Voltage waveform of output terminal at Max ON duty VOH No generate pulse VOL 0 Operation start Figure 5 Relation between OSC and Output Waveform Circuit Operation at Start-up M51995A VOUT RVFFB VF CVFFB Figure 6 Feedback Loop with Low Pass Filter from Output to VF Terminal REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 19 of 40 M51995AP/AFP PWM Comparator and PWM Latch Section Figure 7 shows the PWM comparator and latch section. The on-duration of output waveform coincides with the rising duration of CF terminal waveform, when the infinitive resistor is connected between F/B terminal and GND. When the F/B terminal has finite impedance and current flows out from F/B terminal, “A” point potential shown in figure 7 depends on this current. So the “A” point potential is close to GND level when the flow-out current becomes large. “A” point potential is compared with the CF terminal oscillator waveform and PWM comparator, and the latch circuit is set when the potential of oscillator waveform is higher than “A” point potential. On the other hand, this latch circuit is reset by high level signal during the dead-time of oscillation (falling duration of oscillation waveform). So the “B” point potential or output waveform of latch circuit is the one shown in figure 8. The final output waveform or “C” point potential is got by combining the “B” point signal and dead-time signal logically. (please refer to figure 8) ≈ 7.1 V 15.2 k 3k 500 Ω 5.8 V 6S Point A 200 µA − + 1S Latch Point B Point C PWM COMP. F/B To output From OSC M51995A CF Figure 7 PWM Comparator and Latch Circuit OSC waveform Point A Waveform of OSC & point A Point B Point C Figure 8 Waveforms of PWM Comparator Input point A, Latch Circuit Points B and C REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 20 of 40 M51995AP/AFP Current Limiting Section When the current-limit signal is applied before the crossing instant of “A” pint potential and CF terminal voltage shown in figure 7, this signal makes the output “off” and the off state will continue until next cycle. Figure 9 shows the timing relation among them. The current limiting circuit has two input terminals, one has the detector-sensitivity of +200 mV to the GND terminal and the other has −200 mV. The circuit will be latched if the input signal is over the limit of either terminal. If the current limiting circuit is set, no waveform is generated at output terminal however this state is reset during the succeeding dead-time. So this current limiting circuit is able to have the function in every cycle, and is named “pulse-by-pulse current limit”. It is rather recommended to use not "CLM+" but "CLM−" terminal, as the influence from the gate drive current of MOS FET can be eliminated and wide voltage rating of +4 V to −4 V is guaranteed for absolute maximum rating. There happen some noise voltage on RCLM during the switching of power transistor due to the snubber circuit and stray capacitor of the transformer windings. To eliminate the abnormal operation by the noise voltage, the low pass filter, which consists of RNF and CNF is used as shown in figure 10. It is recommended to use 10 to 100 Ω for RNF because such range of RNF is not influenced by the flow-out current of some 200 µA from CLM terminal and CNF is designed to have the enough value to absorb the noise voltage. OSC waveform of CF terminal VTHCLM ≈ 200 mV Waveform of CLM+ terminal Current limit signal to set latch Waveform of VOUT terminal (a) +current limit OSC waveform of CF terminal Waveform of CLM− terminal VTHCLM ≈ −200 mV Current limit signal to set latch Waveform of VOUT terminal (b) −current limit Figure 9 Operating Waveforms of Current Limiting Circuit REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 21 of 40 M51995AP/AFP + + M51995A M51995A VOUT VOUT RNF GND CLM+ CNF CNF RCLM GND RCLM CLM− RNF (b) In case of CLM− (a) In case of CLM+ Figure 10 How to Connect Current Limit Circuit Intermittent Action and Oscillation Control Section When the internal current limiting circuit states to operate and also the VF level decreases to lower than the certain level of some 3 V, the dead-time spreads and intermittent action and OSC control circuit (which is one of the timer-typeprotection circuit) starts to operate. The intermittent action and OSC control circuit is the one to generate the control signal for oscillator and intermittent action circuit. Figure 11 shows the timing-chart of this circuit. When the output of intermittent action and oscillation control is at “high” level, the waveform of oscillator depends on the VF terminal voltage and the intermittent action circuit begins to operate. OSC waveform of CF terminal Current limit signal Output of current limit latch Output of intermittent action and OSC control circuit (a) With current limit signal OSC waveform of CF terminal Current limit signal GND Output of current limit latch GND Output of intermittent action and OSC control circuit GND (b) Without current limit signal Figure 11 Timing Chart of Intermittent and OSC Control Circuit REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 22 of 40 M51995AP/AFP Intermittent Action Circuit Section Intermittent action circuit will start to operate when the output signal from the intermittent action and oscillation control circuit are “high” and also VF terminal voltage is lower than VTHTIME of about 3 V. Figure 12 shows the block diagram of intermittent action circuit. Transistor Q is on state when VF terminal voltage is higher than VTHTIME of about 3 V, so the CT terminal voltage is near to GND potential. When VF terminal voltage is lower than VTHTIME, Q becomes “off” and the CT has the possibility to be charged up. Under this condition, if the intermittent action and oscillation control signal become “high” the switch SWA will close only in this “high” duration and CT is charged up by the current of 120 µA through SWA (SWB is open) and CT terminal potential will rise. The output pulse can be generated only this duration. When the CT terminal voltage reaches to 8 V, the control logic circuit makes the SWA “off” and SWB “on”, in order to flow in the ITIMEOFF of 15 µA to CT terminal. The IC operation will be ceased in the falling duration. On the other hand, when CT terminal voltage decreases to lower than 2 V, the IC operation will be reset to original state, as the control logic circuit makes the SWA “on” and SWB “off”. Therefore the parts in power circuit including secondary rectifier diodes are protected from the overheat by the over current. ITIMEON (≈ 120 µA) VTHTIME (≈ 3 V) A CT VF − + SWA Control logic SWB Q B + ITIMEOFF (≈ 15 µA) CT Figure 12 Block Diagram of Intermittent Action Circuit No operating duration 8V 2V Figure 13 Waveform of CT Terminal Figure 14 shows the ICC versus VCC in this timer-off duration. In this duration the power is not supplied to IC from the third winding of transformer but through from the resistor R1 connected to VCC line. If the R1 shown in Application Example is selected adequate value, VCC terminal voltage will be kept at not so high or low but adequate value, as the ICC versus VCC characteristics has such the one shown in figure 14. To ground the CT terminal is recommended, when the intermittent mode is not used. In this case the oscillated frequency will become low but the IC will neither stop the oscillation nor change to the intermittent action mode, when the current limit function becomes to operate and the VF terminal voltage becomes low. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 23 of 40 M51995AP/AFP Circuit Current ICC (mA) 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 Supply Voltage VCC (V) Figure 14 ICC vs. VCC in Timer-off Duration of Intermittent Action Circuit Voltage Detector Circuit (DET) Section The DET terminal can be used to control the output voltage which is determined by the winding ratio of fly back transformer in fly-back system or in case of common ground circuit of primary and secondary in feed forward system. The circuit diagram is quite similar to that of shunt regulator type 431 as shown in figure 15. As well known from figure 15 and figure 16, the output of OP AMP has the current-sink ability, when the DET terminal voltage is higher than 2.5 V but it becomes high impedance state when lower than 2.5 V DET terminal and F/B terminal have inverting phase characteristics each other, so it is recommended to connect the resistor and capacitor in series between them for phase compensation. It is very important, one can not connect by resistor directly as there is the voltage difference between them and the capacitor has the DC stopper function. ≈ 7.1 V 3k 1S 500 Ω 6S F/B DET 5.4 k 10.8 k 10.8 k 10 S 1.2 k Figure 15 Equivalent Circuit Diagram of Voltage Detector REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 24 of 40 M51995AP/AFP ≈ 7.1 V 3k 1S 500 Ω 6S F/B − DET OP AMP + 2.5 V Figure 16 Equivalent Circuit Diagram of Voltage Detector ON-OFF Circuit Section Figure 17 shows the circuit diagram of ON-OFF circuit. The current flown into the ON-OFF terminal makes the Q4 “on” and the switching operation stop. On the other hand, the switching operation will recover as no current flown into ON/OFF terminal makes Q4 “off”. As the constant current source connected to Q4 base terminal has such the hysteresis characteristics of 20 µA at operation and 3 µA at stopping. So the unstable operation is not appeared even if the ON/OFF terminal voltage signal varies slowly. 2k ON/OFF Q1 Q2 Q3 Q4 Operate stop at Q4 ON I: 3 µA at stopping I: 20 µA at operating I Figure 17 ON/OFF Circuit Figure 18 shows how to connect the ON/OFF terminal. The switching operation will stop by switch-off and operate by switch-on. Transistor or photo transistor can be replaced by this switch, of course. No resistor of 30 to 100 kΩ is connected and ON/OFF terminal is directly connected to GND, when it is not necessary to use the ON/OFF operation. Figure 19 shows the ICC versus VCC characteristics in OFF state and VCC will be kept at not so high or low but at the adequate voltage, when R1 shown in Application Example is selected properly. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 25 of 40 M51995AP/AFP VCC M51995A 30 k to 100 kΩ ON/OFF Figure 18 Connecting of ON/OFF Terminal Circuit Current ICC (mA) 1.6 1.2 0.8 0.4 0 0 5 10 15 20 25 30 Supply Voltage VCC (V) Figure 19 ICC vs. VCC in OFF State OVP Circuit (Over Voltage Protection Circuit) Section OVP circuit is basically positive feedback circuit constructed by Q2, Q3 as shown in figure 20. Q2, Q3 turn on and the circuit operation of IC stops, when the input signal is applied to OVP terminal. (threshold voltage ≈ 750 mV) The current value of I2 is about 150 µA when the OVP does not operates but it decreases to about 2 µA when OVP operates. It is necessary to input the sufficient larger current (800 µA to 8 mA) than I2 for triggering the OVP operation. The reason to decrease I2 is that it is necessary that ICC at the OVP rest supply voltage is small. It is necessary that OVP state holds by circuit current from R1 in the application example, so this IC has the characteristic of small ICC at the OVP reset supply voltage (≈stand-by current +20 µA) On the other hand, the circuit current is large in the higher supply voltage, so the supply voltage of this IC doesn’t become so high by the voltage drop across R1. This characteristic is shown in figure 21. The OVP terminal input current in the voltage lower than the OVP threshold voltage is based on I2 and the input current in the voltage higher than the OVP threshold voltage is the sum of the current flowing to the base of Q3 and the current flowing from the collector of Q2 to the base. For holding in the latch state, it is necessary that the OVP terminal voltage is kept in the voltage higher than VBE of Q3. So if the capacitor is connected between the OVP terminal and GND, even though Q2 turns on in a moment by the surge voltage, etc. this latch action does not hold if the OVP terminal voltage does not become higher than VBE of Q3 by charging this capacitor. For resetting OVP state, it is necessary to make the OVP terminal voltage lower than the OVP L threshold voltage or make VCC lower than the OVP reset supply voltage. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 26 of 40 M51995AP/AFP As the OVP reset voltage is settled on the rather high voltage of 9.0 V, SMPS can be reset in rather short time from the switch-off of the AC power source if the smoothing capacitor is not so large value. VCC 7.8 V 100 µA 8k I1 12 k Q1 Q2 400 OVP Q3 2.5 k I2 GND Note: I1 = 0 when OVP operates Figure 20 Detail Diagram of OVP Circuit Circuit Current ICC (mA) 8 Ta = 25 °C Ta = 85 °C Ta = −30 °C 7 6 OVP reset point 8.82 V (−30 °C) 8.97 V (25 °C) 9.07 V (85 °C) 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 Supply Voltage VCC (V) Figure 21 Circuit Current vs. Supply Voltage (OVP Operation) Output Section It is required that the output circuit has the high sink and source abilities for MOS FET drive. It is well known that the totempole circuit has high sink and source ability. However, it has the demerit of high through current. For example, the through current may reach such the high current level of 1 A, if type M51995A has the “conventional” totempole circuit. For the high frequency application such as higher than 100 kHz, this through current is very important factor and will cause not only the large ICC current and the inevitable heat-up of IC but also the noise voltage. This IC uses the improved totempole circuit, so without deteriorating the characteristic of operating speed, its through current is approximately 100 mA. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 27 of 40 M51995AP/AFP Application Note of Type M51995AP/AFP Design of Start-up Circuit and the Power Supply of IC 1. The start-up circuit when it is not necessary to set the start and stop input voltage Rectified DC voltage from smoothing capacitor Main transformer R1 VF VCC M51995A Third winding or bias winding + CVCC GND Figure 22 Start-up Circuit Diagram (when it is not necessary to set the start and stop input voltage) Figure 22 shows one of the example circuit diagram of the start–up circuit which is used when it is not necessary to set the start and stop voltage. It is recommended that the current more than 300 µA flows through R1 in order to overcome the operation start-up current ICC(START) and CVCC is in the range of 10 to 47 µF. The product of R1 by CVCC causes the time delay of operation, so the response time will be long if the product is too much large. Just after the start-up, the ICC current is supplied from CVCC, however, under the steady state condition, IC will be supplied from the third winding or bias winding of transformer, the winding ratio of the third winding must be designed so that the induced voltage may be higher than the operation-stop voltage VCC(STOP). The VCC voltage is recommended to be 12 V to 17 V as the normal and optimum gate voltage is 10 to 15 V and the output voltage (VOH) of type M51995AP/AFP is about (VCC − 2 V). It is not necessary that the induced voltage is settled higher than the operation start-up voltage VCC(START), and the high gate drive voltage causes high gate dissipation, on the other hand, too low gate drive voltage does not make the MOS FET fully on-state or the saturation state. 2. The start-up circuit when it is not necessary to set the start and stop input voltage It is recommend to use the third winding of “forward winding” or “positive polarity” as shown in figure 23, when the DC source voltages at both the IC operation start and stop must be settled at the specified values. The input voltage (VIN(START)), at which the IC operation starts, is decided by R1 and R2 utilizing the low start-up current characteristics of type M51995AP/AFP. The input voltage (VIN(STOP)), at which the IC operation stops, is decided by the ratio of third winding of transformer. The VIN(START) and VIN(STOP) are given by following equations. VIN (START) ≈ R1 × ICCL + ( R1 + 1) × VCC (START) ……… (9) R2 VIN (STOP) ≈ (VCC (STOP) − VF) × NP 1 + V'IN RIP (P-P) …… (10) NB 2 Where ICCL is the operation start-up current of IC VCC(START) is the operation start-up voltage of IC VCC(STOP) is the operation stop voltage of IC VF is the forward voltage of rectifier diode V’IN(P-P) is the peak to peak ripple voltage of VCC terminal ≈ NB V'IN RIP (P-P) NP It is required that the VIN(START) must be higher than VIN(STOP). REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 28 of 40 M51995AP/AFP When the third winding is the “fly back winding” or “reverse polarity”, the VIN(START) can be fixed, however, VIN(STOP) can not be settled by this system, so the auxiliary circuit is required. Rectified DC voltage from smoothing capacitor VIN NP Primary winding of transformer R1 VF VCC NB M51995A R2 Third winding of transformer + CVCC GND Figure 23 Start-up Circuit Diagram (when it is not necessary to set the start and stop input voltage) 3. Notice to the VCC, VCC line and GND line Collector Main transformer third winding VCC M51995A + CVCC Output RCLM Emitter GND Figure 24 How to Design the Conductor-pattern of Type M51995A on PC Board (schematic example) To avoid the abnormal IC operation, it is recommended to design the VCC is not vary abruptly and has few spike voltage, which is induced from the stray capacity between the winding of main transformer. To reduce the spike voltage, the CVCC, which is connected between VCC and ground, must have the good high frequency characteristics. To design the conductor-pattern on PC board, following cautions must be considered as shown in figure 24. (1) To separate the emitter line of type M51995A from the GND line of the IC (2) The locate the CVCC as near as possible to type M51995A and connect directly (3) To separate the collector line of type M51995A from the VCC line of the IC (4) To connect the ground terminals of peripheral parts of ICS to GND of type M51995A as short as possible REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 29 of 40 M51995AP/AFP 4. Power supply circuit for easy start-up When IC starts to operate, the voltage of the CVCC begins to decrease till the CVCC becomes to be charged from the third winding of main-transformer as the ICC of the IC increases abruptly. In case shown in figure 22 and 23, some “unstable start-up” or “fall to start-up” may happen, as the charging interval of CVCC is very short duration; that is the charging does occur only the duration while the induced winding voltage is higher than the CVCC voltage, if the induced winding voltage is nearly equal to the “operation-stop voltage” of type M51995. It is recommended to use the 10 to 47 µF for CVCC1, and about 5 times capacity bigger than CVCC1 for CVCC2 in figure 25. R1 Main transformer third winding VCC + M51995A CVCC1 + CVCC2 GND Figure 25 DC Source Circuit for Stable Start-up OVP Circuit (1) To avoid the miss operation of OVP It is recommended to connect the capacitor between OVP terminal and GND for avoiding the miss operation by the spike noise. The OVP terminal is connected with the sink current source (≈150 µA) in IC when OVP does not operate, for absorbing the leak current of the photo coupler in the application. So the resistance between the OVP terminal and GND for leak-cut is not necessary. If the resistance is connected, the supply current at the OVP reset supply voltage becomes large. As the result, the OVP reset supply voltage may become higher than the operation stop voltage. In that case, the OVP action is reset when the OVP is triggered at the supply voltage a little high than the operation stop voltage. So it should be avoided absolutely to connect the resistance between the OVP terminal and GND. 10 k VCC M51995A OVP Photo coupler + GND Figure 26 Peripheral Circuit of OVP Terminal REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 30 of 40 M51995AP/AFP 2. Application circuit to make the OVP-reset time fast The reset time may becomes problem when the discharge time constant of CFIN • (R1 + R2) is long. Under such the circuit condition, it is recommended to discharge the CVCC forcedly and to make the VCC low value. This makes the OVP-reset time fast. To main transformer R1 + + CFIN CVCC R2 VCC M51995A GND The time constant of this part should be short Figure 27 Example Circuit Diagram to Make the OVP-Reset-Time Fast 3. OVP setting method using the induced third winding voltage on fly back system For the over voltage protection (OVP), the induced fly back type third winding voltage can be utilized, as the induced third winding voltage depends on the output voltage. Figure 28 shows one of the example circuit diagram. Main transformer third winding VCC M51995A OVP 470 Ω + CVCC GND Figure 28 OVP Setting Method Using the Induced Third Winding Voltage on Fly Back System REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 31 of 40 M51995AP/AFP Current Limiting Circuit 1. Peripheral circuit of CLM+, CLM− terminal R1 CFIN + Input smoothing capacitor VCC Collector VOUT + CVCC M51995A GND RNF1 CLM+ Emitter CNF RNF2 RCLM Figure 29 Peripheral Circuit Diagram of CLM+ Terminal R1 CFIN Input smoothing capacitor + VCC Collector VOUT + CVCC M51995A Emitter GND CLM− CNF RNF2 RCLM RNF1 Figure 30 Peripheral Circuit Diagram of CLM− Terminal Figure 29 and 30 show the example circuit diagrams around the CLM+ and CLM− terminal. It is required to connect the low pass filter, as the main current or drain current contains the spike current especially during the turnon duration of MOS FET. 1,000 pF to 22,000 pF is recommended for CNF and the RNF1 and RNF2 have the functions both to adjust the “currentdetecting-sensitivity” and to consist the low pass filter. To design the RNF1 and RNF2, it is required to consider the influence of CLM terminal source current (IINCLM+ or INFCLM−), which value is in the range of 90 to 270 µA. In order to be not influenced from these resistor paralleled value of RNF1 and RNF2, (RNF1/RNF2) is recommended to be less than 100 Ω. The RCLM should be the non-inductive resistor. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 32 of 40 M51995AP/AFP 2. Over current limiting curve (1) In case of feed forward system I2 IP1 I1 IP2 CLM I2 I1 RCLM (a) Feed forward system (b) Primary and secondary current Figure 31 Primary and Secondary Current Waveforms Under the Current Limiting Operation Condition on Feed Forward System Output Voltage Figure 31 shows the primary and secondary current wave-forms under the current limiting operation. At the typical application of pulse-by-pulse primary current detecting circuit, the secondary current depends on the primary current. As the peak value of secondary current is limited to specified value, the characteristics curve of output voltage versus output current become to the one as shown in figure 32. The demerit of the pulse by pulse current limiting system is that the output pulse width can not reduce to less than some value because of the delay time of low pass filter connected to the CLM terminal and propagation delay time TPDCLM from CLM terminal to output terminal of type M51995A. The typical TPDCLM is 100 ns. As the frequency becomes higher, the delay time must be shorter. And as the secondary output voltage becomes higher, the dynamic range of on-duty must be wider; it means that it is required to make the on-duration much more narrower. So this system has the demerit at the higher oscillating frequency and higher output voltage applications. Output Current Figure 32 Over Current Limiting Curve on Feed Forward System To improve these points, the oscillating frequency is set low using the characteristics of VF terminal. When the current limiting circuit operates under the over current condition, the oscillating frequency decreases in accordance with the decrease of VF terminal voltage, if the VF is lower than 3.5V.And also the dead time becomes longer. Under the condition of current limiting operation, the output current I2 continues as shown in figure 31. So the output voltage depends on the product of the input primary voltage VIN and the on-duty. If the third winding polarity is positive, the VCC depends on VIN, so it is concluded that the smoothed voltage of VOUT terminal depends on the output DC voltage of the SMPS. So the sharp current limiting characteristics will be got, if the VOUT voltage if feed back to VF terminal through low pass filter as shown in figure 33. It is recommended to use 15 kΩ for RVFFB, and 10,000 pF for CVFFB in figure 33. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 33 of 40 M51995AP/AFP M51995A VOUT RVFFB VF CVFFB Figure 33 Feed Back Loop through Low Pass Filter from VOUT to VF Terminal Figure 34 shows how to control the knee point where the frequency becomes decrease, To VF From VOUT To VF From VOUT To VF From VOUT To make the knee point high To make the knee point low Figure 34 How to Control the Knee Point DC Output Voltage (2) In case of fly back system The DC output voltage of SMPS depends on the VCC Voltage of type M51995A when the polarity of the third winding is negative and the system is fly back. So the operation of type M51995A will stop when the VCC becomes lower than “Operation-stop voltage” of M51995A when the DC output voltage of SMPS decreases under specified value at over load condition. Point that VCC voltage or third winding voltage decreases under "Operation-Stop Voltage" DC Output Current Figure 35 Over Current Limiting Curve on Fly Back System VCC Collector R1 VF M51995A + CVCC R2 Figure 36 Circuit Diagram to make Knee Point Low on Fly Back System REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 34 of 40 M51995AP/AFP However, the M51995A will non-operate and operate intermittently, as the VCC voltage rises in accordance with the decrease of ICC current. The fly back system has the constant output power characteristics as shown in figure 35 when the peak primary current and the operating frequency are constant. To control the increase of DC output current, the operating frequency is decreased using the characteristics of VF terminal when the over current limiting function begins to operate. The voltage which mode by dividing the VCC is applied to VF terminal as shown in figure 36, as the induced third winding voltage depends on the DC output voltage of SMPS. 15 kΩ or less is recommended for R2 in figure 36, it is noticed that the current flows through R1 and R2 will superpose on the ICC(START) current. If the R1 is connected to CVCC2 in figure 25, the current flows through R1 and R2 is independent of the ICC(START). (3) Application circuit to keep the non-operating condition when over load current condition will continue for specified duration The CT terminal voltage will begin to rise and the capacitor connected to CT terminal will be charged-up, if the current limiting function starts, and VF terminal voltage decreases below VTHTIME (∼ 3 V). If the charged-up CT terminal voltage is applied to OVP terminal through the level-shifter consisted of buffer transistor and resistor, it makes type M51995A keep non-operating condition. VCC CT + CT M51995A OVP Figure 37 Application Circuit Diagram to Keep the Non-Operating Condition when Over Load Current Condition will Continue for Specified Duration Output Circuit 1. The output terminal characteristics at the VCC voltage lower than the “Operation-stop” voltage The output terminal has the current sink ability even though the VCC voltage lower than the “Operation-stop” voltage or VCC(STOP) (It means that the terminal is “Output low state” and please refer characteristics of output low voltage versus sink current.) This characteristics has the merit not to damage the MOS FET at the stop of operation when the VCC voltage decreases lower than the voltage of VCC (STOP), as the gate charge of MOS FET, which shows the capacitive load characteristics to the output terminal, is drawn out rapidly. The output terminal has the draw-out ability above the VCC voltage of 2 V, however, lower than the 2 V, it loses the ability and the output terminal potential may rise due to the leakage current. In this case, it is recommended to connect the resistor of 100 kΩ between gate and source of MOS FET as shown in figure 38. To main transformer VOUT M51995A 100 kΩ RCLM Figure 38 Circuit Diagram to Prevent the MOS FET Gate Potential Rising REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 35 of 40 M51995AP/AFP 2. MOS FET gate drive power dissipation Figure 39 shows the relation between the applied gate voltage and the stored gate charge. In the region 1, the charge is mainly stored at CGS as the depletion is spread and CGD is small owing to the off-state of MOS FET and the high drain voltage. In the region 2, the CGD is multiplied by the “mirror effect” as the characteristics of MOS FET transfers from offstate to on-state. In the region 3, both the CGD and CGS affect to the characteristics as the MOS FET is on-state and the drain voltage is low. Gate-source Voltage VGS (V) 20 Drain ID VDS = 80 V 200 V 320 V 15 10 CGD (3) Gate CDS (2) VD CGS 5 (1) VGS ID = 4 A Source 0 0 4 8 12 16 20 Total Stored Gate Charge (nC) Figure 39 The Relation between Applied Gate-Source Voltage and Stored Gate Charge The charging and discharging current caused by this gate charge makes the gate power dissipation. The relation between gate drive current ID and total gate charge QGSH is shown by following equation; ID = QGSH • fOSC ……………………………………………… (11) Where fosc is switching frequency As the gate drive current may reach up to several tenths milliamperes at 500 kHz operation, depending on the size of MOS FET, the power dissipation caused by the gate current can not be neglected. In this case, following action will be considered to avoid heat up of type M51995A. (1) To attach the heat sink to type M51995A (2) To use the printed circuit board with the good thermal conductivity (3) To use the buffer circuit shown next section 3. Output buffer circuit It is recommended to use the output buffer circuit as shown in figure 40, when type M51995A drives the large capacitive load or bipolar transistor. VOUT M51995A Figure 40 Output Buffer Circuit Diagram REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 36 of 40 M51995AP/AFP DET Circuit Figure 41 shows how to use the DET circuit for the voltage detector and error amplifier. A C Detecting voltage C1 R1 F/B C2 M51995A R3 DET B R2 C4 Figure 41 How to use the DET Circuit for the Voltage Detector For the phase shift compensation, it is recommended to connected the CR network between DET terminal and F/B terminal. Log G (dB) Figure 42 shows the gain-frequency characteristics between point B and point C shown in figure 41. GAVDET (DC Voltage gain) G1 Log ω ω1 ω2 Figure 42 Gain-Frequency Characteristics between Point B and C shown in Figure 41 The G1, ω1 and ω2 are given by following equations; G1 = R3 ……………………… (12) R1 / R2 ω1 = 1 ………………………… (13) C2 • R3 ω2 = C1 + C2 C1 • C2 • R3 ………………… (14) At the start of the operation, there happen to be no output pulse due to F/B terminal current through C1 and C2, as the potential of F/B terminal rises sharply just after the start of the operation. Not to lack the output pulse, is recommended to connect the capacitor C4 as shown by broken line. Please take notice that the current flows through the R1 and R2 are superposed to ICC(START). Not to superpose, R1 is connected to CVCC2 as shown in figure 25. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 37 of 40 M51995AP/AFP How to Get the Narrow Pulse Width During the Start of Operation Figure 43 shows how to get the narrow pulse width during the start of the operation. If the pulse train of forcedly narrowed pulse-width continues too long, the misstart of operation may happen, so it is recommended to make the output pulse width narrow only for a few pulse at the start of operation. 0.1µF is recommended for the C. F/B M51995A 100 Ω To photo coupler C Figure 43 How to Get the Narrow Pulse Width During the Start of Operation How to Synchronize with External Circuit Type M51995A has no function to synchronize with external circuit, however, there is some application circuit for synchronization as shown in figure 44. If this circuit is used, the synchronization may be out of order at the overload condition when the current limiting function starts to operate and VF terminal voltage becomes lower than 3 V. M51995A T-ON RON CF CF T-OFF CT + CT ROFF 120 µA Synchronous pulse Q1 Q2 Oscillating waveform 0V Synchronize waveform Minimum pulse width of synchronous pulse 0V Maximum pulse width of synchronous pulse Figure 44 How to Synchronize with External Circuit REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 38 of 40 M51995AP/AFP Driver Circuit for Bipolar Transistor When the bipolar transistor is used instead of MOS FET, the base current of bipolar transistor must be sinked by the negative base voltage source for the switching-off duration, in order to make the switching speed of bipolar transistor fast one. In this case, over current can not be detected by detecting resistor in series to bipolar transistor, so it is recommended to use the CT (current transformer). VCC VCC Collector VOUT M51995A −VSS (−2 V to −5 V) GND Emitter Figure 45 Driver Circuit Diagram (1) for Bipolar Transistor For the low current rating transistor, type M51995A can drive it directly as shown in figure 46. VCC Collector VOUT Bipolar transistor M51995A GND Emitter Figure 46 Driver Circuit Diagram (2) for Bipolar Transistor Attention for Heat Generation The maximum ambient temperature of type M51995A is +85°C, however, the ambient temperature in vicinity of the IC is not uniform and varies place by place, as the amount of power dissipation is fearfully large and the power dissipation is generated locally in the switching regulator. So it is one of the good idea to check the IC package temperature. The temperature difference between IC junction and the surface of IC package is 15°C or less, when the IC junction temperature is measured by temperature dependency of forward voltage of pin junction, and IC package temperature is measured by “thermo-viewer”, and also the IC is mounted on the “phenol-base” PC board in normal atmosphere. So it is concluded that the maximum case temperature (surface temperature of IC) rating is 120°C with adequate margin. As type M51995 has the modified totempole driver circuit, the transient through current is very small and the total power dissipation is decreased to the reasonable power level. REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 39 of 40 M51995AP/AFP Package Dimensions JEITA Package Code P-SOP20-5.3x12.6-1.27 RENESAS Code PRSP0020DA-A Previous Code 20P2N-A MASS[Typ.] 0.3g 20 E *1 HE 11 F 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 10 c Index mark *2 A2 D A1 L A Reference Symbol *3 bp e y Detail F D E A2 A1 A bp c HE e y L RENESAS Code PRDP0016AA-A Previous Code 16P4 Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 MASS[Typ.] 1.0g 9 1 8 c *1 E 16 e1 JEITA Package Code P-DIP16-6.3x19-2.54 Dimension in Millimeters NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 L A1 A A2 D e *3 b3 SEATING PLANE bp *3 b2 Reference Symbol e1 D E A A1 A2 bp b2 b3 c e L REJ03D0835-0300 Rev.3.00 Jun 06, 2008 Page 40 of 40 Dimension in Millimeters Min 7.32 18.8 6.15 Nom 7.62 19.0 6.3 Max 7.92 19.2 6.45 4.5 0.51 0.4 0.9 1.4 0.22 0° 2.29 3.0 3.3 0.5 1.0 1.5 0.27 2.54 0.6 1.3 1.8 0.34 15° 2.79 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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