MITSUBISHI M51996AP

MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
DESCRIPTION
M51996A is the primary switching regulator controller which is
especially designed to get the regulated DC voltage from AC power
PIN CONFIGURATION (TOP VIEW)
supply.
This IC can directly drive the MOS-FET with fast rise and fast fall
output pulse and with a large-drive totempole output.
Type M51996A has the functions of not only high frequency OSC
and fast output drive but also current limit with fast response and
high sensibility so the true "fast switching regulator" can be
realized.
The M51996A is equivalent to the M51978 with externally resettable OVP(over voltage protection)circuit.
COLLECTOR
1
14
Vcc
VOUT
2
13
CLM+
EMITTER
3
12
GND
OVP
4
11
T-OFF
F/B
5
10
CF
DET
6
9
T-ON
REG
7
8
SOFT
Outline 14P4
FEATURES
500kHz operation to MOS FET
Output current...............................................................±1A
Output rise time 60ns,fall time 40ns
COLLECTOR
1
16
Vcc
VOUT
2
15
CLM+
•Small start-up current............................................100µA typ.
EMITTER
3
14
GND
•Big difference between "start-up voltage" and "stop voltage"
HEAT SINK PIN
4
13
HEAT SINK PIN
OVP
5
12
T-OFF
F/B
6
11
CF
DET
7
10
T-ON
REG
8
9
SOFT
Modified totempole output method with small through current
Compact and light-weight power supply
makes the smoothing capacitor of the power input section small.
Start-up threshold 16V,stop voltage 10V
•Packages with high power dissipation are used to with-stand the
heat generated by the gate-drive current of MOS FET.
14-pin DIP,16-pin SOP 1.5W(at 25°C)
Simplified peripheral circuit with protection circuit and built-in
Outline 16P2N-A
large-capacity totempole output
•High-speed current limiting circuit using pulse-by-pulse
method(CLM+pin)
•Over-voltage protection circuit with an externally re-settable
Connect the heat sink pin to GND.
latch(OVP)
•Protection circuit for output miss action at low supply
voltage(UVLO)
High-performance and highly functional power supply
•Triangular wave oscillator for easy dead time setting
•SOFT start function by expanding period
APPLICATION
Feed forward regulator,fly-back regulator
RECOMMENDED OPERATING CONDITIONS
Supply voltage range............................................12 to 30V
Operating frequency.................................less than 500kHz
Oscillator frequency setting resistance
•T-ON pin resistance RON...........................10k to 75kΩ
•T-OFF pin resistance ROFF..........................2k to 30kΩ
( 1 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
BLOCK DIAGRAM
F/B
REG(7.8V)
VCC
7.1V
VOLTAGE
REGULATOR
5.8V
3K
15.2K 1S
500
6S
DET
UNDER
VOLTAGE
LOCK OUT
OVP
OP AMP
1S
1S
2.5V
LATCH
PWM
LATCH
PWM
COMPARATOR
COLLECTOR
VOUT
EMITTER
CF
CURRENT LIMIT
DETECTION
OSCILLATOR
T-ON
(TRIANGLE)
T-OFF
SOFT
CLM+
GND
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VC
Parameter
Supply voltage
Collector voltage
IO
Output current
IVREG
VSOFT
VCLM+
VDET
IOVP
IFB
VREG terminal output current
SOFT terminal voltage
CLM+ terminal voltage
DET terminal voltage
OVP terminal current
F/B terminal current
T-ON terminal input current
T-OFF terminal input current
Power dissipation
Thermal derating
Operating temperature
Storage temperature
ITON
ITOFF
Pd
K
Topr
Tstg
Conditions
Peak
Continuous
Ta=25˚C
Ta>25˚C
Ratings
31
31
±1
±0.15
-6
VREG +0.2
-0.3 to +3
6
8
-10
-1
-2
1.5
12
-30 to +85
-40 to +125
Note 1."+" sign shows the direction of current flowing into the IC and "-" sign shows the current flowing out from the IC.
2.The low impedance voltage supply should not be applied to the OVP terminal.
( 2 / 22 )
Unit
V
V
A
mA
V
V
V
mA
mA
mA
mA
W
mW/˚C
˚C
˚C
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
ELECTRICAL CHARACTERISTICS (VCC=18V, Ta=25°C, unless otherwise noted)
Block
Symbol
Parameter
Test conditions
16.2
9.9
5.0
6.3
7.6
V
65
50
7.3
8
1.3
140
-2.1
-0.9
-1.35
4.9
420
540
100
100
150
200
µA
11
12
2.0
210
-1.5
-0.6
-0.99
5.9
17
19
3.0
320
-1.0
-0.4
-0.70
7.1
780
960
OVP terminal is open.
(high impedance)
80
80
7.5
600
750
30
150
150
9.0
0.55
1.20
Vcc=30V
Vcc=18V
-480
-210
-320
-140
-213
-93
180
-280
200
-200
220
-140
mV
µA
ns
170
188
207
kHz
47
3.97
1.76
50
4.37
1.96
53
4.77
2.16
%
V
V
2.11
2.41
2.71
V
RON=20kΩ
3.8
4.5
5.4
V
ROFF=17kΩ
2.9
170
111
19.0
-0.5
3.5
V
188
131
23.3
-0.1
4.2
207
151
27.0
1
3.3
Vcc(START),Vcc(STOP) difference
∆Vcc=Vcc(START) -Vcc(STOP)
IccL
Stand-by current
IccO
Operating circuit current
IccOVP
Circuit current in OVP state
Vcc=14.5V,Ta=25°C
Vcc=14.5V,-30≤Ta≤85°C
Vcc=15V,f=188kHz
Vcc=30V,f=188kHz
Vcc=25V
Vcc=9.5V
F/B terminal input current
F/B terminal input current
∆IFB=IFBMIND-IFBMAXD
Current at 0% duty
Current at maximum duty
Current difference between max and 0% duty
F/B terminal voltage
OVP terminal resistance
OVP terminal H threshold voltage
OVP terminal hysteresis voltage
OVP terminal threshold current
OVP terminal input current
OVP reset supply voltage
Difference supply voltage between
operation stop and OVP reset
ITHOVPC
Current from OVP terminal for
OVP reset
VTHCLM+
IINCLM+
TPDCLM+
CLM+ terminal threshold voltage
CLM+ terminal current
Delay time from CLM+ to VOUT
fOSC
F/B terminal input current=0.95mA
∆VTHOVP=VTHOVPH-VTHOVPL
VOVP=400mV
VCLM+=0V
TDUTY
VOSCH
VOSCL
Maximum ON duty
Upper limit voltage of oscillation waveform
Lower limit voltage of oscillation waveform
∆VOSC
Voltage difference between upper limit and
lower limit of OSC waveform
VT-ON
VT-OFF
T-ON terminal voltage
T-OFF terminal voltage
VSOFT=5.5V
VSOFT=2.5V
VSOFT=0.2V
RON=20kΩ,ROFF=17kΩ
CF=220pF
RON=20kΩ,ROFF=17kΩ
CF=220pF
fOSCSOFT
Oscillating frequency during
SOFT operation
ISOFTIN
SOFT terminal input current
VSOFT=1V
ISOFDIS
SOFT terminal discharging current
Discharge current of SOFT terminal at
Vcc less than Vcc(STOP)
VREG
Regulator output voltage
VOL1
VOL2
VOL3
VOL4
VOH1
VOH2
TRISE
TFALL
VDET
IINDET
GAVDET
Output low voltage
Output high voltage
6.8
Vcc=18V,Io=10mA
Vcc=18V,Io=100mA
Vcc=5V,Io=1mA
Vcc=5V,Io=100mA
Vcc=18V,Io=-10mA
Vcc=18V,Io=-100mA
2.4
30
1.0
40
16.0
15.5
VDET=2.5V
( 3 / 22 )
7.8
0.04
0.7
0.85
1.3
16.7
16.5
60
40
2.5
Output voltage rise time
Output voltage fall time
Detection voltage
DET terminal input current
Voltage gain of detection amp
250
250
10.0
V
V
V
mA
mA
µA
mA
mA
mA
V
Ω
mV
mV
µA
µA
V
V
100
RON=20kΩ,ROFF=17kΩ
CF=220pF,-5≤Ta≤85°C
Oscillating frequency
Unit
15.2
9.0
Vcc(STOP)
∆Vcc
IFBMIND
IFBMAXD
∆IFB
VFB
RFB
VTHOVPH
∆VTHOVP
ITHOVP
IINOVP
VCCOVPC
VCC(STOP)
-VCCOVPC
Limits
Typ.
Max.
30
17.2
10.9
Operating supply voltage range
VCC
VCC(START) Operation start up voltage
VCC(STOP) Operation stop voltage
Min.
µA
kHz
µA
mA
8.8
0.4
1.4
1.0
2.0
2.6
3.0
V
V
V
V
V
V
V
ns
ns
V
µA
dB
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
TYPICAL CHARACTERISTICS
THERMAL DERATING
(MAXIMUM RATING)
1800
CIRCUIT CURRENT VS.SUPPLY VOLTAGE
(NORMAL OPERATION)
16m
14m
1500
fOSC=500kHz
RON=18kΩ
ROFF=20kΩ
12m
1200
10m
fOSC=100kHz
900
150m
600
Ta=-30°C
Ta=25°C
Ta=85°C
100µ
300
50µ
0
25
50
75 85 100
125
AMBIENT TEMPERATURE Ta(°C)
0
4.0
1 RON=15k,ROFF=27k
2 RON=18k,ROFF=24k
3.5
40
(fOSC=500kHz)
4.5
4.0
35
5.0
(fOSC=100kHz)
4.5
1 RON=15k,ROFF=27k
2 RON=18k,ROFF=24k
3.5
3.0
3 RON=22k,ROFF=22k
4 RON=24k,ROFF=20k
5 RON=22k,ROFF=12k
3.0
2.5
6 RON=36k,ROFF=6.2k
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0
10
15
20 25
30
SUPPLY VOLTAGE Vcc(V)
5
SOFT TERMINAL INPUT VOLTAGE VS.
EXPANSION RATE OF PERIOD
SOFT TERMINAL INPUT VOLTAGE VS.
EXPANSION RATE OF PERIOD
5.0
0
150
3 RON=22k,ROFF=22k
4 RON=24k,ROFF=20k
5 RON=22k,ROFF=12k
6 RON=36k,ROFF=6.2k
0.5
1 2
0
2
4
6
4
3
8
6
5
10
12
0
14 16
18
20
EXPANSION RATE OF PERIOD(TIMES)
5
6
2
4 6 8 10 12 14 16 18
EXPANSION RATE OF PERIOD(TIMES)
20
CLM+ TERMINAL THRESHOLD VOLTAGE
VS. AMBIENT TEMPERATURE
SOFT TERMINAL INPUT VOLTAGE VS.
INPUT VOLTAGE
-100
4
1 2 3
0
-90
-80
205
-70
-60
Ta=-30°C
-50
200
Ta=25°C
Ta=85°C
-40
-30
195
-20
-10
0
0
1
2
3
4
5
6
7
8
9
10
-60
SOFT TERMINAL INPUT VOLTAGE VSOFT(V)
-40
-20
0
20
40
60
80
AMBIENT TEMPERATURE Ta(°C)
( 4 / 22 )
100
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
CLM+ TERMINAL CURRENT
VS. CLM+ TERMINAL VOLTAGE
REG OUTPUT VOLTAGE
VS. AMBIENT TEMPERATURE
-400
8.5
Rc=∞
Rc=3.6k
Rc=1.5k
-300
Ta=-30°C
Ta=25°C
8.0
Ta=85°C
-200
7.5
-100
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
-40
-20
0
20
40
60
100
80
CLM+ TERMINAL VOLTAGE VCLM+(V)
AMBIENT TEMPERATURE Ta(°C)
OUTPUT HIGH VOLTAGE VS.
SOURCE CURRENT
OUTPUT LOW VOLTAGE
VS. SINK CURRENT
4.5
5.0
Ta=25°C
4.2
4.5
3.9
3.6
7.0
-60
4.0
Vcc=18V
Ta=25°C
3.5
3.3
3.0
3.0
2.7
2.5
2.4
2.0
Vcc=5V
2.1
1.5
1.8
1.0
1.5
0.5
1.2
10 -3 2
Vcc=18V
3
5
10 -2 2 3 5 10 -1 2 3 5 10 0 2
SOURCE CURRENT IOH(A)
3
5
10
1
0
10 -3 2
3
5
10 -2 2 3 5 10 -1 2 3 5 10 0
SINK CURRENT IOL(A)
2 3
5
10 1
DETECTION TERMINAL INPUT CURRENT
VS. AMBIENT TEMPERATURE
DETECTION VOLTAGE
VS. AMBIENT TEMPERATURE
1.4
2.55
1.3
1.2
1.1
2.50
1.0
0.9
2.45
0.8
0.7
2.40
-60
-40
-20
0
20
40
60
80
0
-60
100
-40
-20
0
20
40
60
80
AMBIENT TEMPERATURE Ta(°C)
AMBIENT TEMPERATURE Ta(°C)
( 5 / 22 )
100
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
VOLTAGE GAIN OF DETECTION AMP
VS. FREQUENCY
ON duty
VS. F/B TERMINAL INPUT CURRENT
50
50
45
45
40
40
35
35
30
30
25
25
20
20
15
15
10
10
Ta=-30°C
Ta=25°C
Ta=85°C
5
0
(fOSC=100kHz)
RON=18kΩ
ROFF=20kΩ
5
2 2 3
5
10
10
3 2 3
5
10
4 2 3
5
10
5 2 3
5
10
6
0
0
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
FREQUENCY f(Hz)
F/B TERMINAL INPUT CURRENT IF/B (mA)
ON duty
VS. F/B TERMINAL INPUT CURRENT
ON duty VS.
F/B TERMINAL INPUT CURRENT
50
50
(fOSC=200kHz)
RON=18kΩ
ROFF=20kΩ
40
(fOSC=500kHz)
RON=18kΩ
ROFF=20kΩ
40
30
30
Ta=-30°C
Ta=-30°C
Ta=25°C
Ta=25°C
20
Ta=85°C
20
Ta=85°C
10
0
10
0
0
F/B TERMINAL INPUT CURRENT IF/B (mA)
F/B TERMINAL INPUT CURRENT IF/B(mA)
UPPER & LOWER LIMIT VOLTAGE OF OSC
VS. AMBIENT TEMPERATURE
5.2
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
0
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
OSCILLATING FREQUENCY VS. CF
TERMINAL CAPACITANCE
10 4
RON=18kΩ
ROFF=20kΩ
5
RON=22kΩ
ROFF=12kΩ
3
2
4.8
10 3
5
4.4
fOSC=500kHz
fOSC=200kHz
fOSC=100kHz
4.0
3
2
10
2
5
3
fOSC=100kHz
fOSC=200kHz
fOSC=500kHz
2.2
RON=36kΩ
ROFF=6.2kΩ
2
RON=24kΩ
ROFF=20kΩ
10 1
2.0
5
3
1.8
-60
2
-40
-20
0
20
40
60
80
100
10
0
100
AMBIENT TEMPERATURE Ta(°C)
2 3
5
10 1
2 3
5
10 2
2 3
5
10 3
2 3
CF TERMINAL CAPACITANCE(pF)
( 6 / 22 )
5
10 4
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
OSCILLATOR FREQUENCY VS.
AMBIENT TEMPERATURE
ON duty VS. ROFF
100
120
90
RON=24kΩ
ROFF=20kΩ
CF=330pF
80
110
70
RON=75kΩ
60
51kΩ
50
36kΩ
24kΩ
22kΩ
18kΩ
15kΩ
10kΩ
40
30
20
100
90
10
0 0
10
3
5
7
10 1
3
5
80
-60
10 2
7
-40
0
20
40
60
100
80
AMBIENT TEMPERATURE Ta(°C)
ROFF(kΩ)
OSCILLATOR FREQUENCY VS.
AMBIENT TEMPERATURE
700
-20
ON duty VS. AMBIENT TEMPERATURE
100
RON=24kΩ
ROFF=20kΩ
CF=47pF
600
(fOSC=100kHz)
90
80
RON=36k,ROFF=6.2k
70
500
60
RON=22k,ROFF=12k
50
400
RON=24k,ROFF=20k
RON=22k,ROFF=22k
40
RON=18k,ROFF=24k
RON=15k,ROFF=27k
30
300
20
10
200
-60
-40
-20
0
20
40
60
0
-60
100
80
AMBIENT TEMPERATURE Ta(°C)
ON duty VS. AMBIENT TEMPERATURE
ON duty VS. AMBIENT TEMPERATURE
100
100
(fOSC=200kHz)
90
(fOSC=500kHz)
90
80
RON=36k,ROFF=6.2k
70
80
RON=36k,ROFF=6.2k
70
60
RON=22k,ROFF=12k
60
50
RON=24k,ROFF=20k
RON=22k,ROFF=22k
50
40
RON=18k,ROFF=24k
40
30
RON=15k,ROFF=27k
20
10
10
-40
-20
0
20
40
60
80
RON=22k,ROFF=12k
RON=24k,ROFF=20k
RON=22k,ROFF=22k
RON=18k,ROFF=24k
RON=15k,ROFF=27k
30
20
0
-60
100
-40 -20
0
20
40 60 80
AMBIENT TEMPERATURE Ta(°C)
0
-60
100
-40
-20
0
20
40
60
80
AMBIENT TEMPERATURE Ta(°C)
AMBIENT TEMPERATURE Ta(°C)
( 7 / 22 )
100
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
1m
OVP TERMINAL INPUT VOLTAGE VS.
INPUT CURRENT
1.1
OVP TERMINAL THRESHOLD VOLTAGE
VS.AMBIENT TEMPERATURE
Vcc=18V
Ta=85°C
Ta=25°C
Ta=-30°C
1.0
0.9
100µ
H threshold voltage
(VTHOVPH)
0.8
0.7
L threshold voltage
(VTHOVPL)
0.6
10µ
0.5
0.4
1µ
0.3
0.2
0.4
0.6
0.8
1.0
OVP TERMINAL INPUT VOLTAGE VOVP(V)
-40
-20
0
20 40
60
80 100
AMBIENT TEMPERATURE Ta(°C)
CURRENT FROM OVP TERMINAL FOR
OVP RESET VS.SUPPLY VOLTAGE
CIRCUIT CURRENT VS.SUPPLY VOLTAGE
(OVP OPERATION)
800
8.0
OVP RESET POINT
8.87V(-30°C)
7.0
8.94V(25°C)
9.23V(85°C)
6.0
700
600
500
5.0
4.0
Ta=-30°C
Ta=25°C
400
Ta=-30°C
Ta=25°C
3.0
Ta=85°C
300
Ta=85°C
2.0
200
1.0
100
0
0
10.0
20.0
30.0
SUPPLY VOLTAGE Vcc(V)
40.0
0
0
5
10
15
20
25
30
35
SUPPLY VOLTAGE Vcc(V)
OUTPUT THRUGH CURRENT WAVEFORM
AT RISING EDGE OF OUTPUT PULSE
AT FALLING EDGE OF OUTPUT PULSE
Horizontal-axis : 20ns/div
Vertical-axis : 5mA/div
Horizontal-axis : 20ns/div
Vertical-axis : 50mA/div
( 8 / 22 )
40
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
FUNCTION DESCRIPTION
parts can be reduced and also parts can be replaced by
reasonable one.
In the following circuit diagram,MOS-FIT is used for output
transistor,however bipolar transistor can be replaced with no
problem.
Type M51996AP and M51996AFP are especially designed for
off-line primary PWM control IC of switching mode power supply
to get DC voltage from AC power supply.
Using this IC,smart SMPS can be realized with reasonable
cost and compact size as the number of external electric
RUSH CURRENT
PREVENTION CIRCUIT
DC OUTPUT
R1
Vcc
COLLECTOR
VOUT
REG
CLM+
R2
AC
INPUT
CVcc
M51996AP/FP
EMITTER
CFIN
GND
SOFT
OVP
F/B
T-ON
DET
T-OFF
CF
CF
RON
ROFF
FEEDBACK
OVP
(TL431)
Fig.1 Application example for feed forward regulator
RUSH CURRENT
PREVENTION CIRCUIT
DC OUTPUT
R1
Vcc
COLLECTOR
VOUT
F/B
CLM+
DET
AC
INPUT
M51996AP/FP
CFIN
CVcc
EMITTER
REG
GND
SOFT
DET
T-ON
RON
CF
CF
T-OFF
ROFF
Fig.2 Application example for fly-back regulator
( 9 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
Start-up circuit section
where VOSCH ~ 4.4V
VOSCL ~ 2.0V
The start-up current is such low current level as typical 100µ
A,as shown in Fig.3,when the Vcc voltage is increased
from low level to start-up voltage Vcc(START).
In this voltage range,only a few parts in this IC,which has the
function to make the output voltage low level,is alive and
Icc current is used to keep output low level.The large voltage
difference between Vcc(START) and Vcc(STOP) makes start-up
easy,because it takes rather long duration from Vcc(START) to
Vcc(STOP).
CF is discharged by the summed-up of ROFF current and one
sixteenth (1/16) of RON current by the function of Q2,Q3 and Q4
when SW1,SW2 are switched to "discharge side".
5.8V
Q4
T-ON
1/16
Q3
RON
Icco
~ 11mA
T-OFF
ROFF
Q1
CHARGING
SW1
FROM
VF SIGNAL
Vz ~ 4.2V
SWITCHED BY
CHARGING AND
DISCHARGING
SIGNAL
CF
CF
IccL
~ 100µA
SW2
Q2
DISCHARGING
Vcc
Vcc
(STOP)
(START)
M51996A
~ 9.9V ~ 16.2V
Fig.4 Schematic diagram of charging and discharging
control circuit for OSC.capacitor CF
SUPPLY VOLTAGE Vcc(V)
Fig.3 Circuit current vs.supply voltage
VOSCH
~ 4.4V
Oscillator section
The oscillation waveform is the triangle one.The ON-duration
of output pulse depends on the rising duration of the triangle
waveform and dead-time is decided by the falling duration.
The rising duration is determined by the product of external
resistor RON and capacitor CF and the falling duration is mainly
determined by the product of resistor ROFF and capacitor CF.
VOSCL
~ 2.0V
(1)Oscillator operation when SOFT circuit does
not operate
VOH
Fig.4 shows the equivalent charging and discharging circuit
diagram of oscillator.
The current flows through RON from the constant voltage source
of 5.8V.CF is charged up by the same amplitude as RON
current,when internal switch SW1,SW2 is switched to "charging
side".The rise rate of CF terminal is given as
~
VT - ON
(V/s) ................................................(1)
RON X CF
where VT - ON ~ 4.5V
The maximum on duration is approximately given as
~ (VOSCH-VOSCL) X RON X CF (s)........................(2)
VT - ON
VOL
Fig.5 OSC.waveform at normal condition (nooperation of intermittent action and OSC.control
circuit)
So fall rate of CF terminal is given as
~
VT - OFF
VT - ON
+
(V/s) .....................(3)
ROFF X CF
16 X RON X CF
The minimum off duration approximately is given as
~ (VOSCH-VOSCL) X CF (s) .....................................(4)
VT-OFF + VT-ON
ROFF
16 X RON
where VT - OFF
~
3.5V
The cycle time of oscillation is given by the summation of
Equations 2 and 4.
The frequency including the dead-time is not influenced by the
temperature because of the built-in temperature compensating
circuit.
( 10 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
(2)Oscillator operation when the SOFT(soft
start) circuit is operating.
START FROM 0V
VOSCH
Output transistor is protected from rush current by CLM function
at the start time of power on.SOFT terminal is used to improve
the rising response of the output voltage of power
supply(prevention of overshooting).
The ON duration of output is kept constant,and the OFF
duration is extended as the SOFT terminal voltage becomes
lower by the soft start circuit of this IC.
The maximum value of extension is set internally at
approximately sixteen times of the maximum ON duartion.
The features of this method are as follows:
1 It is ideal for primary control as IC driving current is supplied
from the third widing of the main transformer at the start-up
because constant ON duration is obtained from start-up.
2 It is possible to get a wide dynamic range for ON/OFF ratio
by pulse-by-pulse current limit circuit.
3 The response characteristics at power-on is not affected by
input voltage as the pulse-by-pulse limit current value is not
affected by the input voltage.
Fig.6 shows the circuit diagram of the soft start.If SOFT terminal
voltage is low,T-OFF terminal voltage bocomes low and VT-OFF
in equations (3) and (4) become low.
TO REG
TERMINAL
VOSCL
0
THE FIRST
OUTPUT PULSE
VOH
NO OUTPUT
PULSE
VOL
0
t
Fig.8 Relationship between oscillator waveform and
output waveform at start-up
Fig.7 shows the relationship between oscillator waveform and
output pulse.
If the SOFT terminal voltage is VSOFT,the rise rate of CF
terminal given as
TO REG
TERMINAL
RSOFT
~
SOFT
TERMINAL
VT - ON
(V/S) ..............................................................(5)
RON • CF
The fall rate of oscillation waveform is given as
CSOFT
T-OFF
TERMINAL
Vz ~ 4.2V
~ VSOFT - VBE
RON • CF
+
VT - ON
(V/S) .............................(6)
16 • RON • CF
GND
TERMINAL
DISCHARGING TRANSISTOR*
IC's INTERNAL CIRCUIT
where
VSOFT;SOFT terminal applied voltage
VBE ~ 0.65V
If VSOFT - VBE < 0, VSOFT - VBE = 0
If VSOFT - VBE > VT - OFF (~3.5V), VSOFT - VBE =VT - OFF
*Active when operation stops.
Fig.6 Circuit diagram of SOFT terminal section and TOFF terminal section
VOSCH
~ 4.4V
PWM comparator, PWM latch and current limit
latch section
VOSCL
~ 2.0V
t
VOH
VOL
t
Fig.7 Oscillator waveform when the SOFT circuit is
operating
Fig.9 shows the scematic diagram of PWM comparator and
PWM latch section. The on-duration of output waveform
coincides with the rising duration of CF terminal waveform,when
the no output current flows from F/B terminal.
When the F/B terminal has finite impedance and current flows
out from F/B terminal,"A" point potential shown in Fig.9 depends
on this current.So the "A" point potential is close to GND level
when the flow-out current becomes large.
"A" point potential is compared with the CF terminal oscillator
waveform and PWM comparator,and the latch circuit is set
when the potential of oscillator waveform is higher than "A"
point potential.
The latch circuit is reset during the dead-time of oscillation
(falling duration of oscillation current).So the "B" point potential
or output waveform of latch circuit is the one shown in Fig.10.
The final output waveform or "C" point potential is got by
combining the "B" point signal and dead-time signal
logically.(please refer to Fig.10)
( 11 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
~ 7.1V
5.8V
OSC WAVEFORM
OF CF TERMINAL
POINT A
6S
LATCH
CURRENT
+
1S
POINT B
WAVEFORM OF
CLM+ TERMINAL
*1
PWM
COMP
F/B
VTHCLM~ 200mV
TO
OUTPUT
POINT C
CURRENT LIMIT
SIGNAL TO SET
LATCH
POINT D
M51996
CF
*2
FROM
OSC
CLM+
WAVEFORM OF
VOUT TERMINAL
*1 Resistor to determine current limit sensitivety
*2 High level during dead time
Fig.11 Operating waveform of current limiting circuit
Fig.9 PWM comparator PWM latch and
current limit latch section
To eliminate the abnormal operation by the noise voltage,the
low pass filter,which consists of RNF and CNF is used as shown
in Fig.12.
It is recommended to use 10 to 100Ω for RNF because such
range of RNF is not influenced by the flow-out current of some
200µA from CLM+ terminal and CNF is designed to have the
enough value to absorb the noise voltage.
OSC WAVEFORM
WAVEFORM AT POINT A
WAVEFORM
OF O.S.C. &
POINT A
M51996
POINT B
VOUT
POINT C
CLM+
POINT
D
RNF
CNF
Fig.10 Waveforms of PWM comparator input point A,
latch circuit points B and C
RCLM
GND
Current limiting section
When the current-limit signal is applied before the crossing
instant of "A" pint potential and CF terminal voltage shown in
Fig.9,this signal makes the output "off" and the off state will
continue until next cycle.Fig.11 shows the timing relation among
them.
If the current limiting circuit is set,no waveform is generated at
output terminal, however this state is reset during the
succeeding dead-time.
So this current limiting circuit is able to have the function in
every cycle,and is named "pulse-by-pulse current limit".
There happen some noise voltage on RCLM during the switching
of power transistor due to the snubber circuit and stray
capacitor of the transformer windings.
Fig.12 Connection diagram of current limit circuit
Voltage detector circuit(DET) section
The DET terminal can be used to control the output voltage
which is determined by the winding ratio of fly back transformer
in fly-back system or in case of common ground circuit of
primary and secondary in feed forward system.
The circuit diagram is quite similar to that of shunt regulator
type 431 as shown in Fig.13.As well known from Fig.13 and
Fig.14,the output of OP AMP has the current-sink ability,when
the DET terminal voltage is higher than 2.5V
( 12 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
7.1V
It is necessary to input the sufficient larger current(800µA to
8mA)than I2 for triggering the OVP operation.
The reason to decrease I2 is that it is necessary that Icc at the
OVP rest supply voltage is small.
It is necessary that OVP state holds by circuit current from R1 in
the application example,so this IC has the characteristic of
small Icc at the OVP reset supply voltage(~stand-by current +
20µA)
On the other hand,the circuit current is large in the higher
supply voltage,so the supply voltage of this IC doesn't become
so high by the voltage drop across R1.
This characteristic is shown in Fig.16.
The OVP terminal input current in the voltage lower than the
OVP threshold voltage is based on I2 and the input current in
the voltage higher than the OVP threshold voltage is the sum of
the current flowing to the base of Q3 and the current flowing
from the collector of Q2 to the base.
For holding in the latch state,it is necessary that the OVP
terminal voltage is kept in the voltage higher than VBE of Q3.
So if the capacitor is connected between the OVP terminal and
GND,even though Q2 turns on in a moment by the surge
voltage,etc,this latch action does not hold if the OVP terminal
voltage does not become higher than VBE of Q3 by charging
this capacitor.
For resetting OVP state,it is necessary to make the OVP
terminal voltage lower than the OVP L threshold voltage or
make Vcc lower than the OVP reset supply voltage.
As the OVP reset voltage is settled on the rather high voltage of
9.0V,SMPS can be reset in rather short time from the switch-off
of the AC power source if the smoothing capacitor is not so
large value.
500Ω
3k
1S
6S
F/B
DET
5.4k
10.8k
10.8k
10S
1.2k
Fig.13 Voltage detector circuit section(DET)
but it becomes high impedance state when lower than
2.5V DET terminal and F/B terminal have inverting
phase characteristics each other,so it is recommended
to connect the resistor and capacitor in series between
them for phase compensation.It is very important one
can not connect by resistor directly as there is the
voltage difference between them and the capacitor has
the DC stopper function.
7.1V
3k
1S
500Ω
Vcc
6S
7.8V
F/B
100µA
8k
OP AMP
I1
DET
12k
+
Q1
2.5V
Q2
Fig.14 Schmatic diagram of voltage detector circuit section(DET)
400
Q3
OVP
OVP circuit(over voltage protection circuit)section
OVP circuit is basically positive feedback circuit constructed
by Q2,Q3 as shown in Fig.15.
Q2,Q3 turn on and the circuit operation of IC stops,when the
input signal is applied to OVP terminal.(threshold voltage ~
750mV)
The current value of I2 is about 150µA when the OVP does
not operates but it decreases to about 2µA when OVP
operates.
2.5k
GND
I2
I1=0 when OVP operates
Fig.15 Detail diagram of OVP circuit
( 13 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
RECTIFIED DC
VOLTAGE FROM
SMOOTHING CAPACITOR
8
OVP RESET POINT
8.87V(-30°C)
8.94V(25°C)
9.23V(85°C)
7
6
5
VF
THIRD WINDING OR
BIAS WINDING
Vcc
Ta=-30°C
Ta=25°C
Ta=85°C
4
MAIN TRANSFORMER
R1
M51996A
CVcc
3
GND
2
1
0
Fig.24 Start-up circuit diagram when it is not
necessary to set the start and stop input voltage
0
10
20
30
40
SUPPLY VOLTAGE Vcc(V)
Fig.16 CIRCUIT CURRENT VS. SUPPLY VOLTAGE
(OVP OPERATION)
Output section
It is required that the output circuit have the high sink and
source abilities for MOS-FET drive.It is well known that the
"totempole circuit has high sink and source ability.However,it
has the demerit of high through current.
For example,the through current may reach such the high
current level of 1A,if type M51996A has the "conventional"
totempole circuit.For the high frequency application such as
higher than 100kHz,this through current is very important factor
and will cause not only the large Icc current and the inevitable
heat-up of IC but also the noise voltage.
This IC uses the improved totempole circuit,so without
deteriorating the characteristic of operating speed,its through
current is approximately 100mA.
APPLICATION NOTE OF TYPE M51996AP/FP
Design of start-up circuit and the power supply
of IC
Just after the start-up,the Icc current is supplied from
Cvcc,however,under the steady state condition ,IC will be
supplied from the third winding or bias winding of
transformer,the winding ratio of the third winding must be
designed so that the induced voltage may be higher than the
operation-stop voltage Vcc(STOP).
The Vcc voltage is recommended to be 12V to 17V as the
normal and optimum gate voltage is 10 to 15V and the output
voltage(VOH) of type M51996AP/FP is about(Vcc-2V).
It is not necessary that the induced voltage is settled higher
than the operation start-up voltage Vcc(START),and the high gate
drive voltage causes high gate dissipation,on the other hand,too
low gate drive voltage does not make the MOS-FET fully onstate or the saturation state.
(2)The start-up circuit when it is not necessary to set the
start and stop input voltage
It is recommend to use the third winding of "forward winding"
or "positive polarity" as shown in Fig.18,when the DC source
voltages at both the IC operation start and stop must be
settled at the specified values.
The input voltage(VIN(START)),at which the IC operation
starts,is decided by R1 and R2 utilizing the low start-up
RECTIFIED DC
VOLTAGE FROM
SMOOTHING CAPACITOR
(1)The start-up circuit when it is not necessary to set the
start and stop input voltage
Fig.17 shows one of the example circuit diagram of the start-up
circuit which is used when it is not necessary to set the start
and stop voltage.
It is recommended that the current more than 300µA flows
through R1 in order to overcome the operation start-up current
Icc(START) and Cvcc is in the range of 10 to 47µF.The product of
R1 by Cvcc causes the time delay of operation,so the response
time will be long if the product is too much large.
VIN
NP
PRIMARY WINDING
OF TRANSFORMER
R1
VF
Vcc
M51996A
NB
R2
THIRD WINDING OF
TRANSFORMER
CVcc
GND
Fig.18 Start-up circuit diagram when it is not
necessary to set the start and stop input voltage
( 14 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
current characteristics of type M51996AP/FP.
The input voltage(VIN(STOP)),at which the IC operation stops,is
decided by the ratio of third winding of transformer.
The VIN(START) and VIN(STOP) are given by following equations.
VIN(START)~ R1 • ICCL + ( R1 + 1) • Vcc(START)...............(7)
R2
NP + 1
VIN(STOP)~ (Vcc(STOP)-VF) •
2 V'IN RIP(P-P)............(8)
NB
where
ICCL is the operation start-up current of IC
Vcc(START) is the operation start-up voltage of IC
Vcc(STOP) is the operation stop voltage of IC
VF is the forward voltage of rectifier diode
V'IN(P-P) is the peak to peak ripple voltage of
Vcc terminal ~
NB
NP V'IN RIP(P-P)
It is required that the VIN(START) must be higher than VIN(STOP).
When the third winding is the "fly back winding" or "reverse
polarity",the VIN(START) can be fixed,however,VIN(STOP) can not
be settled by this system,so the auxiliary circuit is required.
(3)Notice to the Vcc,Vcc line and GND line
To avoid the abnormal IC operation,it is recommended to
design the Vcc is not vary abruptly and has few spike
voltage,which is induced from the stray capacity between the
winding of main transformer.
To reduce the spike voltage,the Cvcc,which is connected
between Vcc and ground,must have the good high frequency
characteristics.
To design the conductor-pattern on PC board,following cautions
must be considered as shown in Fig.19.
(a)To separate the emitter line of type M51996A from the GND
line of the IC
(b)The locate the CVCC as near as possible to type M51996A
and connect directly
(c)To separate the collector line of type M51996A from the Vcc
line of the IC
(d)To connect the ground terminals of peripheral parts of ICs to
GND of type M51996A as short as possible
MAIN
TRANSFORMER
THIRD
WINDING
Vcc
COLLECTOR
M51996A
CVcc
OUTPUT
RCLM
EMITTER
GND
Fig.19 How to design the conductor-pattern of type
M51996A on PC board(schematic example)
(4)Power supply circuit for easy start-up
When IC start to operate,the voltage of the CVCC begins to
decrease till the CVCC becomes to be charged from the third
winding of main-transformer as the Icc of the IC increases
abruptly.In case shown in Fig.17 and 18,some "unstable startup" or "fall to start-up" may happen, as the charging interval of
CVCC is very short duration;that is the charging does occur only
the duration while the induced winding voltage is higher than
the CVCC voltage,if the induced winding voltage is nearly equal
to the "operation-stop voltage" of type M51996A.
It is recommended to use the 10 to 47µF for CVCC1,and about 5
times capacity bigger than CVCC1 for CVCC2.
R1
MAIN
TRANSFORMER
THIRD
WINDING
Vcc
M51996A
CVcc1
CVcc2
GND
Fig.20 DC source circuit for stable start-up
( 15 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
OVP circuit
(1)To avoid the miss operation of OVP
It is recommended to connect the capacitor between OVP
terminal and GND for avoiding the miss operation by the spike
noise.
The OVP terminal is connected with the sink current source
(~150µA) in IC when OVP does not operate,for absorbing the
leak current of the photo coupler in the application.
So the resistance between the OVP terminal and GND for leakcut is not necessary.
If the resistance is connected,the supply current at the OVP
reset supply voltage becomes large.
As the result,the OVP reset supply voltage may become higher
than the operation stop voltage.
In that case,the OVP action is reset when the OVP is triggered
at the supply voltage a little high than the operation stop
voltage.
So it should be avoided absolutely to connect the resistance
between the OVP terminal and GND.
TO MAIN
TRANSFORMER
R1
Vcc
~
CFIN R2
Cvcc
M51996A
GND
THE TIME CONSTANT OF
THIS PART SHOULD BE SHORT
Fig.22 Example circuit diagram to make the
OVP-reset-time fast
To REG or Vcc
5.6k
Vcc
M51996A
OVP
MAIN
TRANSFORMER
THIRD
WINDING
Vcc
470Ω
M51996A
PHOTO COUPLER
OVP
CVcc
GND
GND
Fig.21 Peripheral circuit of OVP terminal
FIG.23 OVP setting method using the induced
third winding voltage on fly back system
(2)Application circuit to make the OVP-reset time fast
The reset time may becomes problem when the discharge time
constant of CFIN • (R1+R2) is long. Under such the circuit
condition,it is recommended to discharge the CVCC forcedly and
to make the Vcc low value;This makes the OVP-reset time fast.
(3)OVP setting method using the induced third winding
voltage on fly back system
For the over voltage protection (OVP),the induced fly back type
third winding voltage can be utilized,as the induced third
winding voltage depends on the output voltage.Fig.23 shows
one of the example circuit diagram.
(4)Method to control for ON/OFF using the OVP terminal
You can reset OVP to lower the OVP terminal voltage lower
than VTHOVPL.
So you can control for ON/OFF using this nature.
The application is shown in Fig.24.
The circuit turns off by SW OFF and turns on by SW ON in this
application.
Of course you can make use of the transistor or photo-transistor
instead of SW.
REG
5.1k
M51996A
ON/OFF
SW
FIG.24 Method to control for ON/OFF using the
OVP terminal
( 16 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
Current limiting circuit
I2
(1)Peripheral circuit of CLM+ terminal
Fig.25 shows the example circuit diagrams around the CLM+
terminal.It is required to connect the low pass filter,in order to
reduce the spike current component,as the main current or
drain current contains the spike current especially during the
turn-on duration of MOS-FIT.
1,000pF to 22,000pF is recommended for CNF and the RNF1
and RNF2 have the functions both to adjust the "currentdetecting-sensitivity" and to consist the low pass filter.
CLM
RCLM
I1
(a) Feed forward system
IP1
R1
I1
CFIN
INPUT
SMOOTHING
CAPACITOR
Vcc
COLLECTOR
IP2
Cvcc
VOUT
I2
M51996A
CLM+
GND
EMITTER
RNF1
CNF
(b) Primary and secondary current
RNF2 RCLM
Fig.26 Primary and secondary current waveforms
under the current limiting operation
condition on feed forward system
Fig.25 Peripheral circuit diagram of CLM+ terminal
To design the RNF1 and RNF2,it is required to consider the
influence of CLM+ terminal source current(IINCLM+),
which value is in the range of 90 to 270µA.
In order to be not influenced from these resistor paralleled value
of RNF1 and RNF2,(RNF1/RNF2)is recommended to be less than
100Ω.
The RCLM should be the non-inductive resistor.
(2)Over current limiting curve
(a)In case of feed forward system
OUTPUT CURRENT
Fig.26 shows the primary and secondary current wave-forms
under the current limiting operation.
At the typical application of pulse by pulse primary current
detecting circuit,the secondary current depends on the primary
current.As the peak value of secondary current is limited to
specified value,the characteristics curve of output voltage
versus output current become to the one as shown in Fig.27.
Fig.27 Over current limiting curve on feed forward
system
The demerit of the pulse by pulse current limiting system is that
the output pulse width can not reduce to less than some value
because of the delay time of low pass filter connected to the
CLM+ terminal and propagation delay time TPDCLM from CLM+
terminal to output terminal of type M51996A.The typical
TPDCLM+ is 100ns.
As the frequency becomes higher,the delay time must be
shorter.And as the secondary output voltage becomes
higher,the dynamic range of on-duty must be wider;it means
that it is required to make the on-duration much more narrower.
So this system has the demerit at the higher oscillating
frequency and higher output voltage applications.
To prevent that the SOFT terminal is used to lower the
frequency when the curve starts to become vertical.
( 17 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
BIAS WINDING OF
THE MAIN TRANSFORMER
D2
Vcc
COLLECTOR
CVcc
REG
VOUT
TO OUTPUT TRANSISTOR
500
3K
M51996A
1S
R3
SOFT
6S
C
F/B
F/B
M51996A
REG
R1
R2
Q1
Fig.28 Relationship between REG terminal and
F/B terminal
D1
PHOTO-COUPLER
FOR FEED BACK SIGNAL
If the curve becomes vertical because of an excess current, the
output voltage is lowered and no feedback current flows from
feedback photo-coupler;the PWM comparator operates to
enlarge the duty sufficiently,but the signal from the CLM+
section operates to make the pulse width narrower.
Under the condition in which I2 in Fig.26 does not become 0,the
output voltage is proportional to the product of the input voltage
VIN(primary side voltage of the main transformer) and on duty.If
the bias winding is positive,Vcc is approximately proportional to
VIN.The existance of feed back current of the photo-coupler is
known by measuring the F/B terminal voltage which becomes
less than 2VBE in the internal circuit of REG terminal and F/B
terminal if the output current flows from the F/B terminal.
Fig.29 shows an application example.
Q1 is turned on when normal output voltage is controlled at a
certain value.The SOFT terminal is clampedto a high-level
voltage.If the output voltage decreases and the curve starts to
drop,no feed back current flows,Q1 is turned off and the SOFT
terminal responds to the smoothed output voltage.
It is recommended to use an R1 and R2 of 10kΩ~30kΩ.An R3
of 20 to 100kΩ and C of 1000pF to 8200pF should be used.
To change the knee point of frequency drop,use the circuit in
Fig.30.
To have a normal SOFT start function in the circuit in Fig.29,use
the circuit in Fig.31.It is recommended to use an R4 of 10kΩ.
Fig.29 Current to lower frequency during over current
SOFT
SOFT
VOUT
VOUT
TO MAKE THE KNEE POINT HIGH
SOFT
VOUT
TO MAKE THE KNEE POINT LOW
Fig.30 Method to control the knee point of
frequency drop
D2 BIAS WINDING OF
THE MAIN TRANSFORMER
Vcc
COLLECTOR
CVcc
VOUT
TO OUTPUT TRANSISTOR
M51996A
SOFT
R4
R3
C
REG
F/B
R1
RSOFT
Q2
CSOFT
R2
Q1
D1
PHOTO-COUPLER
FOR FEED BACK SIGNAL
Fig.31 Circuit to use frequency drop during the over
current and normal soft start
( 18 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
(b)In case of fly back system
Output circuit
The DC output voltage of SMPS depends on the Vcc voltage of
type M51996A when the polarity of the third winding is negative
and the system is fly back.So the operation of type M51996A
will stop when the Vcc becomes lower than "Operation-stop
voltage" of M51996A when the DC output voltage of SMPS
decreases under specified value at over load condition.
However,the M51996A will non-operate and operate
intermittently,as the Vcc voltage rises in accordance with the
decrease of Icc current.
The fly back system has the constant output power
characteristics as shown in Fig.32 when the peak primary
current and the operating frequency are constant.
Toavoid anincrease of the output current,the frequency is
lowered when the DC output voltage of SMPS starts to drop
using the SOFT terminal.Vcc is divided and is input to the SOFT
terminal as shown in Fig.33,because the voltage in proportional
to the output voltage is obtained from the bias winding.In this
application example,the current flowing to R3 added to the startup current.So please use high resistance or 100kΩ to 200kΩ for
R3.
The start-up current is not affected by R3 if R3 is connected to
Cvcc2 in the circuit shown in Fig.20.
(1)The output terminal characteristics at the Vcc voltage
lower than the "Operation-stop" voltage
POINT THAT Vcc VOLTAGE
OR THIRD WINDING
VOLTAGE DECREASES
UNDER "OPERATION-STOP
VOLTAGE"
DC OUTPUT CURRENT
TO MAIN
TRANSFORMER
VOUT
M51996A
100kΩ
RCLM
Fig.34 Circuit diagram to prevent the MOS-FIT gate
potential rising
The output terminal has the current sink ability even though the
Vcc voltage lower than the "Operation-stop" voltage or Vcc(STOP)
(It means that the terminal is "Output low state" and please refer
characteristics of output low voltage versus sink current.)
This characteristics has the merit not to damage the MOS-FIT
at the stop of operation when the Vcc voltage decreases lower
than the voltage of Vcc(STOP),as the gate charge of MOSFIT,which shows the capacitive load characteristics to the
output terminal,is drawn out rapidly.
The output terminal has the draw-out ability above the Vcc
voltage of 2V,however,lower than the 2V,it loses the ability and
the output terminal potential may rise due to the leakage
current.
In this case, it is recommended to connect the resistor of 100kΩ
between gate and source of MOS-FIT as shown in Fig.34.
Fig.32 Over current limitting curve on fly back system
Vcc
COLLECTOR
M51996A
SOFT
R3
CVcc
R4
F/B
R1
REG
R2
To photo-coupler for feed back signal
Fig.33 Current to lower the frequency during the
over current in the fly back system
(2)MOS-FIT gate drive power dissipation
Fig.35 shows the relation between the applied gate voltage
and the stored gate charge.
In the region 1 ,the charge is mainly stored at CGS as the
depletion is spread and CGD is small owing to the off-state of
MOS-FIT and the high drain voltage.
In the region 2 ,the CGD is multiplied by the "mirror effect" as
the characteristics of MOS-FIT transfers from off-state to onstate.
In the region 3 ,both the CGD and CGS affect to the
characteristics as the MOS-FIT is on-state and the drain
voltage is low.
The charging and discharging current caused by this gate
charge makes the gate power dissipation.The relation between
gate drive current ID and total gate charge QGSH is shown by
following equation;
ID=QGSH • fOSC .....................................(11)
Where
fOSC is switching frequency
( 19 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
As the gate drive current may reach up to several tenths
milliamperes at 500kHz operation,depending on the size of
MOS-FIT,the power dissipation caused by the gate current can
not be neglected.
In this case,following action will be considered to avoid heat
up of type M51996A.
R1
F/B
M51996A
DETECTING
VOLTAGE
C1
C
DET
C2
R3
B
C4
20
R2
DRAIN
VDS=80V
VDS=200V
VDS=320V
15
Fig.37 How to use the DET circuit for the voltage
detector
ID
CGD
CDS
3
GATE
10
VD
CGS
VGS
2
SOURCE
5
1
ID=4A
0
0
4
8
12
16
Fig.38 shows the gain-frequency characteristics between point
B and point C shown in Fig.37.
The G1, 1 and 2 are given by following equations;
R3
G1=
R1/R2 .............................................(10)
1
1=
C2 • R3 ............................................(11)
C1 + C2
2=
C1 • C2 • R3 ....................................(12)
At the start of the operation,there happen to be no output pulse
due to F/B terminal current through C1 and C2,as the potential
of F/B terminal rises sharply just after the start of the operation.
Not to lack the output pulse,is recommended to connect the
capacitor C4 as shown by broken line.
Please take notice that the current flows through the R1 and R2
are superposed to Icc(START).Not to superpose,R1 is connected
to Cvcc2 as shown in Fig.20.
20
TOTAL STORED GATE CHARGE(nC)
Fig.35 The relation between applied gate-source
voltage and stored gate charge
GAVDET
(DC VOLTAGE GAIN)
(1) To attach the heat sink to type M51996A
(2) To use the printed circuit board with the good
thermal conductivity
(3) To use the buffer circuit shown next section
G1
(3)Output buffer circuit
It is recommended to use the output buffer circuit as shown in
Fig.36,when type M51996A drives the large capacitive load or
bipolar transistor.
Log
1
2
Fig.38 Gain-frequency characteristics between
point B and C shown in Fig.37
How to get the narrow pulse width during the
start of operation
Fig.39 shows how to get the narrow pulse width during the start
of the operation.If the pulse train of forcedly narrowed pulsewidth continues too long,the misstart of operation may
happen,so it is recommended to make the output pulse width
narrow only for a few pulse at the start of operation.0.1µF is
recommended for the C.
VOUT
M51996A
Fig.36 Output buffer circuit diagram
DET
Fig.37 shows how to use the DET circuit for the voltage detector
and error amplifier.
For the phase shift compensation,it is recommended to
connected the CR network between det terminal and F/B
terminal.
( 20 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
Driver circuit for bipolar transistor
F/B
M51996A
When the bipolar transistor is used instead of MOS-FIT,the
base current of bipolar transistor must be sinked by the
negative base voltage source for the switching-off duration,in
order to make the switching speed of bipolar transistor fast one.
In this case,over current can not be detected by detecting
resistor in series to bipolar transistor,so it is recommended to
use the CT(current transformer).
For the low current rating transistor,type M51996A can drive it
directly as shown in Fig.42.
100Ω
TO PHOTO
COUPLER
C
Fig.39 How to get the narrow pulse width
during the start of operation
How to synchronize with external circuit
Type M51996A has no function to synchronize with external
circuit,however,there is some application circuit for
synchronization as shown in Fig.40.
COLLECTOR
Vcc
VOUT
M51996A
M51996A
CF
T-ON
BIPOLAR
TRANSISTOR
EMITTER
GND
T-OFF
Fig.42 Driver circuit diagram (2) for bipolar transistor
RON
CF
ROFF
Q1
SYNCHRONOUS
PULSE
0V
0V
MINIMUM PULSE
WIDTH OF
SYNCHRONOUS
PULSE
MAXIMUM PULSE WIDTH OF
SYNCHRONOUS PULSE
Fig.40 How to synchronize with external circuit
COLLECTOR
Vcc
Vcc
VOUT
M51996A
-Vss
(-2V to -5V)
GND
EMITTER
Fig.41 Driver circuit diagram (1) for bipolar transistor
( 21 / 22 )
MITSUBISHI (Dig./Ana. INTERFACE)
M51996AP/FP
SWITCHING REGULATOR CONTROL
Attention for heat generation
The maximum ambient temperature of type M51996A is
+85°C,however,the ambient temperature in vicinity of the IC is
not uniform and varies place by place,as the amount of power
dissipation is fearfully large and the power dissipation is
generated locally in the switching regulator.
So it is one of the good idea to check the IC package
temperature.
The temperature difference between IC junction and the surface
of IC package is 15°C or less,when the IC junction temperature is
measured by temperature dependency of forward voltage of pin
junction,and IC package temperature is measured by "thermoviewer",and also the IC is mounted on the "phenol-base" PC
board in normal atmosphere.
So it is concluded that the maximum case temperature(surface
temperature of IC) rating is 120°C with adequate margin.
( 22 / 22 )