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HAT2210R, HAT2210RJ Silicon N Channel Power MOS FET with Schottky Barrier Diode High Speed Power Switching REJ03G0578-0300 Rev.3.00 Mar.15.2005 Features • • • • Low on-resistance Capable of 4.5 V gate drive High density mounting Built-in Schottky Barrier Diode Outline RENESAS Package code: PRSP0008DD-A (Package name: SOP-8<FP-8DA>) 7 8 D D 5 6 D D 2 G 8 4 G 5 7 6 3 1 2 S 1 4 1, 3 2, 4 5, 6, 7, 8 Source Gate Drain S 3 MOS1 MOS2 and Schottky Barrier Diode Absolute Maximum Ratings (Ta = 25°C) Ratings Item Drain to source voltage Gate to source voltage Drain current Drain peak current Reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Symbol VDSS VGSS ID ID(pulse)Note1 IDR IAP Note 2 Note 2 EAR Pch Note3 Tch Tstg HAT2210R HAT2210RJ MOS1 30 ±20 7.5 60 7.5 — MOS2 & SBD 30 ±12 8.0 64 8.0 — MOS1 30 ±20 7.5 60 7.5 7.5 MOS2 & SBD 30 ±12 8.0 64 8.0 8.0 V V A A A A — 1.5 150 –55 to +150 — 1.5 150 –55 to +150 5.62 1.5 150 –55 to +150 6.4 1.5 150 –55 to +150 mJ W °C °C Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. Value at Tch = 25°C, Rg ≥ 50 Ω 3. 1 Drive operation; When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW ≤ 10 s Rev.3.00, Mar.15.2005, page 1 of 11 Unit HAT2210R, HAT2210RJ Electrical Characteristics • MOS1 (Ta = 25°C) Item Drain to source breakdown voltage Gate to source leak current Zero gate voltage drain current HAT2210R Zero gate voltage drain current HAT2210RJ Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body–drain diode forward voltage Body–drain diode reverse recovery time Notes: 4. Pulse test Rev.3.00, Mar.15.2005, page 2 of 11 Symbol V(BR)DSS IGSS IDSS IDSS Min 30 — — — Typ — — — — Max — ±0.1 1 — Unit V µA µA µA IDSS — — 10 µA VGS(off) RDS(on) 1.0 — — 9 — — — — — — — 19 27 15 630 155 57 4.6 2.2 1.2 2.5 24 40 — — — — — — — V mΩ mΩ S pF pF pF nC nC nC VDS = 10 V, ID = 1 mA ID = 3.75 A, VGS = 10 V Note4 ID = 3.75 A, VGS = 4.5 V Note4 ID = 3.75 A, VDS = 10 V Note4 — — — — — — 7 14 36 3.4 0.85 17 — — — — 1.11 — ns ns ns ns V ns VGS =10 V, ID = 3.75 A, VDD ≈ 10 V, RL = 2.66 Ω, Rg = 4.7 Ω RDS(on) |yfs| Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDF trr Test Conditions ID = 10 mA, VGS = 0 VGS = ±20 V, VDS = 0 VDS = 30 V, VGS = 0 VDS = 24 V, VGS = 0, Ta = 125°C VDS = 10 V, VGS = 0, f = 1MHz VDD = 10 V, VGS = 4.5 V, ID = 7.5 A IF = 7.5 A, VGS = 0 Note4 IF =7.5 A, VGS = 0 diF/ dt = 100 A/µs HAT2210R, HAT2210RJ • MOS2 & Schottky Barrier Diode (Ta = 25°C) Item Drain to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Symbol V(BR)DSS IGSS IDSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf Schottky Barrier diode forward voltage VF Body–drain diode reverse recovery time Notes: 4. Pulse test trr Rev.3.00, Mar.15.2005, page 3 of 11 Min 30 — — 1.4 — — 15 — — — — — — — — — — Typ — — — — 17 21 25 1330 230 92 11 3.8 3.2 10 16 43 3.9 Max — ±0.1 1 2.5 22 29 — — — — — — — — — — — Unit V µA mA V mΩ mΩ S pF pF pF nC nC nC ns ns ns ns — — 0.5 15 — — V ns Test Conditions ID = 10 mA, VGS = 0 VGS = ±12 V, VDS = 0 VDS = 30 V, VGS = 0 VDS = 10 V, ID =1 mA ID =4 A, VGS = 10 V Note4 ID = 4 A, VGS = 4.5 V Note4 ID = 4 A, VDS = 10 V Note4 VDS = 10 V, VGS = 0, f = 1MHz VDD = 10 V, VGS = 4.5 V, ID = 8 A VGS = 10 V, ID = 4 A, VDD ≈ 10 V, RL = 2.5 Ω, Rg = 4.7 Ω IF = 3.5 A, VGS = 0 Note4 IF = 8 A, VGS = 0 diF/ dt = 100 A/µs HAT2210R, HAT2210RJ Main Characteristics • MOS1 Power vs. Temperature Derating 3.0 ID (A) Test Condition : When using the glass epoxy board (FR4 40x40x1.6 mm), PW < 10 s 100 2.0 1.0 10 µs 10 Drain Current Pch (W) Channel Dissipation Maximum Safe Operation Area 1000 4.0 PW DC =1 1 m 100 µs s 0m s( 1s ho tio t) n( P Operation in W N ≤ 1 ote this area is 0s 5 ) 0.1 limited by RDS(on) Op era 1 Ta = 25°C 0 50 100 Ambient Temperature 150 200 0.01 1 shot Pulse 0.1 1 10 100 Drain to Source Voltage VDS (V) Ta (°C) Note 5 : When using the glass epoxy board (FR4 40x40x1.6 mm) Typical Output Characteristics 20 Typical Transfer Characteristics 20 4.5 V 3.2 V 10 VGS = 2.8 V Drain Current ID (A) ID (A) Drain Current VDS = 10 V Pulse Test 3.6 V 10 V 10 Pulse Test 200 5 Drain to Source Voltage VDS Drain to Source Saturation Voltage vs Gate to Source Voltage Pulse Test 150 100 ID = 5 A 50 2A 1A 0 12 4 8 Gate to Source Voltage Rev.3.00, Mar.15.2005, page 4 of 11 0 10 (V) 16 20 VGS (V) 8 VGS 10 (V) Static Drain to Source on State Resistance vs. Drain Current 100 Static Drain to Source on State Resistance RDS(on) (mΩ) Drain to Source Voltage VDS(on) (mV) 0 Tc = 75°C 25°C −25°C 2 4 6 Gate to Source Voltage VGS = 4.5 V 10 V 10 1 0.1 Pulse Test 1 Drain Current 10 ID (A) 100 40 VGS = 4.5 V 30 20 1 A, 2 A, 5 A 10 V 10 0 -25 Forward Transfer Admittance vs. Drain Current 100 Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance vs. Temperature 50 5A Pulse Test ID = 1 A, 2 A 50 Tc = –25°C 20 10 5 25°C 2 75°C 1 0.5 0.1 0.1 0.2 0.5 1 0 25 50 75 100 125 150 Case Temperature Tc (°C) 50 100 ID (A) Typical Capacitance vs. Drain to Source Voltage VGS = 0 f = 1 MHz 5000 50 20 10 5 di / dt = 100 A / µs VGS = 0, Ta = 25°C 2 2000 1000 Ciss 500 200 Coss 100 Crss 50 20 10 0 0.3 1 3 10 30 100 Reverse Drain Current IDR (A) Dynamic Input Characteristics 16 VGS 30 12 VDS 20 8 10 0 4 VDD = 25 V 10 V 5V 4 8 Gate Charge Rev.3.00, Mar.15.2005, page 5 of 11 12 16 Qg (nC) 0 20 50 Switching Time t (ns) VDD = 25 V 10 V 5V 40 Switching Characteristics (V) ID = 7.5 A 5 10 15 20 25 30 Drain to Source Voltage VDS (V) 100 20 VGS 50 Gate to Source Voltage VDS (V) 5 10 20 10000 1 0.1 Drain to Source Voltage 2 Drain Current Body-Drain Diode Reverse Recovery Time 100 VDS = 10 V Pulse Test 0.2 Capacitance C (pF) Reverse Recovery Time trr (ns) Static Drain to Source on State Resistance RDS(on) (mΩ) HAT2210R, HAT2210RJ td(off) tr 20 10 td(on) 5 tf 2 VGS = 10 V, VDD = 10 V Rg =4.7 Ω, duty ≤ 1 % 1 0.1 0.2 0.5 1 2 5 10 20 Drain Current ID (A) 50 100 HAT2210R, HAT2210RJ Maximum Avalanche Energy vs. Channel Temperature Derating Repetitive Avalanche Energy EAR (mJ) Reverse Drain Current vs. Source to Drain Voltage Reverse Drain Current IDR (A) 20 10 V 5V VGS = 0 V, –5 V 10 Pulse Test 0 0.4 0.8 1.2 Source to Drain Voltage 1.6 2.0 10 IAP = 7.5 A VDD = 15 V duty < 0.1 % Rg > 50 Ω 8 6 4 2 0 25 VSD (V) 50 75 100 125 150 Channel Temperature Tch (°C) Normalized Transient Thermal Impedance γs (t) Normalized Transient Thermal Impedance vs. Pulse Width 10 1 D=1 0.5 0.2 0.1 0.1 θch - f(t) = γs (t) x θch - f θch - f = 125°C/W, Ta = 25°C When using the glass epoxy board (FR4 40x40x1.6 mm) 0.05 0.02 0.01 0.01 t ho lse PDM pu D= 1s PW T PW T 0.001 10 µ 100 µ 1m 10 m 100 m 1 Pulse Width PW (S) Rev.3.00, Mar.15.2005, page 6 of 11 10 100 1000 10000 HAT2210R, HAT2210RJ • MOS2 & Schottky Barrier Diode Power vs. Temperature Derating 3.0 ID (A) Test Condition : When using the glass epoxy board (FR4 40x40x1.6 mm), PW < 10 s 100 2.0 1.0 10 µs 10 Drain Current Pch (W) Channel Dissipation Maximum Safe Operation Area 1000 4.0 PW DC 1m s 0µ s =1 0m s( 1s ho tio t) n( PW Operation in N ≤ 1 ote this area is 0s 5 ) 0.1 limited by RDS(on) Op era 1 Ta = 25°C 0.01 1 shot Pulse 0 50 100 150 Ambient Temperature 0.1 200 1 Ta (°C) Typical Transfer Characteristics Pulse Test 10 V VDS = 10 V Pulse Test 2.8 V 10 2.6 V ID (A) 3.0 V ID (A) 100 20 Drain Current 4.5 V 10 Drain to Source Voltage VDS (V) Note 5 : When using the glass epoxy board (FR4 40x40x1.6 mm) Typical Output Characteristics 20 Drain Current 10 10 Tc = 75°C 25°C VGS = 2.4 V −25°C 200 5 Drain to Source Voltage VDS Drain to Source Saturation Voltage vs Gate to Source Voltage Pulse Test 150 100 ID = 5 A 50 0 2A 1A 6 2 4 8 10 12 Gate to Source Voltage VGS (V) Rev.3.00, Mar.15.2005, page 7 of 11 0 10 (V) 2 4 6 Gate to Source Voltage 8 VGS 10 (V) Static Drain to Source on State Resistance vs. Drain Current 100 Pulse Test Static Drain to Source on State Resistance RDS(on) (mΩ) Drain to Source Voltage VDS(on) (mV) 0 VGS = 4.5 V 10 1 0.1 10 V 1 Drain Current 10 ID (A) 100 40 5A ID = 1 A, 2 A 30 VGS = 4.5 V 20 1 A, 2 A, 5 A 10 V 10 0 -25 Forward Transfer Admittance vs. Drain Current 100 Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance vs. Temperature 50 Pulse Test 50 Tc = –25°C 20 10 5 25°C 2 75°C 1 0.5 0.1 0.1 0.2 0.5 1 0 25 50 75 100 125 150 Case Temperature Tc (°C) 50 100 ID (A) Typical Capacitance vs. Drain to Source Voltage VGS = 0 f = 1 MHz 5000 50 20 10 5 di / dt = 100 A / µs VGS = 0, Ta = 25°C 2 Ciss 2000 1000 500 200 Coss 100 Crss 50 20 10 0 0.3 1 3 10 30 100 Reverse Drain Current IDR (A) Dynamic Input Characteristics 30 8 VDD = 25 V 10 V 5V VGS 6 VDS 20 4 VDD = 25 V 10 V 5V 10 0 4 8 Gate Charge Rev.3.00, Mar.15.2005, page 8 of 11 12 2 16 Qg (nC) 0 20 50 Switching Time t (ns) 40 Switching Characteristics (V) ID = 8 A 5 10 15 20 25 30 Drain to Source Voltage VDS (V) 100 10 VGS 50 Gate to Source Voltage VDS (V) 5 10 20 10000 1 0.1 Drain to Source Voltage 2 Drain Current Body-Drain Diode Reverse Recovery Time 100 VDS = 10 V Pulse Test 0.2 Capacitance C (pF) Reverse Recovery Time trr (ns) Static Drain to Source on State Resistance RDS(on) (mΩ) HAT2210R, HAT2210RJ td(off) tr 20 td(on) 10 5 tf 2 VGS = 10 V, VDD = 10 V Rg =4.7 Ω, duty ≤ 1 % 1 0.1 0.2 0.5 1 2 5 10 20 Drain Current ID (A) 50 100 HAT2210R, HAT2210RJ Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current vs. Source to Drain Voltage 10 V VGS = 0 V, –5 V 5V 10 Pulse Test 0 0.4 0.8 1.2 Source to Drain Voltage 1.6 2.0 10 Repetitive Avalanche Energy EAR (mJ) Reverse Drain Current IDR (A) 20 IAP = 8 A VDD = 15 V duty < 0.1 % Rg > 50 Ω 8 6 4 2 0 25 VSD (V) 50 75 100 125 150 Channel Temperature Tch (°C) Normalized Transient Thermal Impedance γs (t) Normalized Transient Thermal Impedance vs. Pulse Width 10 1 D=1 0.5 0.2 0.1 0.1 θch - f(t) = γs (t) x θch - f θch - f = 125°C/W, Ta = 25°C When using the glass epoxy board (FR4 40x40x1.6 mm) 0.05 0.02 0.01 0.01 e uls PDM p ot D= h 1s PW T PW T 0.001 10 µ 100 µ 1m 10 m 100 m 1 Pulse Width PW (S) Rev.3.00, Mar.15.2005, page 9 of 11 10 100 1000 10000 HAT2210R, HAT2210RJ • Common Avalanche Test Circuit Avalanche Waveform EAR = L VDS Monitor 1 2 L • IAP2 • VDSS VDSS – VDD I AP Monitor V (BR)DSS IAP Rg VDS VDD D. U. T ID Vin 10 V 50 Ω 0 VDD Switching Time Test Circuit Vout Monitor Vin Monitor Rg Switching Time Waveform 90% D.U.T. RL Vin Vin 10 V V DS = 10 V Vout 10% 10% 90% td(on) Rev.3.00, Mar.15.2005, page 10 of 11 tr 10% 90% td(off) tf HAT2210R, HAT2210RJ Package Dimensions JEITA Package Code RENESAS Code Package Name P-SOP8-3.95 × 4.9-1.27 PRSP0008DD-A FP-8DA MASS[Typ.] F 0.085g *1 D bp b1 5 Index mark 1 Z c1 c HE *2 E 8 4 *3 Terminal cross section bp NOTE) 1. DIMENSIONS "*1(Nom)" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. x M e Reference Symbol L1 Dimension in Millimeters Min Nom Max D 4.90 5.3 E 3.95 A2 A1 0.10 0.14 0.25 0.34 0.42 0.50 1.75 A A A1 bp L 0.40 b1 c 0.19 c1 0.25 0.20 0° Detail F y 0.22 HE 5.80 e 8° 6.10 6.20 1.27 x 0.25 y 0.1 Z 0.75 L L1 0.40 0.60 1.27 1.08 Ordering Information Part Name HAT2210R-EL-E HAT2210RJ-EL-E Quantity 2500 pcs 2500 pcs Shipping Container Taping Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.3.00, Mar.15.2005, page 11 of 11 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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