STMICROELECTRONICS STA011

STA011
L-band RF front-end for digital radio
Preliminary Data
Features
●
Single chip receiver for satellite and
terrestrial digital radio
●
Super-heterodyne tuner with low IF output
●
High input intercept point
●
Low noise IC
●
RF image rejection mixer
●
Adjustable RF and IF gain
●
54 dB IF VGA gain range
●
Integrated RF and IF VCOs
●
Integrated synthesizers
●
Low cost external components
●
I2C-bus slave control interface
●
Unregulated 2.7 to 3.3V supply voltage
Table 1.
TQFP44
Description
The STA011 is an RF IC using
STMicroelectronics BiCMOS6G high speed
technology for one chip solution for the digital
satellite radio receiver. The STA011 is assembled
in a TQFP44 package. The front-end architecture
is a double conversion receiver (see block
diagram). The chip includes all the RF functions
up to low IF and it manages the signals going to
and coming from the base-band.
Device summary
Order code
Package
Packing
STA011
TQFP44 (10x10x1.4mm)(1)
Tube
1. ECOPACK® (see Chapter 8).
November 2007
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/38
www.st.com
1
Contents
STA011
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
3.1
Absolute maximum/minimum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Receiver chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
Synthesizers, PLL, charge pump and VCOs . . . . . . . . . . . . . . . . . . . . . . 16
4.3
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4
Interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
5.2
I2C-bus specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.1
Power ON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.2
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.3
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.4
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.5
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.6
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.7
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.8
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.9
Write operation (single byte write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.10
Write operation (multibyte write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.11
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.12
Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.13
Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.14
ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2.1
2/38
Write mode (multibyte write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STA011
Contents
5.3
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.1
6
Bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Programming specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1
6.2
6.3
RFPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.1
Loop divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.2
Reference divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.3
Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4
VCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5
VCO output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.6
Charge pump current setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.7
PFD programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1.8
Fractional spurious compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RF path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.1
Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.2
RF gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2.3
IF buffer setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
IF path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.1
Blocks disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4
Lock detector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5
IF PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.1
IFVCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.2
PFD programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.3
Charge pump enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.4
Reference divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.5
Loop divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6
XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.7
Startup configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/38
List of tables
STA011
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
4/38
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum/minimum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Supply currents, (Tamb = 25°C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
LNA, RF mixer and IF1 buffer, (Tamb = 25°C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . 10
IFVGA amplifiers, IF mixer and output buffer (Tamb = 25°C, VP-VN = 3V). . . . . . . . . . . . . 11
Base-band output performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Crystal oscillator, (T=25°C, VP-VN=3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PLLs, Synthesizers, (Tamb = 25°C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RF VCO, (Tamb = 25°C°C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
IF VCO, (Tamb = 25°C, VP-VN = 3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital interface to MP (SCL,SDA,TLCK), ENRFOSC and XOSEL interface . . . . . . . . . . . 14
Additional optional interface (REF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timing electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Start and stop electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ACK electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6th data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reference divider division ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VCO output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Charge pump current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Frequency phase detector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fractional spurious compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DAC current adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Down Asym delay setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Blocks enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
RF gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
IF Buffer setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Blocks disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Lock detector setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IFVCO enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Frequency phase detector setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Charge pump enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reference divider division ratio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Loop divider division ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Startup configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STA011
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical IF overall gain vs control voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System clock input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Validity on I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timing diagram of the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ack on I2Cbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TQFP44 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5/38
Block diagram
1
STA011
Block diagram
Figure 1.
Block diagram
SIP,SIN
LNI
RFMixer
SOP,SON
IF1 Buffer
IFAGC
VGAs
IF2 Buffer
IFMixer
RXI,NRXI
LNA
NLNI
2nd PLL
/8
N2
PADJ1,2
I2CBUS
PFD
INTERFACE
DIGITAL
Charge
Pump
CIRCUITRY
SCL
VCO
FLT2
SDA
R2
M_CLK1,2
1st PLL
/2
N1
VCO
Charge
Pump
FLT1
PFD
R1
MUX
MUX
XOSEL
OSC
REF
XTAL1,2
AC00335
6/38
STA011
Pins description
FLT2
VP4
TK2
NTK2
VP4
AGC2
AGC1
VN4
SON
SOP
Pins connection (top view)
VN4
Figure 2.
44 43 42 41 40 39 38 37 36 35 34
VP1
1
33
RXI
SIP
2
32
NRXI
SIN
3
31
GADJ2
VN1
4
30
GADJ1
LNI
5
29
CE
NLNI
6
28
VP3
VN1
7
27
SCL
Address
8
26
SDA
PADJ1
9
25
VN3
PADJ2
10
24
M_CLK1
ENRFOSC
11
23
M_CLK2
Table 2.
TLCK
XOSel
REF
XTAL2
XTAL1
VN2
FLT1
VP2
NTK1
TK1
12 13 14 15 16 17 18 19 20 21 22
VP2
2
Pins description
AC00336
Pins description
N.
Name
Function
1
VP1
Positive supply 1
2
SIP
SAW filter input connection
3
SIN
SAW filter input connection
4
VN1
Negative supply1
5
LNI
RF input
6
NLNI
RF input
7
VN1
Negative supply 1
8
Address
9
PADJ1
RF gain adjust connection1
10
PADJ2
RF gain adjust connection2
11
ENRFOSC
12
VP2
Positive supply 2
13
TK1
External LO1 connection1
14
NTK1
External LO1 connection2
15
VP2
Positive supply 2
16
FLT1
1st PLL loop filter connection
17
VN2
Negative supply 2
Device address selection
RF oscillator hardware enable
7/38
Pins description
Table 2.
8/38
STA011
Pins description (continued)
N.
Name
Function
18
XTAL1
Quartz oscillator connection 1
19
XTAL2
Quartz oscillator connection 2
20
REF
External optional TCXO input
21
XOSel
Internal/external XO selection
22
TLCK
Lock detector output
23
M_CLK2
Master Clock differential output2
24
M_CLK1
Master Clock differential output1
25
VN3
Negative supply 3
26
SDA
Data Serial Input
27
SCL
Clock Input
28
VP3
Positive supply 3
29
CE
Chip Enable
30
GADJ1
IF gain adjust connection 1
31
GADJ2
IF gain adjust connection 2
32
NRXI
Low IF Signal output 2
33
RXI
Low IF Signal output 1
34
FLT2
2nd PLL loop filter connection
35
VP4
Positive supply 4
36
TK2
External LO2 connection1
37
NTK2
External LO2 connection2
38
VP4
Positive supply 4
39
AGC1
VGA control pin 1
40
AGC2
VGA control pin 2
41
VN4
Negative supply 4
42
SON
SAW filter negative output connection 2
43
SOP
SAW filter output connection 1
44
VN4
Negative supply 4
STA011
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum/minimum ratings
Table 3.
Absolute maximum/minimum ratings
Symbol
Parameter
Min.
Tstg
Storage temperature
-40
Top
Operating ambient temperature
-40
VMax
Maximum voltage on each pin
VMin
Minimum voltage on each pin
Vpmax
VESD,HBM
Table 4.
Operating conditions
Parameter
VP
Operating supply voltage
Tj
Junction temperature
3.3
Thermal data
Table 5.
Thermal data
Rth j-amb
Unit
125
°C
85
°C
3.6
V
25
V
-0.3
3.6
Electrostatic discharge Voltage (ESD,
Human Body Model)
Operating conditions
Symbol
Max.
GND-0.3
Minimum/Maximum power supply
Between VP1,2,3,4 and VN1,2,3,4
3.2
Symbol
Typ.
Parameter
Thermal resistance junction to
ambient
Test conditions/notes
2
Min.
Typ.
2. 7
Test conditions/notes
According to JEDEC
specification on a layers
board
Min.
Typ.
45
kV
Max.
Unit
3.3
V
125
°C
Max.
Unit
°C/W
9/38
Electrical specifications
STA011
3.4
Electrical characteristics
Table 6.
Supply currents, (Tamb = 25°C, VP-VN = 3V)
Symbol
Parameter
Test conditions/notes
ICC1
Current supplied by VP1
Powered circuits: LNA, RFMixer,
IF buffer
Powered circuits: RFVCO, divider
by 2 and LO buffer
ICC2
ICC3
ICCTOT
ICCTOT,SB
Table 7.
Symbol
Typ.
Max.
Unit
12.5
17
21.5
mA
5.5
9
12.5
mA
Current supplied by VP2
Powered circuits: external LO1,
divider by 2 and LO buffer
11.5
15
18.5
Powered circuits: Digital cells,
Crystal oscillator (XOSel high)
5.5
7
11.5
Current supplied by VP3
mA
Powered circuits: Digital cells,
external REF (XOSel low)
ICC4
Min.
Powered circuits: VGAs, IFMixer,
output buffer, IFPLL
Current supplied by VP4
VAGC1=VAGC2=1.2V,
IFgain=75dB
ICC1+ ICC2+ ICC3+ ICC4
CE = high, XOSel high, RFVCO
enabled
Standby current
CE = low
3.5
6
8
8.5
13
17.5
mA
36
46
56
mA
20
µA
Max.
Unit
LNA, RF mixer and IF1 buffer, (Tamb = 25°C, VP-VN = 3V)
Parameter
Test conditions/notes
Min.
Typ.
BWi
Input signal BW
1452
1492
MHz
BW0
Output signal BW
114
116.5
MHz
GV
Voltage gain
Input LNI, NLNI pins; output SIP,
SIN pins.
RL = 200Ω, PADj1,2 pins floating
26
30
34
dB
GV,trim
Voltage gain
Input LNI, NLNI pins; output
SIP,SIN pins.
RL=200Ω, Rext=0
19
25
29
dB
ΔGV
Voltage gain
variation
Programmable via software mode
2.5
dB
Zi
Input impedance
Balanced @ LNi, NLNI pins, R//C
75
0.2
Ω
pF
Zo
Output impedance
Balanced @ SIP, SIN pins
50
Ω
Return loss
LNI,NLNI pins
14
dB
Noise figure
Measurements condition: Input
LNI, NLNI pins; output SIP,SIN
pins,RL=200Ω, PADj1,2 pins
floating, Rs=50Ω
5
γ
NF
10/38
7
dB
STA011
Table 7.
Symbol
Electrical specifications
LNA, RF mixer and IF1 buffer, (Tamb = 25°C, VP-VN = 3V) (continued)
Parameter
Test conditions/notes
Min.
Typ.
Max.
Unit
6.5
8.5
dB
Noise figure @
minimum gain
Measurements condition: Input
LNI, NLNI pins; output SIP,SIN
pins,RL=200Ω, Rext=0, Rs=50Ω
Input IP3
Input LNI, NLNI pins; output
SIP,SIN pins.
RL=200Ω, PADj1,2 pins floating
-21
-17
-12
dBm
Input IP3 @
minimum gain
Input LNI, NLNI pins; output
SIP,SIN pins.
RL=200Ω, Rext=0
-18
-14.5
-7
dBm
1dB C.P.
1dB compression
point
Input LNI, NLNI pins; output
SIP,SIN pins.
RL=200Ω,PADj1,2 pins floating
-29
-26
dBm
1dB C.P.trim
1dB compression
point
Input LNI, NLNI pins; output
SIP,SIN pins.
RL=200Ω, Rext=0
-27
-24
dBm
Image rejection
RFin = LO-IF
15
REXT trim
REXT usable range
Connected between PADJ1 and
PADJ2, to obtain intermediate
gain between min and max
10
IF1leak
NFtrim
IIP3
IIP3trim
IR
dB
100
kΩ
LO1 to IF1 leakage
-24
dBm
RFleak
LO1 to RF leakage
-29
dBm
VDC,RFin
LNI,NLNI common
mode DC voltage
AC coupled to the balun
VP-1.3
VP-1.1
VP-0.9
V
VDC,IFout
SIP,SIN common
mode DC voltage
AC coupled to the SAW filter
VP-1.45
VP-1.2
VP-0.95
V
Table 8.
Symbol
IFVGA amplifiers, IF mixer and output buffer (Tamb = 25°C, VP-VN = 3V)
Parameter
Test conditions/notes
Min.
Typ.
Max.
Unit
BWi
Input signal BW
114
116.5
MHz
BWo
Output BW
0.6
3.1
MHz
Gmin
Minimum gain
Input SOP, SON pins; output
RXI,RXIN pins, RLoad high
impedance, VAGC1,2 = 0V
38
dB
Gmax
Maximum gain
Input SOP, SON pins; output
RXI,RXIN pins, RLoad high
impedance, VAGC1,2 = 3V
IAGC
Input current in AGC pin
ZAGC
AGC input impedance
32
80
86
dB
10
150
600
µA
kΩ
11/38
Electrical specifications
Table 8.
STA011
IFVGA amplifiers, IF mixer and output buffer (Tamb = 25°C, VP-VN = 3V) (continued)
Symbol
Parameter
Test conditions/notes
Min.
Typ.
Max.
Unit
9
12
dB
Noise Figure
Measurements condition:
Input SOP, SON pins; output
RXI, NRXI pins, Rs=50Ω,
Double Side Band,
IFGain=65dB
1dB cp
1dB compression point
Gain=65dB
-53
-50
dBm
1dB cp,fg
1dB compression point,
full gain
Gain=81dB
-69
-66
dBm
IIP3
Input IP3
Gain=65dB
-45
-41
dBm
IIP3,fg
Input IP3
Gain=81dB
-61
-57
dBm
Zin
Input impedance
Balanced @ SOP, SON,
50
Ω
Zout
Output impedance
Balanced @ RXI, RXIN
Corresponding to 1.75mA in
each emitter follower
50
Ω
SIP, SIN common mode
DC voltage
AC coupled to the SAW filter
VP-1.3
VP-1.1
VP-0.9
V
VDC,RXout
RXI,NRXI common mode
AC coupled to the base-band
DC voltage
VP-2.1
VP-1.8
VP-1.65
V
VDC,PADJ
PADJ1,2 common mode
DC voltage
VP-0.3
VP-0.12
VP-0.5
V
650
800
950
W
NF
VDC,IFin
Gain adjustment pins
impedance
Balanced GADJ1, GADJ2
pins
BBleak
LO2 to BB leakage
Obtained by using low pass
filter at the output
-49
-30
dBm
IF2leak
LO2 to IF1 leakage
Obtained by using SAW filter
at the input
-44
-30
dBm
Zadj
Figure 3.
Typical IF overall gain vs control voltage
IF TOTAL VOLTAGE GAIN (dB)
IF TOTAL VOLTAGE GAIN (dB)
input SOP,NOP output RXI,NRXI
60
90
55
85
IF TOTAL VOLTAGE GAIN (dB)
IF TOTAL VOLTAGE GAIN (dB)
input SOP,NOP output RXI,NRXI
IF gain (dB)
50
45
40
80
IF gain (dB)
75
70
65
35
60
30
1
0.7
0.75
0.77
0.79
0.8
0.82
0.84
V(AGC1, AGC2) (Volt)
12/38
0.86
0.88
0.9
1.2
1.1
1.4
1.3
1.6
1.5
1.8
1.7
2
1.9
2.2
2.1
V(AGC1, AGC2) (Volt)
2.4
2.3
2.6
2.5
2.7
STA011
Table 9.
Electrical specifications
Base-band output performance
Symbol
Parameter
Test conditions/notes
Rload
Baseband Output load
resistance
The output resistance the
IC is loaded
SE to GND
Cload
Baseband output load
capacitance
The output capacitance the
IC is loaded
SE to GND
Table 10.
Symbol
Min.
Typ.
Max.
5
Unit
KΩ
10
pF
Max.
Unit
Crystal oscillator, (T=25°C, VP-VN=3V)(1)
Parameter
Test conditions/notes
Min.
Typ.
fXTAL1
Quartz frequency
Resonance mode: series
Using 14.72
14.72
MHz
fXTAL2
Quartz frequency
Resonance mode: series
Using 14.725
14.725
MHz
Phase Noise
Δf=1kHz
Pn
VDC,XTAL
XTAL1,2 common
mode voltage
VP-1.1
-120
-118
dBc
VP-.9
VP-.7
V
1. A 18pF capacitor connected from XTAL1 pin to gnd is suggested for start-up robustness (see Figure 4).
Figure 4.
System clock input/output
M_CLKP CD
REF
to baseband
Cp
Symbol
Output
Buffer
XTAL1
Table 11.
XTAL2
TCXO
MUX
yy
;;
;;
yy
;;
yy
18pF
AC00414
PLLs, Synthesizers, (Tamb = 25°C, VP-VN = 3V)
Parameter
Test conditions/notes
ts
RF pll loop setting
time
Pn
Total phase noise
contribution
100Hz<Δf<1.84MHz
fREF1
RF pll comparison
frequency
Programmable via software
mode
fREF2
IF pll comparison
frequency
Programmable via software
mode
PSP
Spurious power level
RFPLL, Δf=n*460KHz
IFPLL, Δf=113.23KHz
Min.
0.92
Typ.
Max.
Unit
1
10
msec
1.8
°rms
14.72
MHz
3.68
113.23
KHz
-50
-50
dBc
13/38
Electrical specifications
Table 11.
Symbol
STA011
PLLs, Synthesizers, (Tamb = 25°C, VP-VN = 3V) (continued)
Parameter
Test conditions/notes
Nprog1
RF PLL selectable
division ratios
From REF1 to LO1,
fcomp=3.68MHz
Nprog2
IF PLL selectable
division ratios
fcomp=113.23KHz
NREF1
REF1 division ratio
Programmable via software
mode
NREF2
REF2 division ratio
Programmable via software
mode
Table 12.
Symbol
fosc
Parameter
Test conditions/notes
VCO frequency
oscillation
LO1 frequency range
after divider by 2, by using
14.72MHz crystal
FLO1_2
LO1 frequency range
after divider by 2, by using
14.725MHz crystal
VFLT1
Freq control voltage
range
FLT1 pin
Symbol
fosc
Typ.
Max.
Unit
376.5
(373.75
last used)
360.75
(363.625
1st used)
987
1034
1081
1
4
16
130
RF VCO, (Tamb = 25°C°C, VP-VN = 3V)
FLO1_1
Table 13.
Min.
Min.
Typ.
Max.
Unit
2676.28
2750.8
MHz
1338.14
1375.4
MHz
1338.134375 to 1375.407031
VN+0.2
MHz
VP-0.2
V
IF VCO, (Tamb = 25°C, VP-VN = 3V)
Parameter
Test conditions/notes
VCO frequency
oscillation
Min.
Typ.
Max.
Unit
894.08
936.64
979.2
MHz
fLO2_1
LO2 frequency range
after divider by 8, by using
14.72MHz crystal
111.76
117.08
122.4
MHz
fLO2_2
LO2 frequency range
after divider by 8, by using
14.725MHz crystal
111.8
117.12
122.44
MHz
VFLT2
Frequency control
voltage range
FLT2 pin
VP-0.2
V
Table 14.
Symbol
VN+0.2
Digital interface to MP (SCL,SDA,TLCK), ENRFOSC and XOSEL interface
(Tamb = 25°C, VP-VN = 3V)
Parameter
Test conditions/notes
Min.
Typ.
Max.
Unit
Input parameters (SCL, SDA, ENRFOSC, XOSEL)
VIH
VIL
14/38
High
VP-.7
VP
V
Low
VN
VN+.7
V
0.1
µs/V
Digital input signals
Tt
Input edge transition
Rin
Input resistance
10
MΩ
STA011
Table 14.
Electrical specifications
Digital interface to MP (SCL,SDA,TLCK), ENRFOSC and XOSEL interface (continued)
(Tamb = 25°C, VP-VN = 3V)
Symbol
Parameter
Test conditions/notes
Min.
Typ.
Max.
Unit
Output parameter (TLCK)
VOH
High
VP-.7
VP
V
Low
VN
VN+.7
V
Digital output signals
VOL
tr
Rise time
C=5pF
0.4
0.6
µs/V
tf
Fall time
C=5pF
0.4
0.6
µs/V
Differential digital interface (M_CLK1, M_CLK2)
VOH
VOL
VDC,M_CLK
Digital output signals,
V(M_CLK1)-V(M_CLK2)
High
0.3
V
Low
-0.3
V
M_CLK1,2 Common mode
voltage
VP-1.65
VP-1.4
VP-1.2
tr
Rise time
Cl=5pF each pin
10
12
ns
tf
Fall time
C=5pF
10
12
ns
Zout
Output impedance
balanced
500
Ω
FM_CLK1
M_CLK frequency
Using a 14.72MHz
quartz
14.72
MHz
FM_CLK2
M_CLK frequency
Using a 14.725MHz
quartz
14.725
MHz
Table 15.
Additional optional interface (REF)
Symbol
Parameter
Test conditions/notes
Min.
Typ.
PREF
External reference input power
It must be AC coupled to
REF, XOSel low
-2
0
VDC
REF DC voltage
XOSel low
VP-1.2
VP-1.35
Rin
Input resistance
70
Max.
Unit
dBm
VP-1.6
V
kΩ
15/38
Functional description
4
Functional description
4.1
Receiver chain
STA011
The receiver chain transforms the RF frequency signals to an IF signal at 1.84 MHz carrier
directly usable by the channel decoder. In front of the STA011 IC there it must be an external
LNA and a band-pass filter; the band-pass filter limits the input bandwidth and guarantees a
suitable rejection to the image frequency. The STA011 input stage is a LNA working in the
1452-1492 MHz band. The RF signal is down-converted, using an active mixer, to a first IF
of 115.244 MHz. The first LO is tunable with a frequency step of 460 KHz. The RF gain can
be reduced by 5dB by using an external trimmer/resistor connected between the PADJ1 and
PADJ2 pins, and it can also be reduced by 7.5dB (2.5 step) via thesoftware mode.
A 54 dB typical gain range is guaranteed at IF level. By connecting an external
trimmer/resistor to pins GADJ1, GADJ2, the IF output signal level can be decreased to the
desired value.
Moreover, the IF chain can be configured to have a fixed gain by fixing statically control voltages on AGC1 and AGC2 pins (i.e. V(AGC1)=VCC and V(AGC2)=GND), and trimming the
gain by connecting an external resistor between GADJ1 and GADJ2.
By using an 800 Ohm resistor connected between GADJ1 and GADJ2, for example, a
typical 56 dBs IF static gain is obtained. The first IF signal, having a bandwidth of 2.5 MHz,
shaped by an external SAW filter, is down-converted to a second IF of 1.84 MHz.
A differential clock output of 14.72 MHz is available for use from the base-band.
4.2
Synthesizers, PLL, charge pump and VCOs
The first voltage controlled oscillator is controlled by an integrated PLL, and it's able to cover
a frequency range of 37 MHz with a step size of 460 KHz.
The second voltage controlled oscillator produces a fixed 8 x 117.08MHz frequency, scaled
by a divider by 8, and controlled by a second integrated PLL. Moreover, the 2nd PLL is able
cover the frequency range from 111.76MHz to 122.4MHz, suitable for anapplication test.
The other components of the first PLL synthesizer are a low frequency programmable
divider and a dual modulus prescaler; a fixed divider is instead used to synthesize the
second VCO fre-quency. Other internal programmable dividers are used to obtain the
comparison frequencies of both loops.
Channel selection is made through the I2CBUS interface, directly from the µP.
4.3
Power supplies
The chip operates from an unregulated power supply of 2.7 to 3.3 Volts. All interface circuits
to the base-band chips are operate between these supplies unless otherwise specified.
4.4
Interface specification
All the interface voltage levels to the micro controller are referenced to the supply voltage of
the interface power supply (GND). The interface voltage levels are therefore fully compatible
with the base-band circuits. The digital levels are all CMOS threshold compatible with the
ex-ception of M_CLK1, M_CLK2 pins (ECL type). For a total solution all other interface
signals are also included.
16/38
I2C-bus interface
STA011
5
I2C-bus interface
Data transmission from the microprocessor to the STA011 takes place through the 2 wires
(SDA and SCL) of the I2C-bus interface. The STA011 is always a slave device.
5.1
I2C-bus specifications
The I2C-bus protocol defines any device that sends data to the bus as a transmitter, and any
device that reads the data as a receiver. The device that controls the data transfer is known
as the Master and the others as the slave. The master will always initiate the transfer and
will provide the serial clock for synchronization.
5.1.1
Power ON reset
The device at Power ON is able to configure itself to a fixed configuration, with all the
circuitry ON and the RFPLL output frequency set to 1356.54MHz (fcomp=3.68MHz,
N=368.625)
5.1.2
Data validity
Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while
the clock is HIGH are used to identify START or STOP condition.
5.1.3
Start condition
Start is identified by a HIGH to LOW transition of the data bus SDA while the clock signal
SCL is stable in the HIGH state. A Start condition must precede any command for data
transfer.
5.1.4
Stop condition
A LOW to HIGH transition of the data bus SDA identifies a stop while the clock signal SCL is
stable in the HIGH state. A STOP condition terminates communications between the
STA011 and the Bus Master.
5.1.5
Byte format
Every byte transferred on the SDA line must contain bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
5.1.6
Acknowledge
An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either
master or slave, will release the SDA bus after sending 8 bits of data.
During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8
bits of data.
17/38
I2C-bus interface
5.1.7
STA011
Transmission without acknowledge
To avoid detecting an acknowledge from the STA011, the µP can use a simpler
transmission: simply it waits one clock period without checking the STA011 acknowledging,
and sends the new data. This approach of course is less protected from data corruption.
5.1.8
Device addressing
To start the communication between the master and the STA011, the master must initiate
with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first)
corre-sponding to the device select address and read or write mode.
The first 7 MSB`s are the device address identifier, corresponding to the I2C-bus definition.
For the STA011 these are fixed as 110000A. The A bit is reset to 0 internally by a pull-down
re-sistor but it can be changed through the corresponding external pin Address. In this way if
the Address pin is floating the address is fixed to the previous configuration (110000),
otherwise if the pin is set high the address is fixed to 1100001.
The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in
write mode). After a START condition the STA011 identifies on the Bus the device address
and, if matched, it will acknowledge the identification on the SDA bus during the 9th clock
pulse.
The following byte after the device identification byte, is the internal sub-address byte that
provides access to any of the internal registers.
5.1.9
Write operation (single byte write)
Following a START (S) condition the master sends a device select code with the RW bit set
to 0. The I2C gives the acknowledgement and waits for the 1 byte of internal sub address.
This byte provides access to any of the internal registers.
After the reception of the internal byte sub address the I2C again responds with an acknowledgement. The master terminates the transfer by generating a STOP (P) condition.
A single byte write with sub-address 00H would affect DATA_OUT[119:112], so a single byte
write with sub-address 02H would affect DATA_OUT[103:96] and so on
A single byte address with sub-address out of ranges 00H - 0FH produces
illegal_subaddress signal to go high and DATA_OUT[119:0] will not change until a
successive write operation request with the correct range for sub-address will be made.
For example if the sub-address is 15H will be produced illegal_subaddress = '1' and
DATA_OUT will no change.
S
5.1.10
110000A
R/W 0
ack
Sub-address byte
ack
DATA IN
ack
P
Write operation (multibyte write)
The multi-byte write mode can start from any internal sub address (the same as a single
byte write).
Following a START (S) condition the master sends a device select code with the RW bit set
to 0. The I2C gives the acknowledgement and waits for 1 byte from the internal sub address.
This byte provides the starting byte of the internal registers.
18/38
I2C-bus interface
STA011
The master sends the data and each byte isacknowledged by the I2C. The master
terminates the transfer by generating a STOP (P) condition.
The sub-address decides the starting byte. A Multi-byte with sub-address 00H and 5
DATA_IN bytes would affect the bytes starting from DATA_OUT [119:112] to DATA_OUT
[87:80] and so on. A Multi byte with sub-address from the ranges 00H - 0FH produces illegal
sub-address signal to go high, and DATA_OUT[119:0] will not change until a successive
write operation request, with the correct range for sub-address will be made.
S
110000A
5.1.11
R/W 0
ack
Sub-address byte
ack
DATA IN
ack
...………
DATA IN
ack
P
Read operation
Current byte address read
For the I2C of STA011 this is the only read mode operation implemented. In the current byte
address read mode, following a START condition, the master sends the device address with
the RW bit set to 1. The I2C acknowledges this and outputs the byte data by reading from
the internal byte address counter. The master does not acknowledge the received byte, but
terminates the transfer with a STOP condition.
S
110000A
R/W 1
ack
DATA
No ack
P
This method operation is not used.
Data validity
Figure 5.
Validity on I2C-bus
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Timing diagram of the I2C-bus:
Figure 6.
Timing diagram of the I2C-bus
SCL
I2CBUS
SDA
START
D99AU1032
STOP
19/38
I2C-bus interface
STA011
Acknowledge on the I2C-bus:
Figure 7.
Ack on I2Cbus
SCL
1
2
3
7
8
9
SDA
MSB
START
5.1.12
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
Timing specification
Figure 8.
Data and clock
SDA
SCL
tcwl
tcs
Table 16.
tcwh
AC00337
Timing electrical characteristics
Symbol
5.1.13
tch
Parameter
Minimum time (ns)
tcs
Data to clock set up time
100
tch
Data to clock hold time
50
tcwh
Clock pulse width high
100
tcwl
Clock pulse width low
100
Start and stop
Figure 9.
Start and stop
SDA
SCL
tstart1 tstart2
20/38
tstop2tstop1
AC00338
I2C-bus interface
STA011
Table 17.
Start and stop electrical characteristics
Symbol
5.1.14
Parameter
Minimum time (ns)
Tstart1,2
Clock to data start time
100
Tstop1,2
Data to clock down stop time
100
ACK
Figure 10. ACK
SDA
SCL
8
9
td1
Table 18.
td2
AC00339
ACK electrical characteristics
Symbol
Parameter
Maximum time (ns)
td1
Ack begin delay
200
td2
Ack end delay
200
21/38
I2C-bus interface
STA011
5.2
Software specification
5.2.1
Write mode (multibyte write)
MSB
S
1
device address
1
0
0
0
LSB
0
A
0
1st data byte
MSB
MSB
ack
LSB
S7
sub-address byte
S6
S5
S4
S3
LSB
S2
S1
2nd data byte
MSB
S0
ack
LSB
D119 D118 D117 D116 D115 D114 D113 D112 ack D111 D110 D109 D108 D107 D106 D105 D104 ack
3rd data byte
MSB
D103 D102 D101 D100 D99
D86
D85
D70
D69
D54
D53
D38
D37
D22
D81
D68
D52
D36
D21
D20
D67
D66
D6
D5
D4
D50
D35
D3
D80
D65
D64
D49
D48
ack
D33
D32
ack
D17
D16
D93
D92
D79
D63
ack
D47
D78 D77
D76
D31
D62 D61
D60
D15
D89
D75
D74
D59
D58
D46 D45
D44
D43
D42
D73
D28
D27
D26
D57
D12
D11
D10
D72
ack
D56
ack
LSB
D41
D40
ack
LSB
D25
14th data byte
D14 D13
ack
LSB
12th data byte
D30 D29
D88
LSB
10th data byte
MSB
ack
D90
8th data byte
MSB
ack
D91
LSB
6th data byte
MSB
LSB
D18
D94
MSB
LSB
D34
D95
MSB
LSB
D51
D19
ack
LSB
13th data byte
MSB
D7
D82
13th data byte
MSB
D23
D83
11th data byte
MSB
D39
D84
D96
4th data byte
MSB
LSB
9th data byte
MSB
D55
D97
7th data byte
MSB
D71
D98
5th data byte
MSB
D87
LSB
D24
ack
LSB
D9
D8
ack
LSB
D2
D1
D0
ack
P
ack = Acknowledge
S = Start
P = Stop
Bits description
1st data byte
RFPLL
Loop divider
M counter
D119
22/38
D118
D117
D116
D115
D114
D113
D112
I2C-bus interface
STA011
2nd data byte
RF PLL
Loop divider
Loop divider A counter
D111
D110
K (fractional)
D109
D108
D107
D106
D105
D104
Div 2
Enable
Loop div
Enable
CP
Enable
D98
D97
D96
3rd data byte
RF PLL
Reference divider
Division ratio
D103
D102
D101
D100
D99
4th data byte
RFPLL
VCO
Enable
ext LO
Enable
D95
D94
VCO output voltage
setting
D93
Prescaler
Enable
D92
D91
Charge Pump current setting
D90
D89
D88
5th data byte
RF PLL
Phase frequency detector
PFD setting
D87
Table 19.
D86
D85
D84
D83
Down
ASYM
enable
Down Split
enable
DAC
Enable
D82
D81
D80
6th data byte
RFPLL
Down Asym delay
setting
DAC current adjustment
D79
D78
D77
D76
D75
D74
D73
Not used
D72
23/38
I2C-bus interface
STA011
7th data byte
RF path
LNA
enable
RF Mixer
enable
D71
D70
IFpath
RF Gain
Setting
D69
IF Buffer
enable
IF Buffer
Current
setting
Pre VGA
enable
VGA1
enable
D67
D66
D65
D64
VCO
Enable
ext LO
Enable
D57
D56
D68
8th data byte
IF path
IFPLL
VGA2
enable
IF Mixer
enable
IF2 amp
enable
D63
D62
D61
Lock detector setting
D60
D59
D58
9th data byte
IF PLL
CP
enable
PFD setting
D55
D54
D53
D52
D51
D50
Ref div
Division ratio
D49
D48
10th data byte
IF PLL
Loop div
ratio
Reference divider division ratio
D47
D46
D45
D44
D43
D42
D41
D40
D34
D33
D32
11th data byte
IF PLL
Loop divider Division ratio
D39
24/38
D38
D37
D36
D35
I2C-bus interface
STA011
12th data byte
IF PLL
XTAL
Loop divider
division ratio
5.3
M_CLK
output
disable
Double/
single
ended
Cut-off frequency setting
Loop gain
setting
Not used
D31
D30
D29
D28
D27
D26
D25
D24
Not used
Not used
Not used
Not used
Not used
…
…
.
D31
D30
…
…
…
…
….
….
Read mode
Current byte address read
MSB
S
chip address
1
1
0
0
0
R/W
0
A
1
MSB
ack B7
data byte
B6
B5
B4
B3
LSB
B2
B1
B0
P
ack = acknowledge
s = start
p = stop
5.3.1
Bits description
In read mode, only one byte is provided to the master.
PLL’s Lock
Not used
Not used
Not used
Not used
Not used
Not used
Not used
B7
B6
B5
B4
B3
B2
B1
B0
The last six not used bits are fixed to 0.
25/38
Programming specifications
STA011
6
Programming specifications
6.1
RFPLL
6.1.1
Loop divider division ratio
M counter
D119
D118
D117
D116
D115
D114
D113
D112
…
…
…
…
…
…
…
…
0
0
1
0
1
1
1
0
…
…
…
…
…
…
…
…
0
0
1
1
1
0
0
0
…
…
…
…
…
…
…
…
A counter
26/38
Notes
K (fractional)
M=46, startup configuration
Description
D111
D110
D109
D108
D107
D106
D105
D104
1
0
1
1
1
0
0
1
…
…
…
…
…
…
…
…
0
0
0
1
0
1
0
0
…
…
…
…
…
…
…
…
1
1
0
0
0
1
1
1
…
…
…
…
…
…
…
…
1
0
1
1
1
0
0
1
N=M*P+A+K/32 (P=8)
N=368.625, LO1=368.625x3.68=
1356.54 MHz, startup
configuration
STA011
6.1.2
Programming specifications
Reference divider division ratio
Table 20.
6.1.3
Reference divider division ratio
D103
D102
D101
D100
D99
Description
Notes
0
0
0
0
1
R=1
XTAL or TCXO=14.72MHz
fcomp=14. 72MHz,
0
0
0
1
0
R=2
…
…
…
…
…
…
…
R=4
XTAL=14.72MHz
fcomp=3.68MHzKHz,
startup configuration
R=8
fcomp=1.84MHz
R=16
fcomp=.92MHz
Description
Notes
0
0
1
0
0
…
…
…
…
…
0
1
0
0
0
…
…
…
…
…
1
0
0
0
0
Blocks enable
Table 21.
Blocks enable
D98
0
Divider by 2 OFF
1
Divider by 2 ON
0
Loop Divider OFF
1
Loop Divider ON
0
Charge Pump OFF
1
Charge Pump ON
0
Prescaler OFF
1
Prescaler ON
Startup configuration
D97
Startup configuration
D96
Startup configuration
D91
Startup configuration
27/38
Programming specifications
6.1.4
STA011
VCO enable
Table 22.
VCO enable
D95
D94
Description
1
0
Internal RFVCO
1
1
External RFLO
Notes
Startup configuration
The internal RFVCO can also be enabled via hardware mode through the ENRFOSC pin.
With the ENRFOSC pin high the software mode is disabled and the RFVCO is turned ON;
with the ENRFOSC pin low the software mode is enabled, depending on the truth table
described above .
6.1.5
VCO output voltage
Table 23.
6.1.6
VCO output voltage
D93
D92
Description
0
0
Vout=1Vpp
0
1
Vout=2Vpp
1
0
Vout=3Vpp
1
1
Vout=4Vpp
Startup configuration
Charge pump current setting
Table 24.
Charge pump current
D90
D89
D88
0
0
0
ICP=300uA
…
…
…
…….
0
1
1
ICP=400uA
.
1
28/38
Notes
Description
…….
1
1
ICP=600uA
Notes
Startup configuration
STA011
Programming specifications
6.1.7
PFD programming
Table 25.
Frequency phase detector setting
D87
D86
D85
D84
D83
x
x
1
x
1
Normal operation
Default configuration
x
x
1
0
0
Reference divider test, available @Lock
Synthesizer test reserved
configuration
x
x
1
1
0
Loop divider test available @ Lock
Synthesizer test reserved
configuration
0
0
0
x
x
Charge pump test, high impedance state
Synthesizer test reserved
configuration
0
1
0
x
x
Charge pump test, DEC active
Synthesizer test reserved
configuration
1
0
0
x
x
Charge pump test, INC active
Synthesizer test reserved
configuration
1
1
0
x
x
Charge pump test, DEC&INC active
Synthesizer test reserved
configuration
D82
Description
Notes
Down ASYM
0
UP and DOWN sym
1
UP and DOWN asym
0
Down Split disabled
1
Down Split enabled
Startup configuration
D81
6.1.8
Startup configuration
Fractional spurious compensation
Table 26.
Fractional spurious compensation
D80
Description
0
DAC OFF
1
DAC ON
Table 27.
Startup configuration
DAC current adjustment
D79
D78
D77
D76
D75
0
0
1
1
1
Table 28.
Notes
Description
N=7
Notes
startup configuration
Down Asym delay setting
D74
D73
0
0
..
..
1
1
Description
Minimum delay
Notes
Startup configuration
Maximum delay
29/38
Programming specifications
STA011
6.2
RF path
6.2.1
Blocks enable
Table 29.
Blocks enable
Description
Notes
D71
0
LNA OFF
1
LNA ON
0
Mixer OFF
1
Mixer ON
0
Buffer OFF
1
Buffer ON
Startup configuration
D70
Startup configuration
D67
6.2.2
RF gain setting
Table 30.
6.2.3
RF gain setting
D69
D68
1
1
High Gain
1
0
Medium1
0
1
Medium2
0
0
Low Gain
Description
Notes
Startup configuration
IF buffer setting
Table 31.
IF Buffer setting
D66
30/38
Startup configuration
Description
Notes
0
Itail=3mA
lower output linearity
1
Itail=4mA
Higher output linearity, startup configuartion
STA011
Programming specifications
6.3
IF path
6.3.1
Blocks disable
Table 32.
Blocks disable
D65
Description
Notes
D65
0
preVGA OFF
1
preVGA ON
0
VGA1 OFF
1
VGA1 ON
0
VGA2 OFF
1
VGA2 ON
0
Mixer OFF
1
Mixer ON
0
IF2Amp OFF
1
IF2Amp ON
Startup configuration
D64
Startup configuration
D63
Startup configuration
D62
Startup configuration
D61
6.4
Startup configuration
Lock detector setting
Table 33.
Lock detector setting
D60
D59
D58
Description
Notes
0
0
0
Lock test on RF PLL
Test condition
0
0
1
Lock test on IF PLL
Test condition
1
0
0
Lock test on RF PLL and IF PLL
Startup configuration
x
1
0
Test on RF PLL dividers
Test condition
x
1
1
Test on IF PLL dividers
Test condition
31/38
Programming specifications
6.5
IF PLL
6.5.1
IFVCO enable
Table 34.
6.5.2
IFVCO enable
D57
D56
1
0
Internal IFVCO
Startup configuration
1
1
External IFLO
Test condition
Description
Frequency phase detector setting
D55
D54
D53
D52
D51
x
x
1
x
1
Normal operation
Default configuration
x
x
1
0
0
Reference divider test, available
@Lock
Synthesizer test
reserved configuration
x
x
1
1
0
Loop divider test available @ Lock
Synthesizer test
reserved configuration
0
0
0
x
x
Charge pump test, high impedance Synthesizer test
state
reserved configuration
0
1
0
x
x
Charge pump test, DEC active
Synthesizer test
reserved configuration
1
0
0
x
x
Charge pump test, INC active
Synthesizer test
reserved configuration
1
1
0
x
x
Charge pump test, DEC&INC
active
Synthesizer test
reserved configuration
Notes
Charge pump enable
D50
Description
0
Charge Pump OFF
1
Charge Pump ON
Notes
Startup configuration
Reference divider division ratio
Table 37.
D49
0
32/38
Description
Charge pump enable
Table 36.
6.5.4
Notes
PFD programming
Table 35.
6.5.3
STA011
D48
1
Reference divider division ratio
D47
D46
D45
D44
D43
D42
D41
0
0
0
0
0
1
0
Description
R=130
Notes
fcomp=113.23KHz
startup configuration
STA011
Programming specifications
6.5.5
Loop divider division ratio
Table 38.
Loop divider division ratio
D40
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
…
…
…
…
…
…
…
…
…
…
…
0
1
1
1
1
0
1
1
0
1
1
…
…
…
…
…
…
…
…
…
…
…
1
0
0
0
0
0
0
1
0
1
0
…
…
…
…
…
…
…
…
…
…
…
1
0
0
0
0
1
1
1
0
0
1
…
…
…
…
…
…
…
…
…
…
…
6.6
Description
Notes
N=987
N=1034
Startup
configuration
N=1081
XTAL
Table 39.
XTAL
Description
Notes
D29
0
M_CLK output buffer ON
1
M_CLK output buffer OFF
0
M_CLK double ended output
1
M_CLK single ended output
Startup configuration
D28
Startup configuration
Cut-off frequency setting
D27
D26
0
0
Maximum cut-off frequency
0
1
Intermediate 1
1
0
Intermediate 2
1
1
Minimum cut-off frequency
Startup configuration
D25
0
open loop gain set low
1
open loop gain set high
Startup configuration
33/38
Programming specifications
6.7
Startup configuration
Table 40.
34/38
STA011
Startup configuration
Data Byte
Binary
Dec Value
1
00101110
46
2
00010100
20
3
00100111
39
4
10001011
139
5
00101011
43
6
00111000
80
7
11101111
239
8
11110010
242
9
00101101
45
10
00000101
5
11
00000010
2
12
10001010
140
2
2
2
2
2
2
2
2
VREG
Ban2mm
GND1
Ban2mm
GND
Ban2mm
VP4b
Ban2mm
VP4a
Ban2mm
VP3
Ban2mm
VP2b
Ba n2mm
VP2a
1
1
R6
0
1
R4
0
1
1
1
R3 0
1
R5 0
1
R1 0
SW1
0
R32
R33
R30
R29
0
0
0
0
R31
0
R28
C27
C28
C32
-5V
J2
1IF In
Ban2mm
+5V
VP4b
VP4a
RF in
VP3
+5V
Ban2mm
-5V
1uF nc
C31
1uF nc
C17
1uF nc
C14
VP2b
VP2a
VP1
C30
1uF nc
C13
C16
C29
1uF nc
C12
1uF nc
C11
U1
1 1
Vin
4
C1
Gnd
3
100nF C20 Vout
LF30ABDT
10uF
Ban2mm
VP1
Ban2mm
RF Out
J3
1
2
3
1
2
3
4
5
6
ADT4-1WT
100pF
C63
100pF
C64
VP2b
100nF
100nF
VP2a
C7
VP4b
C6
10nF
C46
100pF
C65
VP1
1nF 1uF
C18
C35 tbd
C60
VP3
6
5
4
C34 tbd
Very close to fitting pin
LDB31
6
2
4
Prim Sec
n/ u
ct
Prim2 Sec
U5
ADT1-1WT
Pri m Sec
nu
ct
Prim2 Sec
U3
RF Balun
gnd
bal
unbal
gnd
gnd
bal
U4
VP4a
J4
3
5
1
1
2
AGC ctrl
10nF
TP6
C49
TP7
L1
J8
R2
0
VP1
SIP
SIN
VN1
LNI
NLN1
VN1
Address
PADJ1
PADJ2
ENRFOSC
C3
100nF
C2
100nF
VP1 1
2
3
4
5
6
tbd
7
Addr
8
R13 tbd
9
10
EnRfOsc 11
10nF
C47
10nF
C48
100K
R8
100K
R7
4
5
6
Unbal bal
n/c
n/c
Gnd bal
VP2a
STA011
J9
U9
LDB182G72
Ext RF LO
1
2
3
U2
ADT2-1T-1P
J1
Ext IF LO
2
14.72MHz
tbd
fltRF_Test
1uF C19
27pF C59
C38
tbd
TP1
TP2
J10
Ext Ref
tbd
51ohm
R21
TP4
C8
100nF
TP3
10nF
C54
R10 L2
tbd tbd
C52
tbd
C9
tbd
C44
100nF
R24
1K
100nF
D3
3
1
C10
R27
51
R15
R16
+5V
C5
2
+5V
-5V
U10
1nF 10nF 10uF
AD8009
1nF 10nF 10 uF
C62 C57 C26
LED
D4
51 ohm
R20
U7
AD8130
2
EnRFOsc
VP3
300ohm
R22
Q1
BSN20 gsd
U8
AD8130
C61 C55 C25
-5V
CE
100nF
0 ohm
C23 10uF
C41
CAP
100nF
C22
10uF
C4
0 ohm
nc
0 ohm
C24 10uF
R18
0 ohm
R17
J11
TestDiv
R23
1K
C37
tbd
tbd
C36
C21 10uF
fltIF_Test
R12
J5
C40
10nF
10nF
C51
R14
TP5
10nF 27pF 1uF
C53
10nF
C45
tbd
tbd
C39
C50 C58 C15
tbd
C33
33
32
31
30
29 CE
28 VP3
27 SCL
26 SDA
25
24
23
3
tbd
R9
R11
tb d
18pF
C43
Y1
C42
10nF C56
D2
U6
STA011
RXI
NRXI
GADJ2
GADJ1
CE
VP3
SCL
SDA
VN3
M_Clk1
M_Clk2
1
D1
2
2
1
2
1
1
1
3
3
2
1
Sec Pri m2
ct
n/u
Sec Pri m
6
5
4
44
43
42
41
40
39
38VP4b
37
36
35VP4a
34
VN4
SOP
SON
VN4
AGC2
AGC1
VP4
NTK2
TK 2
VP4
FLT2
VP2
TK 1
NTK1
VP2
FLT1
VN2
XT AL 1
XT AL 2
REF
XOsel
TL ck
12
13
14
VP2b 15
16
17
18
19
20
21
22
3
2
4
3
2
1
nc
VsOut I N +
Vs+ I N nc
nc
XOsel
5
6
7
8
1
3
1
7
6
5
EnRfOsc
InI n+
Vs- Vs+
PD Out
Re f FB
1
3
1
7
6
5
CE
InI n+
Vs- Vs+
PD Out
Re f FB
SCL
SDA
+5V
R251K
2
XOsel
R261K
J7
MClk
51 ohm
R19
2
Add r
A ddr
8
2
3
4
AC00415
1
2
PROG
RX Out
J6
XOsel
8
2
3
4
1
3
7
2
STA011
Evaluation board
Evaluation board
Figure 11. Evaluation board schematic
35/38
Package information
8
STA011
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 12. TQFP44 mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.60
A1
0.05
0.15
0.063
0.002
0.006
A2
1.35
1.40
1.45
0.053
0.055
0.057
B
0.30
0.37
0.45
0.012
0.015
0.018
C
0.09
0.20
0.004
D
11.80
12.00
12.20
0.464
D1
9.80
10.00
10.20
0.386
D3
8.00
0.008
0.472
0.480
0.394
0.401
0.315
E
11.80
12.00
12.20
0.464
0.472
0.480
E1
9.80
10.00
10.20
0.386
0.394
0.401
E3
8.00
0.315
e
0.80
0.031
L
0.45
0.60
L1
0.75
0.018
1.00
k
OUTLINE AND
MECHANICAL DATA
MAX.
0.024
0.030
TQFP44 (10 x 10 x 1.4mm)
0.039
0˚(min.), 3.5˚(typ.), 7˚(max.)
D
D1
A
A2
A1
23
33
34
22
0.10mm
.004
B
E
B
E1
Seating Plane
12
44
11
1
C
L
e
K
TQFP4410
0076922 D
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STA011
9
Revision history
Revision history
Table 41.
Document revision history
Date
Revision
21-Nov-2007
1
Changes
Initial release.
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STA011
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