SM802XXX Flexible Ultra-Low Jitter Clock Synthesizer Clockworks™ FLEX General Description Features The SM802xxx series is a member of the ClockWorks™ family of devices from Micrel and provide an extremely low-noise timing solution for applications such as (1-100) Gigabit Ethernet, SONET, Wireless base station, Satellite communication, Fibre Channel, SAS/SATA and PCI-e. It is based upon a unique PLL architecture that provides less than 250fs phase jitter. • 115fs at 156.25MHz (1.875MHz to 20MHz) • 245fs at 156.25MHz (12kHz to 20MHz) • On chip power supply regulation for excellent board level power supply noise immunity • Generates up to 8 combinations of differential or 16 single-ended clock outputs. − LVPECL, LVDS, HCSL, LVCMOS (SE or Diff) • Selectable input: − Crystal: 11MHz to 30MHz − Reference input: 11MHz to 80MHz • No external crystal oscillator capacitors required • 2.5V or 3.3V operating power supply • Available in Industrial Temperature range • Available in Green, RoHS, and PFOS compliant QFN packages: − 44-pin, 7mm × 7mm − 32-pin, 5mm × 5mm − 24-pin, 4mm × 4mm − 16-pin, 3mm × 3.5mm The devices operate from a 2.5V or 3.3V power supply and synthesize up to 8 different combinations (LVPECL, LVDS, HCSL) of differential or 16 single ended output clocks. The devices accept an external reference clock or crystal input. The SM802xxx series is fully programmable and a web tool is available to configure a part for samples at: http://clockworks.micrel.com/micrel/ Datasheets and support documentation are available on Micrel’s web site at: www.micrel.com. Block Diagram Applications • • • • • • • 1/10/40/100 Gigabit Ethernet – (GbE) SONET/SDH PCI-Express CPRI/OBSAI – Wireless base station Fibre Channel SAS/SATA DIMM Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 6, 2013 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Ordering Information Part Number Marking Shipping Ambient Temperature Range Package SM802xxxUMG 802xxx Tray –40°C to +85°C See Package Options SM802xxxUMGTR 802xxx Tape and Reel –40°C to +85°C See Package Options Package Options Package (1) Option QFN Package # of Outputs Crystal Reference Input XTAL_SEL FSEL OE1 OE2 PLL Bypass #1 44-pin, 7mm × 7mm 8 diff. Yes Yes Yes Yes Yes Yes #2 32-pin, 5mm × 5mm 4 diff. Yes Yes Yes Yes Yes Yes #3 24-pin, 4mm × 4mm 4 diff. Yes Yes Yes No No Yes #4 24-pin, 4mm × 4mm 2 diff. Yes Yes Yes Yes Yes Yes #5 16-pin, 3mm × 3.5mm 2 diff. No Yes No Yes No No #6 16-pin, 3mm × 3.5mm 2 diff. Yes No No No No No Note: 1. Use the web tool at http://clockworks.micrel.com/micrel/ to determine the desired configuration. June 6, 2013 2 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Pin Configurations June 6, 2013 Option #1 44-Pin 7mm x 7mm QFN (QFN-44L) Option #2 32-Pin 5mm x 5mm QFN Option #3 24-Pin 4mm x 4mm QFN Option #4 24-Pin 4mm x 4mm QFN Option #5 16-Pin 3mm x 3.5mm QFN Option #6 16-Pin 3mm x 3.5mm QFN 3 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Pin Description Pin Numbers by Package Option 9 6 XIN 11 10 7 XOUT I, O (SE) 9 8 7 REF_IN I, (SE) LVCMOS Reference Clock input 6 6 FSEL I, (SE) Frequency Select, divides output LVCMOS frequencies by 2. 0 = FREQ, 1 = FREQ/2, 45kΩ pull-up 4 - - XTAL SEL I, (SE) XTAL Select, selects between XTAL and LVCMOS REF_IN 0 = REF_IN, 1 = XTAL, 45kΩ pull-up - PLL BYPASS #3 24-Pin #4 24-Pin 18 13 10 19 14 17 12 14 10 10 6 5 Pin Level Pin Name #2 32-Pin 9 Pin Type #6 16-Pin #1 44-Pin 6 5 3 #5 16-Pin - I, (SE) Pin Function Crystal connections LVCMOS Bypasses the PLL and switches the XTAL or REF_IN frequency to all outputs 0 = PLL mode, 1 = Bypass mode, 45kΩ pull-down Clock Outputs from Bank 1 25 - - 28 21 16 29 22 17 - 35 36 /QA - - - - - - - - - - 25 20 19 14 14 /QD 26 21 20 15 15 QD 41 30 23 22 42 31 24 23 - - - 4 3 3 5 4 4 - 26 32 33 QA /QB QB /QC QC O Various O Various O Various O Various Each output can be programmed to its own logic type: LVPECL, LVDS, HCSL, or (2) LVCMOS Clock Outputs from Bank 2 1 2 7 8 31 37 38 16 43 44 23 27 1 32 /QE Each output can be programmed to its own logic type: LVPECL, LVDS, HCSL, or (2) LVCMOS - - 1 1 /QF 2 2 QF - - - - - - - 18 17 16 16 VDDO1 PWR Power Supply for the outputs on Bank 1. 1 24 16 16 VDDO2 PWR Power Supply for the outputs on Bank 2. QE /QG QG /QH QH O Various O Various O Various O Various Note: 2. In the case of LVCMOS, an output pair can provide two single-ended LVCMOS outputs. June 6, 2013 4 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Pin Numbers by Package Option #3 24-Pin #4 24-Pin #5 16-Pin #6 16-Pin Pin Name Pin Type 22 21 - - VSSO1 PWR Power Supply Ground for the outputs on Bank 1. 2 2 - - VSSO2 PWR Power Supply Ground for the outputs on Bank 2. 7 7 5 4 4 15 12 11 8 8 20 15 16 11 11 24 19 18 13 13 8 1 5 5 3 3 9 9 10 10 12 12 #1 44-Pin #2 32-Pin 24 19 39 28 3 2 6 29 40 11 20 27 30 34 12 8 13 9 21 17 13 23 18 14 13 14 15 Pin Level Pin Function Used for production test. TEST Do not connect anything to these pins. VDD PWR Core Power Supply. VSS PWR Core Power Supply Ground. - - - - - - EXPOSED PAD - The exposed pad must be connected to the VSS ground plane. 15 11 - 7 - - OE1 I, (SE) Output Enable 1, OUT1−8 disables to LVCMOS tri-state, 0 = Disabled, 1 = Enabled, 45kΩ pull-up 22 16 - 12 - - OE2 I, (SE) Output Enable 2, OUT9−16 disables to LVCMOS tri-state, 0 = Disabled, 1 = Enabled, 45kΩ pull-up Truth Table Control Pin (3) Internal Resistor 0 Level (Low) 1 Level (High) OE1 Pull-Up Outputs QA~QD disabled to Hi Z (Tri-State) Outputs QA~QD enabled OE2 Pull-Up Outputs QE~QH disabled to Hi Z (Tri-State) Outputs QE~QH enabled XTAL_SEL Pull-Up External reference clock input is selected Crystal is selected Pull-Up Output = Target Frequency X2 or /2 Output = Target Frequency Pull-Down PLL frequency is connected to outputs PLL is bypassed, Crystal or Ref-in is connected to outputs FSEL (4) PLL_BYPASS Notes: 3. The internal resistor sets the default logic level on the control pin when the pin is left open. Pull up will set default logic 1 and pull down will set default logic 0. When the pin is not available on a specific configuration, the level will be the default logic level. 4. The FSEL pin behavior can be programmed between two types: - At FSEL=0 (low), the output frequency changes to multiply by 2. - At FSEL=0 (low), the output frequency changes to divide by 2. The FSEL function affects all outputs the same way, all outputs change when the FSEL pin level changes. June 6, 2013 5 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Absolute Maximum Ratings(5) Operating Ratings(6) Supply Voltage (VDD, VDDO1/2) ...................................... +4.6V Input Voltage (VIN) ................................ −0.5V to VDD + 0.5V Lead Temperature (soldering, 20s) ............................ 260°C Case Temperature ..................................................... 115°C Storage Temperature (Ts)......................... –65°C to +150°C Supply Voltage (VDD, VDDO1/2) ............... +2.375V to +3.465V Ambient Temperature (TA) .......................... –40°C to +85°C (7) Junction Thermal Resistance QFN (θJA), Still-Air 44-pin ................................................................ 24°C/W 32-pin ................................................................ 34°C/W 24-pin ................................................................ 50°C/W 16-pin ................................................................ 60°C/W DC Electrical Characteristics(8) VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5% VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5% TA = −40°C to +85°C Symbol VDD, VDDO1/2 Parameter Condition Min. Typ. Max. Units 3.3V Operating Voltage VDDO1 = VDDO2 3.135 3.3 3.465 V VDDO1 = VDDO2 2.375 2.5 2.625 V 275 345 mA 150 185 mA 70 90 mA 2.5V Operating Voltage 8 LVPECL, 312.5MHz (44-pin QFN) Outputs open IDD Total supply current, VDD + VDDO 4 HCSL (PCIe), 100MHz (32-pin or 24-pin QFN) Outputs 50Ω to VSS 2 LVCMOS, 125MHz (16-pin QFN) Outputs open LVCMOS Inputs (OE1, OE2, PLL_BYPASS, XTAL_SEL, FSEL) DC Electrical Characteristics(8) VDD = 3.3V ±5% or 2.5V ±5%, TA = −40°C to +85°C Symbol Parameter Condition Min. VIH Input High Voltage VIN Input Low Voltage IIH Input High Current VDD = VIN = 3.465V IIL Input Low Current VDD = 3.465V, VIN = 0V Typ. Max. Units 2 VDD + 0.3 V −0.3 0.8 V 150 µA −150 µA Notes: 5. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6. The datasheet limits are not guaranteed if the device is operated beyond the operating ratings. 7. Package thermal resistance assumes the exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. 8. The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables after thermal equilibrium has been established. June 6, 2013 6 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX LVDS Output DC Electrical Characteristics(8) VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5% VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5% TA = −40°C to +85°C. RL = 100Ω across Q1 and /Q1. Symbol Parameter Condition Min. Typ. Max. Units VOD Differential Output Voltage Figure 6 275 350 475 mV ΔVOD VOD Magnitude Change 40 mV VOS Offset Voltage ΔVOS VOS Magnitude Change 1.15 1.25 1.50 V 50 mV HCSL Output DC Electrical Characteristics(8) VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5% VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5% TA = −40°C to +85°C. RL = 50Ω to VSS Symbol Parameter VOH Condition Min. Typ. Max. Units Output High Voltage 660 700 850 mV VOL Output Low Voltage −150 0 27 mV VSWING Output Voltage Swing 250 350 550 mV Min. Typ. Max. Units LVPECL Output DC Electrical Characteristics(8) VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5% VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5% TA = −40°C to +85°C. RL = 50Ω to VDDO − 2V Symbol Parameter Condition VOH Output High Voltage VDDO – 1.145 VDDO – 0.97 VDDO – 0.845 V VOL Output Low Voltage VDDO – 1.945 VDDO – 1.77 VDDO – 1.645 V VSWING Output Voltage Swing 0.6 0.8 1.0 V Min. Typ. Max. Units LVCMOS Output DC Electrical Characteristics(8) VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5% VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V ±5% TA = −40°C to +85°C. RL = 50Ω to VDDO/2 Symbol Parameter Condition VOH Output High Voltage Figure 7 VOL Output Low Voltage Figure 7 June 6, 2013 VDDO – 0.7 V 0.6 7 V Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX REF_IN DC Electrical Characteristics(8) VDD = 3.3V ±5% or 2.5V ±5%, TA = −40°C to +85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIN Input Current Condition Min. XTAL_SEL = VIL, VIN = 0V to VDD Typ. Max. Units 1.1 VDD + 0.3 V −0.3 0.6 V −5 5 µA XTAL_SEL = VIH, VIN = VDD 20 µA Crystal Characteristics VDD = 3.3V ±5% or 2.5V ±5%, TA = −40°C to +85°C Parameter Condition Min. Mode of Oscillation 10pF load capacitance Typ. Max. Units Fundamental, parallel resonant Frequency 11 Equivalent Series Resistance (ESR) 30 MHz 40 Ω Shunt Capacitance, C0 2 5 pF Correlation Drive Level 10 100 µW LVPECL AC Electrical Characteristics(8, 9, 11, 15) VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output Frequency TR/TF LVPECL Output Rise/Fall Time ODC Output Duty Cycle TSKEW Output-to-Output Skew TLOCK PLL Lock Time Tjit(∅) RMS Phase Jitter @ 156.25MHz Condition Min. Typ. 11 Max. Units 840 MHz 20% – 80% 80 175 350 ps < 350MHz 48 50 52 % ≥ 350MHz 45 50 Note 10 55 % 45 ps 20 ms Integration Range (12kHz to 20MHz) 245 fs Integration Range (1.875MHz to 20MHz) 115 fs Notes: 9. See Figures 4 to 7 for load test circuit examples. 10. Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at the output differential crossing points. 11. All phase noise measurements were taken with an Agilent 5052B phase noise system. June 6, 2013 8 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX LVDS AC Electrical Characteristics(8, 9, 11, 12) VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output Frequency TR/TF LVDS Output Rise/Fall Time ODC Output Duty Cycle TSKEW Output-to-Output Skew TLOCK PLL Lock Time Tjit(∅) RMS Phase Jitter @ 156.25MHz Condition Min. Typ. 11 Max. Units 840 MHz 20% – 80% 100 160 400 ps < 350MHz 48 50 52 % ≥ 350MHz 45 50 55 % 45 ps 20 ms Note 10 Integration Range (1.875MHz to 20MHz) 99 fs HCSL AC Electrical Characteristics(8, 9, 11, 13) VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output Frequency TR/TF Output Rise/Fall Time ODC Output Duty Cycle TSKEW Output-to-Output Skew TLOCK PLL Lock Time Tjit(∅) RMS Phase Jitter @ 100MHz Condition Min. Typ. 11 Max. Units 840 MHz 20% – 80% 150 300 450 ps < 350MHz 48 50 52 % ≥ 350MHz 45 50 55 % 50 ps 20 ms Note 10 Integration Range (12kHz to 20MHz) 254 fs Integration Range (1.875MHz to 20MHz) 115 fs LVCMOS AC Electrical Characteristics(8, 9, 11, 14) VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter FOUT Output Frequency FREF REF_IN Frequency TR/TF Output Rise/Fall Time ODC Output Duty Cycle TSKEW Output-to-Output Skew TLOCK PLL Lock Time Tjit(∅) RMS Phase Jitter @ 125MHz Condition Min. 20% – 80% Max. Units 11 250 MHz 11 80 MHz 100 500 ps 55 % 60 ps 20 ms 45 Typ. 50 Note 10 Integration Range: 1.875MHz to 20MHz 114 fs Notes: 12. Outputs terminated 100Ω between Q and /Q. All unused outputs must be terminated. 13. Output load is 50Ω to VSS. 14. Output load is 50Ω to VDD / 2. 15. Output load is 50Ω to VDD - 2V. June 6, 2013 9 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Phase Noise Plots 100MHz HCSL, 254fs rms for 12kHz to 20MHz integration range 125MHz LVCMOS, 114fs rms for 1.875MHz to 20MHz integration range June 6, 2013 10 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX 156.25MHz LVPECL, 245fs rms for 12kHz to 20MHz integration range 644.53125MHz LVDS, 293fs rms for 12kHz to 20MHz integration range June 6, 2013 11 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Power Supply Filtering Recommendations Preferred filter, using Micrel MIC94300 or MIC94310 Ripple Blocker: Alternative, traditional filter, using a ferrite bead: Application Information Input Reference When operating with a crystal input reference, do not apply a switching signal to REF_IN. The impedance value of the Ferrite Bead (FB) needs to be between 240Ω and 600Ω with a saturation current ≥150mA. The VDDO1 and VDDO2 pins connect directly to the VDD Plane. All VDD pins on the SM802XXX connect to VDD after the power supply filter. Crystal Layout Keep the layers under the crystal as open as possible and do not place switching signals or noisy supplies under the crystal. Crystal load capacitance is built inside the die so no external capacitance is needed. See the Selecting a Quartz Crystal for the Clockworks Flex I Family of Precision Synthesizers application note for more details. Output Traces Design the traces for the output signals according to the output logic requirements. If LVCMOS is unterminated, add a 30Ω resistor in series with the output, as close as possible to the output pin and start a 50Ω trace on the other side of the resistor. If you need help selecting a suitable crystal for your application, contact Micrel’s HBW applications group at: [email protected]. For differential traces you can either use a differential design or two separate 50Ω traces. For EMI reasons it is better to use a differential design. Power Supply Decoupling Place the smallest value decoupling capacitor (4.7nF above) between the VDD and VSS pins, as close as possible to those pins and at the same side of the PCB as the IC. The shorter the physical path from VDD to capacitor and back from capacitor to VSS, the more effective the decoupling. Use one 4.7nF capacitor for each VDD pin on the SM802XXX. June 6, 2013 12 LVDS can be AC-coupled or DC-coupled to its termination. Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Figure 1. Duty Cycle Timing Figure 2. All Outputs Rise/Fall Time Figure 3. RMS Phase/Noise/Jitter Figure 4. LVPECL Output Load and Test Circuit June 6, 2013 Figure 5. HCSL Output Load and Test Circuit 13 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Figure 6. LVDS Output Load and Test Circuit Figure 7. LVCMOS Output Load and Test Circuit Figure 8. Crystal Input Interface June 6, 2013 14 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Package Information and Recommended Land Pattern for 44-Pin QFN(15) NOTE: 1, 2, 3 NOTE: 1, 2, 3 NOTE: 1, 2, 3 3.6±0.02 0.5 BSC 3.6±0.02 0.25±0.02 0.8±0.02 5.6±0.05 7.2±0.05 NOTE: 4, 5 44-Pin QFN Note: 16. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. June 6, 2013 15 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Package Information and Recommended Land Pattern for 32-Pin QFN(15) NOTE: 1, 2, 3 NOTE: 1, 2, 3 NOTE: 1, 2, 3 NOTE: 4, 5 32-Pin QFN June 6, 2013 16 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Package Information and Recommended Land Pattern for 24-Pin QFN(15) NOTE: 1, 2, 3 NOTE: 1, 2, 3 +0.03 −0.00 NOTE: 1, 2, 3 NOTE: 4, 5 24-Pin QFN June 6, 2013 17 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. SM802XXX Package Information and Recommended Land Pattern for 16-Pin QFN(15) NOTE: 1, 2, 3 NOTE: 1, 2, 3 NOTE: 1, 2, 3 NOTE: 4, 5 16-Pin QFN MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2013 Micrel, Incorporated. June 6, 2013 18 Revision 1.0 [email protected] or (408) 955-1690