BM6104FV-C : Power Management

Datasheet
Gate Driver Providing Galvanic isolation Series
Isolation voltage 2500Vrms
1ch Gate Driver Providing Galvanic Isolation
BM6104FV-C
Key Specifications
General Description
The BM6104FV-C is a gate driver with isolation voltage
2500Vrms, I/O delay time of 150ns, and minimum input
pulse width of 90ns, and incorporates the fault signal
output functions, undervoltage lockout (UVLO) function,
and short current protection (SCP, DESAT) function.




Isolation Voltage:
Maximum Gate Drive Voltage:
I/O Delay Time:
Minimum Input Pulse Width:
Package
Features
W(Typ) x D(Typ) x H(Max)
6.50mm x 8.10mm x 2.01mm
SSOP-B20W
 Providing Galvanic Isolation
 Active Miller Clamping
 Fault Signal Output Function
(Adjustable Output Holding Time)
 Undervoltage Lockout Function
 Short Current Protection Function
(Adjustable Reset Time)
 Soft Turn-Off Function For Short Current Protection
(Adjustable Turn-Off Time)
 Supporting Negative VEE2
 Output State Feedback Function
 UL1577 Recognized:File No. E356010
(Note 1)
 AEC-Q100 Qualified
(Note 1:Grade1)
2500Vrms
24V
150ns(Max)
90ns(Max)
Applications
 IGBT Gate Driver
 MOSFET Gate Driver
Typical Application Circuits
GND1
Latch
OSFB
INB
FLTRLS
S
Q
R
ENA
PROOUT
+
INA
-
FB
VEE2
+
OUT1L
-
Timer
FLT
OUT1H
VCC1
VCC2
UVLO
Regulator
UVLO
FLT
LOGIC
INA
VREG
OUT2
ENA
LOGIC
TEST
S
Q
R
GND2
+
VEE2
-
GND1
SCPIN
1pin
Figure 1. For using 4-pin IGBT (for using SCP function)
GND1
INA
Latch
OSFB
INB
FLTRLS
ENA
PROOUT
+
S
Q
R
-
VEE2
FB
+
OUT1L
-
Timer
FLT
OUT1H
VCC1
VCC2
UVLO
UVLO
FLT
Regulator
LOGIC
INA
OUT2
ENA
TEST
GND1
VREG
LOGIC
S
Q
R
GND2
+
-
Figure 2. For using 3-pin IGBT (for using DESAT function)
VEE2
SCPIN
1pin
○Product structure：Silicon integrated circuit ○This product is not designed protection against radioactive rays
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Recommended Range Of External Constants
Pin Name
Recommended Value
Symbol
Min
Typ
Max
Unit
CFLTRLS
-
0.01
0.47
µF
RFLTRLS
50
200
1000
kΩ
VREG
CVREG
1.0
3.3
10.0
µF
VCC1
CVCC1
0.1
1.0
-
µF
VCC2
CVCC2
0.33
-
-
µF
FLTRLS
Pin Configurations
(TOP VIEW)
SCPIN
1
20 GND1
19 TEST
VEE2
2
GND2
3
18 ENA
OUT2
4
17 INA
VREG
5
16 FLT
VCC2
6
15 VCC1
OUT1H
7
14 FLTRLS
OUT1L
8
13 INB
VEE2 9
PROOUT 10
12 OSFB
11 GND1
Pin Descriptions
Pin No.
Pin Name
1
SCPIN
Short current detection pin
Function
2
VEE2
Output-side negative power supply pin
3
GND2
Output-side ground pin
4
OUT2
MOSFET control pin for Miller Clamp
5
VREG
Power supply pin for driving MOSFET for Miller Clamp
6
VCC2
Output-side positive power supply pin
7
OUT1H
Source side output pin
8
OUT1L
Sink side output pin
9
VEE2
10
PROOUT
11
GND1
Input-side ground pin
12
OSFB
Output state feedback output pin
13
INB
14
FLTRLS
15
VCC1
16
FLT
Fault output pin
17
INA
Control input pin A
18
ENA
Input enabling signal input pin
19
TEST
Mode setting pin
20
GND1
Input-side ground pin
Output-side negative power supply pin
Soft turn-off pin
Control input pin B
Fault output holding time setting pin
Input-side power supply pin
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Description of pins and cautions on layout of board
1) VCC1 (Input-side power supply pin)
The VCC1 pin is a power supply pin on the input side. To suppress voltage fluctuations due to the current to drive internal
transformers, connect a bypass capacitor between the VCC1 and the GND1 pins.
2) GND1 (Input-side ground pin)
The GND1 pin is a ground pin on the input side.
3) VCC2 (Output-side positive power supply pin)
The VCC2 pin is a positive power supply pin on the output side. To reduce voltage fluctuations due to OUT1H/L pin
output current and due to the current to drive internal transformers, connect a bypass capacitor between the VCC2 and
the GND2 pins.
4) VEE2 (Output-side negative power supply pin)
The VEE2 pin is a power supply pin on the output side. To suppress voltage fluctuations due to OUT1H/L pin output current
and due to the current to drive internal transformers, connect a bypass capacitor between the VEE2 and the GND2 pins. To
use no negative power supply, connect the VEE2 pin to the GND2 pin.
5) GND2 (Output-side ground pin)
The GND2 pin is a ground pin on the output side. Connect the GND2 pin to the emitter / source of a power device.
6) IN (Control input terminal)
The IN is a pin used to determine output logic.
ENA
INB
H
X
L
H
L
H
L
L
L
L
INA
X
L
H
L
H
OUT1H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
H
OUT1L
L
L
L
L
Hi-Z
7) FLT (Fault output pin)
The FLT pin is an open drain pin used to output a fault signal when a fault occurs (i.e., when the undervoltage lockout
function (UVLO) or short current protection function (SCP) is activated).
Pin
FLT
While in normal operation
Hi-Z
When an Fault occurs
L
(When UVLO or SCP is activated)
8) FLTRLS (Fault output holding time setting pin)
The FLTRLS is a pin used to make setting of time to hold a Fault signal. Connect a capacitor between the FLTRLS pin
and the GND1 pin, and a resistor between it and the VCC1 pin.
The Fault signal is held until the FLTRLS pin voltage exceeds a voltage set with the V FLTRLS parameter. To set holding
time to 0 ms, do not connect the capacitor. Short-circuiting the FLTRLS pin to the VCC1 pin will cause a high current to
flow in the FLTRLS pin and, in an open state, may cause the IC to malfunction. To avoid such trouble, be sure to connect
a resistor between the FLTRLS and the VCC1 pins.
9) OUT1H, OUT1L (Output pin)
The OUT1H pin is a source side pin used to drive the gate of a power device, and the OUT1L pin is a sink side pin
used to drive the gate of a power device.
10) OUT2 (MOSFET control pin for Miller Clamp)
The OUT2 is a pin for controlling the external MOS switch to prevent the increase in gate voltage due to the miller
current of the power device connected to OUT1H/L pin.
11) VREG (Power supply pin for driving the MOSFET for Miller Clamp)
The VREG pin is a power supply pin for Miller Clamp (typ 10V). Be sure to connect a capacitor between VREG pin and
VEE2 pin to prevent oscillation and to reduce voltage fluctuations due to OUT2 pin output current.
12) PROOUT (Soft turn-off pin)
The PROOUT is a pin used to put the soft turn-off function of a power device in operation when the SCP function is
activated. This pin combines with the gate voltage monitoring pin for Miller Clamp function and OSFB function which
output the gate state.
13) SCPIN (Short current detection pin)
The SCPIN is a pin used to detect current for short current protection. When the SCPIN pin voltage exceeds VSCDET
(typ 0.7V), the SCP function will be activated. This may cause the IC to malfunction in an open state. To avoid such
trouble, short-circuit the SCPIN pin to the GND2 pin if the short current protection is not used. In order to prevent the
wrong detection due to noise, the noise mask time tSCPMSK (typ 0.8µs) is set.
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14) OSFB (Output state feedback output pin)
The OSFB pin is an open drain pin used to output the gate state. If the IN and the OUT1H/L pin are at the same level,
the OSFB pin output the “Hi-Z” level, otherwise the OSFB pin output the “L” level and hold “L” until ENA=H or UVLO on
low voltage side is activated.
15) TEST(Mode setting pin)
The TEST pin is an operation mode setting pin. This pin is usually connected to GND1 pin. If the TEST pin is
connected to the VCC1 pin, Input-side UVLO function is disabled.
Description of functions and examples of constant setting
1) Miller Clamp function
When OUT1H/L=Hi-Z/L and PROOUT pin voltage < VOUT2ON (typ 2V), H is output from OUT2 pin and the external MOS
switch is turned ON. When OUT1H/L=H/Hi-Z, L is output from OUT2 pin and the external MOS switch is turned OFF.
While the short-circuit protection function is activated, L is output from OUT2 pin and the external MOS switch is turned
OFF.
Short current
SCPIN
IN
PROOUT
OUT2
Detected
Not less than
VSCDET
X
X
L
X
L
Not less than VOUT2ON
L
X
L
less than VOUT2ON
H
X
H
X
L
Not detected
VCC2
PREDRIV ER
OUT1H/L
PREDRIV ER
PROOUT
PREDRIV ER
LOGIC
VREG
REGULATOR
PREDRIV ER
OUT2
PREDRIV ER
V OUT2ON
+
GND2
VEE2
Figure 3. Block diagram of Miller Clamp function.
tPON
(typ 115ns)
tPOFF
(typ 115ns)
IN
OUT1H/L
PROOUT
(Monitor the gate voltage)
VOUT2ON
tOUT2ON
(typ 25ns)
OUT2
Figure 4. Timing chart of Miller Clamp function
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2) Fault status output
This function is used to output a fault signal from the FLT pin when a fault occurs (i.e., when the undervoltage lockout
function (UVLO) or short current protection function (SCP) is activated) and hold the Fault signal until the set Fault output
holding time is completed. The Fault output holding time t FLTRLS is given as the following equation with the settings of
capacitor CFLTRLS and resistor RFLTRLS connected to the FLTRLS pin. For example, when CFLTRLS is set to 0.01F and
RFLTRLS is set to 200k, the holding time will be set to 2 ms.
tFLTRLS [ms]= CFLTRLS [µF]•RFLTRLS [k]
To set the fault output holding time to “0” ms, only connect the resistor RFLTRLS.
Status
FLT pin
Normal
Hi-Z
Fault occurs
L
Fault occurs (The UVLO or SCP function is activated.)
Status
UVLO
FLT
VFLTRLS
S
SCP
FLTRLS
R
VCC1
CFLTRLS RFLTRLS
Hi-Z
FLT
L
+
FLTRLS
H
OUT1H/L
FLT
L
GND1
Fault output holding time (tFLTRLS)
ECU
Figure 5. Fault Status Output Timing Chart
Figure 6. Fault Output Block Diagram
3) Undervoltage Lockout (UVLO) function
The BM6104FV-C incorporates the undervoltage lockout (UVLO) function both on the low and the high voltage sides.
When the power supply voltage drops to the UVLO ON voltage (low voltage side typ 3.4V, high voltage side typ 9.05V),
the OUT1 and the FLT pin both will output the “L” signal. When the power supply voltage rises to the UVLO OFF voltage
(low voltage side typ 3.5V, high voltage side typ 9.55V), these pins will be reset. However, during the fault output holding
time set in “2) Fault status output” section, the OUT1 pin and the FLT pin will hold the “L” signal. In addition, to prevent
malfunctions due to noises, mask time tUVLO1MSK (typ 10µs) and tUVLO2MSK (typ 10µs) are set on both low and high
voltage sides.
H
L
IN
VUVLO1H
VUVLO1L
VCC1
FLT
OUT1H/L
Figure 7. Low voltage side UVLO Function Operation Timing Chart
Hi-Z
L
H
L
H
L
IN
VUVLO2H
VUVLO2L
VCC2
FLT
OUT1H/L
Figure 8. High voltage side UVLO Operation Timing Chart
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Hi-Z
L
H
Hi-Z
L
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BM6104FV-C
4) Short current protection function (SCP, DESAT)
When the SCPIN pin voltage exceeds VSCDET (typ 0.7V), the SCP function will be activated. When the SCP function is
activated, the OUT1H/L pin voltage will be set to the “Hi-Z/HiZ” level first, and then the PROOUT pin voltage to the “L”
level (soft turn-off).Next, after tSTO (min 30µs, max 110µs) has passed after the short-circuit current falls below the
threshold value, OUT1H/L pin becomes HiZ/L and PROOUT pin becomes L. Finally, when the fault output holding time
set in “2) fault status output” section on page 5 is completed, the SCP function will be released.
VCOLLECTOR/VDRAIN which Desaturation Protection starts operation (VDESAT) and the blanking time (tBLANK) can be
calculated by the formula below;
R3  R 2
 V FD1
R3
R3  R 2  R1
VCC 2 MIN V   VSCDET 
R3
R 2  R1
R3  R 2  R1 VSCDET
t BLANKouternal s   
 R3  (C BLANK  24  10 12 )  ln(1 

)  0.2  10 6
R3  R 2  R1
R3
VCC 2
VDESAT V   VSCDET 
Reference Value
VDESAT
R1
R2
R3
4.0V
15 kΩ
39 kΩ
6.8 kΩ
4.5V
15 kΩ
43 kΩ
6.8 kΩ
5.0V
15 kΩ
36 kΩ
5.1 kΩ
5.5V
15 kΩ
39 kΩ
5.1 kΩ
6.0V
15 kΩ
43 kΩ
5.1 kΩ
6.5V
15 kΩ
62 kΩ
6.8 kΩ
7.0V
15 kΩ
68 kΩ
6.8 kΩ
7.5V
15 kΩ
82 kΩ
7.5 kΩ
8.0V
15 kΩ
91 kΩ
8.2 kΩ
8.5V
15 kΩ
82 kΩ
6.8 kΩ
9.0V
15 kΩ
130 kΩ
10 kΩ
9.5V
15 kΩ
91 kΩ
6.8 kΩ
10.0V
15 kΩ
130 kΩ
9.1 kΩ
VCC2
VCC1
R1
D1
OUT1H/L
LOGIC
S
FLTRLS
+
-
PROOUT
Q
R
R2
FLT
SCPIN
VFLTRLS
SCPMASK
+
-
VSCDET
CBLANK
R3
GND2
GND2
VEE2
Figure 9. Block Diagram for DESAT
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IN
A
OUT1H/L
OUT2
PROOUT
SCPIN
FLT
tSCPMSK+tcomp_delay
VSCPTH (typ 0.95µs)
VSCPTH
t BLANKouternal
tBLANK
BLAN
t BLANKouternal
tBLANK
BLAN
K
tSCPMSK+tcomp_delay
K
Figure 10. DESAT Operation Timing Chart
H
L
INA
VSCDET
SCPIN
H
Hi-Z
L
H
Hi-Z
L
OUT1
OUT2
Hi-Z
L
Hi-Z
L
PROOUT
FLT
tSTO
tSTO
Fault output holding time
(Note 2)
Fault output holding time
(Note 2):
(Note 2)
“2) Fault status output” section on page 5
Figure 11. SCP Operation Timing Chart
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Start
OUT1H/L=Hi-Z/L、OUT2=H
No
VSCPIN>VSCDET
VFLTRLS>VTFLTRLS
No
Yes
Yes
No
Exceed mask time
Yes
FLT=Hi-Z
OUT1H/L=Hi-Z/Hi-Z、OUT2=L、
PROOUT=L、FLT=L
IN=H
No
No
VSCPIN<VSCDET
Yes
OUT1H/L=H/Hi-Z、OUT2=L、
PROOUT=Hi-Z
Yes
No
Exceed tSTO
Yes
Figure 12. SCP Operation Status Transition Diagram
VCC2
VCC1
OUT1H/L
LOGIC
FLTRLS
S
+
-
PROOUT
Q
R
FLT
SCPIN
VFLTRLS
SCPMASK
+
GND2
VSCDET
GND2
VEE2
Figure 13. Block Diagram for SCP
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5）I/O condition table
Input
No
.
Status
1
SCP
2
Output
E
N
A
I
N
B
I
N
A
P
R
O
O
U
T
O
U
T
1
H
O
U
T
1
L
O
U
T
2
P
R
O
O
U
T
F
L
T
O
S
F
B
VCC1
VCC2
S
C
P
I
N
○
○
H
L
L
H
X
Hi-Z
Hi-Z
L
L
L
Hi-Z
UVLO
X
L
X
X
X
H
Hi-Z
L
L
Hi-Z
L
Hi-Z
UVLO
X
L
X
X
X
L
Hi-Z
L
H
Hi-Z
L
Hi-Z
X
UVLO
L
X
X
X
H
Hi-Z
L
L
Hi-Z
L
Hi-Z
X
UVLO
L
X
X
X
L
Hi-Z
L
H
Hi-Z
L
Hi-Z
○
○
L
H
X
X
H
Hi-Z
L
L
Hi-Z
Hi-Z
Hi-Z
○
○
L
H
X
X
L
Hi-Z
L
H
Hi-Z
Hi-Z
Hi-Z
○
○
L
L
H
X
H
Hi-Z
L
L
Hi-Z
Hi-Z
L
○
○
L
L
H
X
L
Hi-Z
L
H
Hi-Z
Hi-Z
Hi-Z
○
○
L
L
L
L
H
Hi-Z
L
L
Hi-Z
Hi-Z
L
○
○
L
L
L
L
L
Hi-Z
L
H
Hi-Z
Hi-Z
Hi-Z
○
○
L
L
L
H
H
H
Hi-Z
L
Hi-Z
Hi-Z
Hi-Z
○
○
L
L
L
H
L
H
Hi-Z
L
Hi-Z
Hi-Z
L
VCC1UVLO
3
4
VCC2UVLO
5
6
Disable
7
8
INB Active
9
10
Normal Operation L Input
11
12
Normal Operation H Input
13
○: VCC1 or VCC2 > UVLO, X:Don't care
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6) Power supply startup / shutoff sequence
H
L
IN
VUVLO1L
VCC1
VCC2
VUVLO2H
VUVLO1L
VUVLO2H
VUVLO1L
VUVLO2H
0V
0V
VEE2
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1H/L
OUT2
PROOUT
FLT
H
L
IN
VCC1
VCC2
VUVLO1L
VUVLO1H
VUVLO2H
VUVLO1H
VUVLO2L
0V
VUVLO2L
VEE2
OUT2
PROOUT
FLT
H
L
IN
VCC1
VUVLO1L
VUVLO2H
VUVLO1L
VUVLO2H
VUVLO1H
0V
VUVLO2L
VEE2
OUT2
PROOUT
FLT
H
L
IN
VCC2
0V
0V
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1H/L
VCC1
0V
0V
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1H/L
VCC2
0V
VUVLO1H
VUVLO1H
VUVLO2L
VUVLO1H
VUVLO2L
0V
VUVLO2L
VEE2
0V
0V
H
Hi-Z
L
H
Hi-Z
L
Hi-Z
L
Hi-Z
L
OUT1H/L
OUT2
PROOUT
FLT
: Since the VCC2 to VEE2 pin voltage is low and the output MOS does not turn ON,
the output pins become Hi-Z conditions.
: Since the VCC1 pin voltage is low and the FLT output MOS does not turn ON, the
output pins become Hi-Z conditions.
Figure 14. Power supply startup / shutoff sequence
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Absolute Maximum Ratings
Parameter
Symbol
Input-Side Supply Voltage
Limits
VCC1
Output-Side Positive Supply Voltage
-0.3～+7.0
VCC2
Output-Side Negative Supply Voltage
VEE2
Maximum Difference
Between Output-Side Positive and Negative Voltages
VMAX2
INA, INB, ENA Pin Input Voltage
VIN
OSFB, FLT Pin Input Voltage
VFLT
FLTRLS Pin Input Voltage
VFLTRLS
SCPIN Pin Input Voltage
VSCPIN
VREG Pin Output Current
IVREG
OUT1H, OUT1L, PROOUT Pin Output Current (Peak 10μs)
-0.3～+30.0
V
-15.0～+0.3
(Note 4)
V
36.0
FLT Output Current
V
(Note 3)
V
(Note 3)
V
(Note 3)
V
-0.3～+VCC1+0.3 or 7.0
-0.3～+VCC1+0.3 or 7.0
-0.3～+VCC1+0.3 or 7.0
-0.3~VCC2+0.3
(Note 4)
10
IOUT2PEAK
OSFB Output Current
V
(Note 4)
IOUT1PEAK
OUT2 Pin Output Current (Peak 10μs)
Unit
(Note 3)
V
mA
5.0
(Note 5)
A
1.0
(Note 5)
A
IOSFB
10
mA
IFLT
10
mA
(Note 6)
W
Power Dissipation
Pd
1.19
Operating Temperature Range
Topr
-40～+125
°C
Storage Temperature Range
Tstg
-55～+150
°C
Junction Temperature
Tjmax
+150
°C
(Note 3) Relative to GND1.
(Note 4) Relative to GND2.
(Note 5) Should not exceed Pd and Tj=150C.
(Note 6) Derate above Ta=25C at a rate of 9.5mW/C. Mounted on a glass epoxy of 70 mm  70 mm  1.6 mm.
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Ratings
Parameter
Input-Side Supply Voltage
Symbol
Min
Max
Units
VCC1
4.5
5.5
V
VCC2
10
24
V
VEE2
-12
0
V
VMAX2
10
32
V
(Note 7)
Output-Side Positive Supply Voltage
(Note 8)
Output-Side Negative Supply Voltage
(Note 8)
Maximum Difference
Between Output-Side Positive and Negative Voltages
(Note 7) Relative to GND1.
(Note 8) Relative to GND2.
Insulation Related Characteristics
Parameter
Insulation Resistance (VIO=500V)
Symbol
Characteristic
9
Units
Ω
RS
>10
Insulation Withstand Voltage / 1min
VISO
2500
Vrms
Insulation Test Voltage / 1sec
VISO
3000
Vrms
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TSZ02201-0717ABH00030-1-2
20.May.2015 Rev.003
BM6104FV-C
Electrical Characteristics
（Unless otherwise specified Ta=-40°C~125°C, VCC1=4.5V~5.5V, VCC2=10V~24V, VEE2=-12V~0V）
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
General
Input Side Circuit Current 1
ICC11
0.38
0.51
0.64
mA
OUT1=L
Input Side Circuit Current 2
ICC12
0.38
0.51
0.64
mA
OUT1=H
Input Side Circuit Current 3
Input Side Circuit Current 4
ICC13
ICC14
0.47
0.54
0.62
0.72
0.77
0.90
mA
mA
INA=10kHz, Duty=50%
INA=20kHz, Duty=50%
Output Side Circuit Current 1
Output Side Circuit Current 2
ICC21
ICC22
1.5
1.3
2.0
1.8
2.5
2.3
mA
mA
VCC2=14V, OUT1=L
VCC2=14V, OUT1=H
Output Side Circuit Current 3
Output Side Circuit Current 4
Output Side Circuit Current 5
Output Side Circuit Current 6
Logic Block
Logic High Level Input Voltage
Logic Low Level Input Voltage
ICC23
ICC24
ICC25
ICC26
1.6
1.3
1.8
1.5
2.2
1.9
2.5
2.1
2.8
2.5
3.2
2.7
mA
mA
mA
mA
VCC2=18V, OUT1=L
VCC2=18V, OUT1=H
VCC2=24V, OUT1=L
VCC2=24V, OUT1=H
VINH
VINL
2.0
0
-
VCC1
0.8
V
V
INA, INB, ENA
INA, INB, ENA
Logic Pull-Down Resistance
Logic Pull-Up Resistance
RIND
RINU
25
25
50
50
100
100
kΩ
kΩ
INA, INB
ENA
Logic Input Mask Time
ENA Mask Time
tINMSK
tENAMSK
4
10
90
20
ns
µs
INA, INB
ENA
Output
OUT1H ON Resistance
RONH
0.7
1.8
4.0
Ω
IOUT1H=40mA
OUT1L ON Resistance
RONL
0.4
0.9
2.0
Ω
OUT1 Maximum Current
IOUTMAX
3.0
4.5
-
A
PROOUT ON Resistance
RONPRO
0.4
0.9
2.0
Ω
IOUT1L=40mA
VCC2=18V
Guaranteed by design
IPROOUT=40mA
tPONA
90
115
150
ns
INA=PWM, INB=L
tPONB
100
125
160
ns
INA=H, INB=PWM
tPOFFA
90
115
150
ns
INA=PWM, INB=L
Turn ON Time
Turn OFF Time
Propagation Distortion
tPOFFB
80
105
140
ns
INA=H, INB=PWM
tPDISTA
tPDISTB
-25
-45
0
-20
20
0
ns
ns
tPOFFA - tPONA
tPOFFB - tPONB
tRISE
tFALL
-
50
50
-
ns
ns
10nF between OUT1-VEE2
RON2H
RON2L
2.0
1.5
4.5
3.5
9.0
7.0
Ω
Ω
IOUT2=10mA
IOUT2=10mA
VOUT2ON
tOUT2ON
1.8
-
2
25
2.2
50
V
ns
Relative to VEE2
VREG
CM
9
100
10
-
11
-
V
kV/µs
Relative to VEE2
Design assurance
Rise Time
Fall Time
OUT2 ON Resistance (Source)
OUT2 ON Resistance (Sink)
OUT2 ON Threshold Voltage
OUT2 Output Delay Time
VREG Output Voltage
Common Mode Transient Immunity
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10nF between OUT1-VEE2
TSZ02201-0717ABH00030-1-2
20.May.2015 Rev.003
BM6104FV-C
Electrical Characteristics
（Unless otherwise specified Ta=-40°C~125°C, V CC1=4.5V~5.5V, VCC2=10V~24V, VEE2=-12V~0V）
Protection functions
VCC1 UVLO OFF Voltage
VUVLO1H
3.35
3.50
3.65
V
VUVLO1L
tUVLO1MSK
3.25
4
3.40
10
3.55
30
V
µs
VCC2 UVLO OFF Voltage
VCC2 UVLO ON Voltage
VUVLO2H
VUVLO2L
8.95
8.45
9.55
9.05
10.15
9.65
V
V
VCC2 UVLO Mask Time
SCPIN Input Voltage
tUVLO2MSK
VSCPIN
4
-
10
0.1
30
0.22
µs
V
SCP Threshold Voltage
SCP Detection Mask Time
VSCDET
tSCPMSK
0.665
0.55
0.700
0.8
0.735
1.05
V
µs
Soft Turn OFF Release Time
OSFB Threshold Voltage H
tSTO
VOSFBH
30
4.5
5.0
110
5.5
µs
V
Respective to GND2
OSFB Threshold Voltage L
OSFB Output Low Voltage
VOSFBL
VOSFBOL
4.0
-
4.5
0.18
5.0
0.40
V
V
Respective to GND2
IOSFB=5mA
OSFB Filter Time
FLT Output Low Voltage
tOSFBON
VFLTL
1.5
-
2.0
0.18
2.6
0.40
µs
V
IFLT=5mA
VTFLTRLS
0.64×VCC1
-0.1
0.64×VCC1
0.64×VCC1
+0.1
V
VCC1 UVLO ON Voltage
VCC1 UVLO Mask Time
FLTRLS Threshold
INA
50%
ISCPIN=1mA
50%
tPON
tPOFF
OUT1H/L
90%
50%
10%
90%
tFALL
tRISE
50%
10%
Figure 15. INA-OUT1 Timing Chart
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BM6104FV-C
Typical Performance Curves
0.64
0.64
Input side circuit current [mA]
Input side circuit current [mA]
Ta=125°C
0.51
Ta=25°C
0.51
Vcc1=5.5V
Vcc1=5.0V
Vcc1=4.5V
Ta=-40°C
0.38
4.50
0.38
4.75
5.00
VCC1 [V]
5.25
-40
5.50
-20
0
20
40 60
Ta [°C]
80
100 120
Figure 17. Input side circuit current vs. Temperature
(OUT1=L)
Figure 16. Input side circuit current vs. VCC1
(OUT1=L)
0.64
0.64
Input side circuit current [mA]
Input side circuit current [mA]
Ta=125°C
0.51
Ta=25°C
0.51
Vcc1=5.5V
Vcc1=5.0V
Vcc1=4.5V
Ta=-40°C
0.38
4.50
0.38
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 18. Input side circuit current vs. VCC1
(OUT1=H)
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TSZ22111・15・001
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-40
-20
0
20
40 60
Ta [°C]
80
100 120
Figure 19. Input side circuit current vs. Temperature
(OUT1=H)
TSZ02201-0717ABH00030-1-2
20.May.2015 Rev.003
0.77
0.77
0.72
0.72
Ta=125°C
Input side circuit current [mA]
Input side circuit current [mA]
BM6104FV-C
0.67
0.62
Ta=25°C
0.57
0.52
Vcc1=5.5V
0.67
0.62
Vcc1=5.0V
0.57
0.52
Vcc1=4.5V
Ta=-40°C
0.47
4.50
0.47
4.75
5.00
VCC1 [V]
5.25
5.50
-40
Figure 20. Input side circuit current vs. VCC1
(INA=10 kHz, Duty=50%)
0
20
40 60
Ta [°C]
80
100 120
Figure 21. Input side circuit current vs. Temperature
(INA=10 kHz, Duty=50%)
0.89
0.89
0.84
Input side circuit current [mA]
0.84
Input side circuit current [mA]
-20
Ta=125°C
0.79
0.74
0.69
Ta=25°C
0.64
Vcc1=5.5V
0.79
0.74
Vcc1=5.0V
0.69
0.64
Vcc1=4.5V
0.59
0.59
Ta=-40°C
0.54
4.50
0.54
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 22. Input side circuit current vs. VCC1
(INA=20 kHz, Duty=50%)
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
-40
-20
0
20
40 60
Ta [°C]
80
100 120
Figure 23. Input side circuit current vs. Temperature
(INA=20 kHz, Duty=50%)
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20.May.2015 Rev.003
BM6104FV-C
3.1
3.1
Output side circuit current [mA]
Output side circuit current [mA]
Ta=125°C
2.9
2.7
2.5
2.3
Ta=25°C
2.1
1.9
Ta=-40°C
1.7
2.7
2.5
2.3
Vcc2=18V
2.1
Vcc2=14V
1.9
1.7
1.5
1.5
14
16
18
20
VCC2 [V]
22
-40
24
Figure 24. Output side circuit current vs. VCC2
(OUT1=L)
-20
0
20
40
60
Ta [°C]
80
100
120
Figure 25. Output side circuit current vs. Temperature
(OUT1=L)
2.7
2.7
Ta=125°C
2.5
Output side circuit current [mA]
2.5
Output side circuit current [mA]
Vcc2=24V
2.9
2.3
2.1
Ta=25°C
1.9
1.7
Ta=-40°C
2.3
2.1
1.9
Vcc2=14V
1.5
1.3
1.3
16
18
20
VCC2 [V]
22
24
Figure 26. Output side circuit current vs. VCC2
(OUT1=H)
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
Vcc2=18V
1.7
1.5
14
Vcc2=24V
-40
-20
0
20
40
60
Ta [°C]
80
100
120
Figure 27. Output side circuit current vs. Temperature
(OUT1=H)
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20.May.2015 Rev.003
BM6104FV-C
24
3.0
20
Ta=-40°C
Ta=25°C
Ta=125°C
2.0
16
OUT1 [V]
VINH / VINL [V]
2.5
H level
1.5
L level
1.0
12
8
Ta=-40°C
Ta=25°C
Ta=125°C
0.5
0.0
4.50
4
0
4.75
5.00
VCC1 [V]
5.25
5.50
0
1
2
3
4
5
INA [V]
Figure 28. Logic (INA/INB/ENA) High/Low level
input voltage vs. VCC1
Figure 29. OUT1 vs. INA input voltage
(VCC1=5V, VCC2=18V, Ta=25°C)
100.0
75.0
75.0
RINU [kΩ ]
RIND [kΩ ]
100.0
Ta=-40°C
50.0
Ta=-40°C
50.0
Ta=25°C
Ta=25°C
Ta=125°C
25.0
4.50
4.75
5.00
VCC1 [V]
Ta=125°C
5.25
5.50
25.0
4.50
Figure 30. Logic pull-down resistance vs. VCC1
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TSZ22111・15・001
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 31. Logic pull-up resistance vs. VCC1
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20.May.2015 Rev.003
BM6104FV-C
90
90
80
80
70
70
Ta=-40°C
Ta=-40°C
60
tINMSK [ns]
tINMSK [ns]
60
50
40
30
Ta=125°C
20
50
40
30
Ta=25°C
Ta=25°C
Ta=125°C
20
10
10
0
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
0
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 33. Logic (INA/INB) input mask time vs. VCC1
(Low pulse)
Figure 32. Logic (INA/INB) input mask time vs. VCC1
(High pulse)
20
3.7
16
3.1
RONH [Ω ]
tENAMSK [µs]
Ta=-40°C
12
2.5
Ta=125°C
1.9
8
Ta=25°C
1.3
Ta=25°C
Ta=125°C
Ta=-40°C
4
4.50
0.7
4.75
5.00
VCC1 [V]
5.25
5.50
16
18
20
VCC2 [V]
22
24
Figure 35. OUT1H ON resistance vs. VCC2
Figure 34. ENA mask time vs. VCC1
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20.May.2015 Rev.003
BM6104FV-C
2.0
2.0
1.6
1.6
RONPRO [Ω ]
RONL [Ω ]
Ta=125°C
Ta=125°C
1.2
Ta=25°C
0.8
1.2
Ta=25°C
0.8
Ta=-40°C
Ta=-40°C
0.4
0.4
14
16
18
20
VCC2 [V]
22
24
14
Figure 36. OUT1L ON resistance vs. VCC2
18
20
VCC2 [V]
22
24
Figure 37. PROOUT ON resistance vs. VCC2
150
150
140
140
130
130
tPON [ns]
Ta=-40°C
tPON [ns]
16
120
110
120
110
Ta=25°C
Ta=125°C
100
100
90
90
14
16
18
20
VCC2 [V]
22
24
Figure 38. Turn ON time vs VCC2
(INA=PWM, INB=L)
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TSZ22111・15・001
-40
-20
0
20
40
60
Ta [°C]
80
100 120
Figure 39. Turn ON time vs Temperature
(VCC2=24V, INA=PWM, INB=L)
19/35
TSZ02201-0717ABH00030-1-2
20.May.2015 Rev.003
150
150
140
140
130
130
Ta=125°C
tPOFF [ns]
tPOFF [ns]
BM6104FV-C
120
110
120
110
Ta=-40°C
Ta=25°C
100
100
90
90
14
16
18
20
VCC2 [V]
22
24
-40
Figure 40. Turn OFF time vs. VCC2
(INA=PWM, INB=L)
100
90
90
20
40
60
Ta [°C]
80
100 120
80
Ta=125°C
70
70
60
60
tFALL [ns]
tRISE [ns]
0
Figure 41. Turn OFF time vs. Temperature
(VCC2=24V, INA=PWM, INB=L)
100
80
-20
50
Ta=125°C
50
40
40
Ta=25°C
30
Ta=25°C
30
Ta=-40°C
Ta=-40°C
20
20
10
10
0
0
14
16
18
20
VCC2 [V]
22
24
16
18
20
VCC2 [V]
22
24
Figure 43. Fall time vs. VCC2
(10nF between OUT1-VEE2)
Figure 42. Rise time vs. VCC2
(10nF between OUT1-VEE2)
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BM6104FV-C
9.0
6.5
Ta=125°C
8.0
Ta=125°C
5.5
RON2L [Ω ]
RON2H [Ω ]
7.0
6.0
Ta=25°C
5.0
Ta=25°C
4.5
3.5
4.0
2.5
3.0
Ta=-40°C
Ta=-40°C
2.0
14
16
1.5
18
20
VCC2 [V]
22
14
24
16
18
20
VCC2 [V]
22
24
Figure 45. OUT2 ON resistance (Sink) vs. VCC2
Figure 44. OUT2 ON resistance (Source) vs. VCC2
2.2
50
Ta=125°C
40
2.1
Ta=25°C
tOUT2ON [ns]
VOUT2ON [V]
Ta=125°C
2.0
30
Ta=25°C
20
Ta=-40°C
Ta=-40°C
1.9
10
1.8
0
14
16
18
20
VCC2 [V]
22
24
16
18
20
VCC2 [V]
22
24
Figure 47. OUT2 output delay time vs. VCC2
Figure 46. OUT2 ON threshold voltage vs. VCC2
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BM6104FV-C
11.0
11.0
Vcc2=24V
Vcc2=18V
Vcc2=14V
10.5
10.5
VREG [V]
VREG [V]
Ta=-40°C
10.0
10.0
Ta=25°C
Ta=125°C
9.5
9.5
9.0
9.0
14
16
18
20
VCC2 [V]
22
-40
24
-20
0
20
40 60
Ta [°C]
80
100 120
Figure 49. VREG output voltage vs. Temperature
Figure 48. VREG output voltage vs. VCC2
5
28
4
Ta=-40°C
tUVLO1MSK [µs]
FLT [V]
3
24
Ta=-40°C
Ta=125°C
2
Ta=125°C
20
16
12
Ta=25°C
Ta=25°C
1
0
3.25
8
4
3.35
3.45
VCC1 [V]
3.55
3.65
-20
0
20
40
60
Ta [°C]
80
100
120
Figure 51. VCC1 UVLO mask time vs. Temperature
Figure 50. FLT vs. VCC1
(VCC1 UVLO ON/OFF voltage)
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BM6104FV-C
6
28
5
24
Ta=125°C
FLT [V]
Ta=125°C
3
Ta=25°C
Ta=25°C
Ta=-40°C
tUVLO2MSK [µs]
4
2
20
16
12
Ta=-40°C
1
8
0
4
8.6
9.1
-40
9.6
-20
0
VCC2 [V]
20
40
60
Ta [°C]
80
100
120
Figure 53. VCC2 UVLO mask time vs. Temperature
Figure 52. FLT vs. VCC2
(VCC2 UVLO ON/OFF voltage, VCC1=5V)
0.22
0.73
Ta=25°C
VSCDET [V]
VSCPIN [V]
Ta=125°C
0.11
Ta=-40°C
Ta=25°C
0.70
Ta=-40°C
Ta=125°C
0.00
0.67
14
16
Figure 54.
18
20
VCC2 [V]
22
24
SCPIN Input voltage vs. VCC2
(ISCPIN=1mA)
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14
16
18
20
VCC2 [V]
22
24
Figure 55. SCP threshold voltage vs. VCC2
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BM6104FV-C
110
1.05
0.95
90
0.85
tSTO [µs]
tSCPMSK [µs]
Ta=-40°C
0.75
Ta=25°C
Vcc2=14V
Vcc2=18V
Vcc2=24V
70
Ta=125°C
Vcc2=14V
Vcc2=18V
Vcc2=24V
Max.
50
0.65
Min.
30
0.55
14
16
18
20
VCC2 [V]
22
-40
24
-20
0
20
40
60
Ta [°C]
80
100 120
Figure 57. Soft turn OFF release time vs. Temperature
Figure 56. SCP detection mask time vs. VCC2
0.4
5.40
Ta=25°C
Ta=125°C
Ta=-40°C
5.20
Ta=125°C
0.3
OSFB_H
VOSFBOL [V]
VOSFB [V]
5.00
4.80
4.60
0.2
Ta=25°C
OSFB_L
4.40
0.1
Ta=125°C
Ta=-40°C
Ta=25°C
4.20
Ta=-40°C
4.00
14
16
18
20
VCC2 [V]
22
24
Figure 58. OSFB threshold voltage H/L vs. VCC2
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0.0
4.50
4.75
5.00
VCC2 [V]
5.25
5.50
Figure 59. OSFB output low voltage vs. VCC2
(IOSFB=5mA)
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0.4
2.50
Ta=125°C
0.3
Ta=125°C
Ta=-40°C
Ta=25°C
VFLTL [V]
tOSFBON [µs]
2.30
2.10
0.2
Ta=25°C
1.90
0.1
1.70
1.50
4.50
Ta=-40°C
4.75
5.00
VCC1 [V]
5.25
5.50
0.0
4.50
4.75
5.00
VCC2 [V]
5.25
5.50
Figure 61. FLT output low voltage vs. VCC2
(IFLT=5mA)
Figure 60. OSFB filter time vs. VCC1
3.62
Ta=-40°C
Ta=25°C
Ta=125°C
VTFLTRLS [V]
3.41
3.20
2.99
2.78
4.50
4.75
5.00
VCC1 [V]
5.25
5.50
Figure 62. FLTRLS threshold vs. VCC1
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Selection of Components Externally Connected
Recommended
ROHM
RSR025N03
RSS065N03
Recommended
ROHM
MCR03EZP
GND1
+
INA
Latch
OSFB
INB
ENA
FLTRLS
PROOUT
-
S
Q
R
FB
VEE2
+
OUT1L
-
Timer
FLT
OUT1H
VCC1
VCC2
UVLO
Regulator
UVLO
FLT
VREG
LOGIC
INA
OUT2
S
Q
R
ENA
LOGIC
TEST
GND2
+
VEE2
-
GND1
SCPIN
1pin
Figure 63. For using 4-pin IGBT (for using SCP function)
Recommended
ROHM
MCR03EZP
Recommended
ROHM
MCR03EZP
GND1
INA
Latch
OSFB
INB
ENA
FLTRLS
-
VEE2
FB
+
OUT1L
-
Timer
FLT
PROOUT
+
S
Q
R
OUT1H
VCC1
VCC2
UVLO
UVLO
FLT
Regulator
VREG
LOGIC
INA
OUT2
S
Q
R
ENA
LOGIC
TEST
GND2
+
VEE2
-
GND1
SCPIN
Figure 64. For using 3-pin IGBT (for using DESAT function)
1pin
Recommended
ROHM
RSR025N03
RSS065N03
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Power Dissipation
Measurement machine：TH156（Kuwano Electric）
Measurement condition：ROHM board
3
Board size：70×70×1.6mm
1-layer board：θja=105.3°C/W
Power Dissipation:Pd [W]
1.5
1.19W
1.0
0.5
0
0
25
50
75
100
125
150
Ambient Temperature: Ta [°C]
Figure 65. SSOP-B20W Derating Curve
Thermal Design
Please confirm that the IC’s chip temperature Tj is not over 150°C, while considering the IC’s power consumption (W),
package power (Pd) and ambient temperature (Ta). When Tj=150°C is exceeded, the functions as a semiconductor do not
operate and some problems (ex. Abnormal operation of various parasitic elements and increasing of leak current) occur.
Constant use under these circumstances leads to deterioration and eventually IC may destruct. Tjmax=150°C must be strictly
followed under all circumstances.
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I/O Equivalence Circuits
Name
Pin No.
I/O equivalence circuits
Function
VCC2
Internal power supply
SCPIN
SCPIN
1
Short current detection pin
GND2
VEE2
VCC2
OUT2
Internalpower
pow er suppl
y
Internal
supply
4
MOSFET control pin for Miller Clamp
VREG
VREG
OUT2
Power supply pin for driving MOSFET
for Miller Clamp
VEE2
5
OUT1H
VCC2
7
Source side output pin
OUT1H
OUT1L
OUT1L
8
VEE2
Sink side output pin
VREG
PROOUT
VCC2
10
PROOUT
Soft turn-off pin
VEE2
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Name
Pin No.
I/O equivalence circuits
Function
OSFB
OSFB
12
GND1
Output state feedback pin
VCC1
FLTRLS
FLTRLS
14
Fault output holding time setting pin
GND1
FLT
FLT
16
Fault output pin
GND1
VCC1
INB
13
Control input pin B
INA、INB
INA
17
GND1
Control input pin A
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Name
Pin No.
I/O equivalence circuits
Function
VCC1
ENA
18
ENA
Input enabling signal input pin
GND1
VCC1
TEST
TEST
19
Test mode setting pin
GND1
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Operational Notes
1.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
terminals.
2.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the power dissipation rating be exceeded, the rise in temperature of the chip may result in
deterioration of the properties of the chip. The absolute maximum rating of the Pd stated in this specification is when
the IC is mounted on a 70mm x 70mm x 1.6mm glass epoxy board. In case of exceeding this absolute maximum rating,
increase the board size and copper area to prevent exceeding the Pd rating.
6.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
7.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
8.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
9.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
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11. Unused Input Terminals
Input terminals of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance
and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input terminals should be connected to
the power supply or ground line.
12. Regarding Input Pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
C
E
Pin A
N
P+
P
N
N
P+
N
Parasitic
Elements
N
P+
N P
N
P+
B
N
C
E
Parasitic
Elements
P Substrate
P Substrate
GND
Parasitic
Elements
Pin B
B
GND
GND
Parasitic
Elements
GND
N Region
close-by
Figure 66. Example of monolithic IC structure
13. Ceramic Capacitor
When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
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Ordering Information
B
M
6
1
0
4
F
V
-
Package
FV:SSOP-B20W
Part Number
CE 2
Rank
C:Automotive
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
SSOP-B20W (TOP VIEW)
Part Number Marking
B M 6 1 0 4
LOT Number
1PIN MARK
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Physical Dimension, Tape and Reel Information
Package Name
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Revision History
Date
Revision
06.Nov.2013
001
23.Jan.2014
002
20.May.2015
003
Changes
New Release
Page 13 : Change Electrical Characteristics ' VCC2 UVLO OFF Voltage '
Page 13 : Change Electrical Characteristics ' VCC2 UVLO ON Voltage '
Page 26 : Change Selection of Components Externally Connected
P.1 Features Adding item (UL1577 Recognized)
P.4 Description of Pins Adding TEST pin
P.7 Description of functions Correcting mistake of Figure 10
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Datasheet
Notice
Precaution on using ROHM Products
1.
If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1),
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2.
ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
© 2015 ROHM Co., Ltd. All rights reserved.
Rev.001