MTS2500 Synthesizer Pinout and Functions This document describes the operating features, software interface information and pin-out of the high performance MTS2500 series of frequency synthesizers, from Synergy Microwave Corporation. The MTS2500® series synthesizers incorporate new advances in frequency synthesis into a small surface-mount package size (1.95” x 1.25”) or connectorized packaging to provide low phase noise and flexibility in step size down to 1 Hz minimum. These synthesizers are truly intelligent incorporating many of the features of the “Intelligent Interactive Synthesizers” (I2S®) product line. An internal controller allows for optimal factory set performance and minimal software development by the user. What is the need for synthesizers having an integrated controller? There are several good reasons to do so! • The operational settings of the PLL chip have to be calculated for each frequency setting to be within the operational specifications. For example in wideband VCOs, the computation of the divider values has to guarantee that no chip internal frequency limits are exceeded. • The settings of the charge pump current and other parameters, which finally define the phase noise and switching speed can be optimized easily with these intelligent features. • Improves the speed of the system processor and makes the software easier to re-use. • Operation can be made independent of the PLL IC used. The use of a controller allows change of the I2S® IC without any impact on the system software. • Integrated error detection and signaling is possible without customer programming. • Reduces design time for the user. A real plug and play solution! Other benefits of the I2S® are: • Intensive internal filtering of the supply voltages. • Monitoring of internal voltages. • Optimized layout to reduce impact of external ground loops. • Standard programming interface for ALL models. • In-circuit firmware upgrade possible for future enhancements. • No hardware programming for a specific PLL IC required. 2 AN7400.000 (Rev. “E”) Software Interface Pins This section describes the software interface pins that are used to address the synthesizers. Some of the pins are not connected (NC) and can be used at a later time for software implementation of additional features. All software I/O interface pins of the MTS2500 are 3.3V CMOS. The input pins are 5V TTL level tolerant with hysteresis and 10ns slew rate control. These inputs also have built-in glitch filtering to ignore pulses shorter than 3ns. • • • • • • • Latch Enable LE for SPI port. (SS) Data In Data to MTS2500. (MOSI) Clock Clock for SPI port. (SCK) Note 1,2 Data Out Data from MTS2500. (MISO) TXD Transmit data. Used for in-circuit programming (field upgrades) only. Note 2 RXD Receive data. Used for in-circuit programming (field upgrades) only. Note 2 RESET A transition “low-high” on this pin re-sets the synthesizer to default frequency. Note 1,2 Note 1: During the “low-high” transition of RESET, a “level-low (0V)” on CLOCK activates in-circuit programming sequence. Keep CLOCK “level-high (3V3)” for regular RESET. Note 2: Contact factory for details Hardware Interface Pins • • • • • • • • 3 Ref in Reference frequency input. Vcc1 (VCO) DC supply voltage for the VCO. This has to be a clean, low noise supply. Decoupling with 10uF close to the MTS2500 is recommended. Vcc2 (Analog) +3.3VDC supply for analog sections of MTS2500. This has to be a clean, low noise supply. Decoupling with 10uF close to MTS2500 is recommended. Vcc3 (Digital) +3.3VDC supply for the digital section of the MTS2500. Decoupling with 10uF close to the MTS2500 is recommended. Vcc4 (Converter) +5VDC supply voltage for the internal voltage converter. Decoupling with 10uF to 100uF/30V close to the MTS2500 is recommended. Vcc5 (Converter) Output of the internal voltage converter. To be connected to Vcc8 (Vtune) externally (No other external loads allowed!) A bypass (shunt) capacitor of 10uF to 100uF/30V is recommended. Vcc6 (PLL) +5VDC supply for PLL. Decoupling with 1uF close to the MTS2500 is recommended. Vcc7 (PLL) +3.3VDC supply for PLL. Decoupling with 1uF close to the MTS2500 is recommended. AN7400.000 (Rev. “E”) • • • • Vcc8 (Vtune) Supply voltage for the VCO tuning. This has to be a clean, low noise supply. Decoupling close to the MTS2500 is recommended. LD Lock Detect, a 3.3V CMOS output, which turns high after the MTS2500 locks. RF out 50Ω output of the Synthesizer. No Connection – leave these pins open (DO NOT CONNECT TO GROUND) Programming The user can address the MTS2500 synthesizers in one of five different options to program the output frequency: 1. Setting an offset frequency from starting frequency of synthesizer. In this mode, an ASCII character code for the letter “C” in hexadecimal (43) indicates to the controller that mode offset frequency is selected. The information for the offset frequency follows in hexadecimal format having 32 bits with LSB sent first (total 40 bits sent). Based on the offset frequency, the controller then calculates the output frequency by the following equation: Fout= FC0 + FOffset, where: Fout- Frequency produced by MTS2500 FC0 - Specified starting frequency of the MTS2500 (Unless otherwise specified FC0 is the lowest frequency produced by MTS2500) FOffset - Frequency offset in Hz For example, an offset frequency of 50Hz would be sent as follows: Data (Hex) 43 32 00 00 00 Maximum frequency that can be set in this mode is 4.29GHz above the starting frequency of the MTS2500 Similarly, the synthesizer can immediately be loaded for standby channel mode by sending ASCII character code for letter “c” in hexadecimal (63) and the data for the next wanted channel number. The programming format for this option is coded as “Little Endian” (MSBit of the LSByte is sent first). 2. Setting a known frequency expressed in Hz. In this mode, an ASCII character code for the letter “D” in hexadecimal (44) indicates to the controller that mode frequency in Hertz is selected. The information for the frequency in Hertz follows in hexadecimal format having 32 bits with LSB sent first (total 40 bits sent). For example, a frequency of 3141592653Hz would be loaded as: Data (Hex) 4 AN7400.000 (Rev. “E”) 44 4D E6 40 BB Maximum frequency that can be set in this mode is ~4.294GHZ Similarly, the synthesizer can immediately be loaded for standby mode by sending ASCII character code for letter “d” in hexadecimal (64) and the data for the next wanted known N. The programming format for this option is coded as “Little Endian” (MSBit of the LSByte is sent first). 3. Setting frequency directly (kHz). In this mode, an ASCII character code for the letter “K” in hexadecimal (4B) indicates to the controller that mode frequency directly (kHz) is selected. The information is loaded in hexadecimal format (1 byte for the “K” command and 8 bytes for the frequency command (72 bits total). No real values allowed, the instruction must be in integer format (KHz). For example, the frequency of 4,000,000 KHz (4 GHz) would be sent as: Data ASCII(Hex) Hex 4B 30 30 33 44 30 39 30 30 or K003D0900 Similarly, the synthesizer can immediately be loaded for standby mode by sending ASCII character code for letter “k” in hexadecimal (6B) and the next wanted frequency (KHz). 4. Setting frequency directly (MHz). In this mode, an ASCII character code for the letter “M” in hexadecimal (4D) indicates to the controller that mode frequency directly (MHz) is selected. The information is loaded in hexadecimal format (1 byte for the “M” command and 8 bytes for the frequency command (72 bits total). No real values allowed, the instruction must be in integer format (MHz). For example, the frequency of 4,000 MHz (4 GHz) would be sent as: Data ASCII(Hex) 4D 30 30 30 30 30 46 41 30 or Hex M00000FA0 Similarly, the synthesizer can immediately be loaded for standby mode by sending ASCII character code for letter “k” in hexadecimal (6D) and the next wanted frequency (MHz). 5. Swap Active/Standby frequencies – When an ASCII character code for the letter “S” in hexadecimal (53) is sent, it indicates to the controller to swap the active and the standby frequency register settings. Data (Hex) 53 Maximum SPI programming speed is recommended not to exceed 200kb/sec in present designs. Design target is 1Mb/sec but not confirmed yet. 5 AN7400.000 (Rev. “E”) By default all MTS2500 are set to a reference frequency of 10 MHz unless otherwise noted in the datasheet. On turn on, the synthesizer defaults to the lowest specified frequency (channel 0). Standby frequency defaults to maximum frequency unless otherwise specified in the datasheet. Systems Design Considerations and Spurious Performance of the MTS2500 The MTS2500 series synthesizers provide a general PLL solution in a wide variety of systems configurations due to its wide frequency range and narrow step size. However in a few cases, the spurious performance may be degraded if the output frequency is slightly offset from a harmonic of the reference frequency. If the offset from the harmonic is less than the loop filter bandwidth, the PLL is unable to sufficiently attenuate the spur. If such output frequencies are required in the system, using a different reference frequency may be more prudent (it is up to the user and their requirements). To handle this situation, the reference frequency can be re-programmed by the user by sending the ASCII “R” command in hexadecimal (52) followed by the reference frequency (in Hz) in hexadecimal having 32 bits with LSB sent first (total 40 bits sent). Currently only reference frequencies from 1 to 250MHz inclusive are supported. For example, a reference frequency of 13MHz would be loaded as: Data (Hex) 52 40 5D C6 00 The programming format for this option is coded as “Little Endian” (MSBit of the LSByte is sent first). The harmonic frequencies where such a reference change may be required are mathematically shown as reference frequency R= ≤ 8Mhz , M where M is smallest possible value that gives an integral result (no fractional part). For example, Ref = 10MHz R = 5MHz Ref = 13MHz R = 6.5MHz Ref = 87MHz R = 7.25MHz Ref = 113MHz R = 7.0625MHz The critical spur regions of the output frequency are then defined as, fout = nR + ∆f where n is integer and 0 < ∆f < PLL loop bandwidth. Table I shows some examples of the different programming options and Figure 2 shows a typical timing diagram for SPI Communication. Table II shows examples of the different programming options for RS232 communication. The synthesizer is programmed to operate with either SPI or RS232 formats. The user must specify the preferred format when ordering these products. 6 AN7400.000 (Rev. “E”) Figure 1: Suggested Connection Diagram 7 AN7400.000 (Rev. “E”) Table I SPI Interface Commands Command Description Command Character C c D d K k M m R S 1 2 3 Byte Position 4 5 6 0x43 0x63 0x44 0x64 0x4B 0x6B 0x4D 0x6D 0x52 0x53 B B B B H H H H B B B B B H H H H B B B B B H H H H B Parameter Unsigned Long Integer, LSByte first Set Active Offset Frequency Set Standby Offset Frequency Set Active frequency in Hz Set Standby frequency in Hz Set Active Frequency in kHz Set Standby Frequency in kHz Set Active Frequency in MHz Set Standby Frequency in MHz Set Reference Frequency in Hz Swap Active / Standby Frequencies Unsigned Long Integer, LSByte first Unsigned Long Integer, LSByte first Unsigned Long Integer, LSByte first Hexadecimal characters Hexadecimal characters Hexadecimal characters Hexadecimal characters Unsigned Long Integer, LSByte first No parameter B B B B H H H H B H H H H 7 8 9 H H H H H H H H H H H H All SPI communication uses most significant bit first. “B” – Binary value with least significant byte first. “H” – ASCII value of a hexadecimal character (uppercase) most significant character first. “C” – ASCII value of option parameter. Examples: “D” Command: “k” Command: “K” Command: “M” Command: Set Active N using a frequency of 3141592653Hz Set Standby N using Frequency of 1100000kHz Set Active N using Frequency of 4000000kHz Set Active N using Frequency of 4000MHz 44 4D E6 40 BB (3141592653 = 0x BB40E64D) 6B 30 30 31 30 43 38 45 30 or “k0010C8E0” 4B 30 30 33 44 30 39 30 30 or “K003D0900” 4D 30 30 30 30 30 46 41 30 or “M00000FA0” Figure 2: Timing Diagram (SPI mode 1) T1 Clock Latch Enable T3 T1: 2.5 us min T2: 5.0 us min T3: 2.5 us min T2 MOSI MISO 8 to 72 bits 8 AN7400.000 (Rev. “D”) Firmware rev 1.0