750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) XIN 26 XOUT 27 SEL3^ 28 SEL2^ 29 OE_CTRL 30 VCON 31 VDD VDD VDD VDD SEL0^ SEL1^ OUTSEL1^ 24 23 22 21 20 19 18 Die ID: A2828-28 1 2 3 4 5 6 7 GND GND GND N/C GND C502A Note: ^ denotes internal pull up Name Value Size 62 x 65 mil Reverse side GND Pad dimensions 80 micron x 80 micron Thickness 10 mil 17 GNDBUF 16 LVCMOS 15 LVDSB 14 LVPECLB 13 VDDBUF 12 VDDBUF 11 LVPECL 10 LVDS 9 OE_SEL^ 8 OUTPUT SELECTION AND ENABLE OUTSEL1 (Pad #18) OUTSEL0 (Pad #25) 0 0 High Drive LVCMOS 0 1 Standard Drive LVCMOS 1 0 LVPECL 1 1 LVDS OE_SELECT (Pad #9) DIE SPECIFICATIONS (1550,1475) GNDBUF X The PLL502-30 is a monolithic low jitter and low phase noise VCXO IC with LVCMOS, LVDS and LVPECL output capabilities, covering the 750kHz to 800MHz output range. It allows the control of the output frequency with an input voltage (VCON), using a low cost 12MHz to 25MHz crystal. This one IC can be used to produce a VCXO with output frequencies ranging from F XIN / 16 to F XIN x 32 thanks to the four frequency selector pads. This makes the PLL502-30 ideal as a universal die for applications ranging from ADSL to SONET. 25 (0,0) Y DESCRIPTION OUTSEL0^ 65 mil GND 750kHz to 800MHz output range. Low phase noise output -127dBc/Hz for 155.52MHz @ 10kHz offset -115dBc/Hz for 622.08MHz @ 10kHz offset Selectable LVCMOS, LVPECL or LVDS output. Selectable High Drive or Standard Drive LVCMOS. 12MHz to 25MHz crystal input. No external load capacitor or varicap required. Output Enable selector. Wide pull range (±200ppm) 3.3V operation. Available in Die form (65 mil x 62 mil). GND DIE CONFIGURATION 62 mil FEATURES 0 1 (Default) Pad #9: Selected Output OE_CTRL (Pad #30) State 0 (Default) Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled Bond to GND to set to “0”, bond to VDD to set to “1” Pad #30: Logical states defined by PECL levels if OE_SELECT is “0” Logical states defined by CMOS levels if OE_SELECT is “1” 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 1 750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) BLOCK DIAGRAM VCON Varicap XIN XOUT Xtal Osc VCO Divider Reference Divider Phase Detector SEL[3:0] Charge Pump + Loop Filter CLKBAR VCO CLK OE FREQUENCY SELECTION TABLE SEL3 (Pad #28) SEL2 (Pad #29) SEL1 (Pad #19) SEL0 (Pad #20) 0 0 0 0 Reserved 0 0 0 1 Reserved 0 0 1 0 Reserved 0 0 1 1 Fin x 32 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 0 Reserved 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication Selected Multiplier All pads have internal pull-ups (default value is 1). Bond to GND to set to 0. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 2 750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature* TA -40 85 C Junction Temperature TJ 125 C 260 C Lead Temperature (soldering, 10s) ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. Crystal Resonator Frequency F XIN Parallel Fundamental Mode 12 Crystal Loading Rating Crystal Pullability Recommended ESR C L (xtal) at VCON = 1.65V TYP. MAX. UNITS 25 MHz 9.5 pF C 0 /C 1 (xtal) AT cut 250 - RE AT cut 30 Ω Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL T VCXOSTB CONDITIONS MIN. From power valid VCXO Tuning Range F XIN = 12MHz to 25MHz; XTAL C 0 /C 1 < 250 0V VCON 3.3V CLK Output Pullability VCON=1.65V, 1.65V MAX. UNITS 10 ms 500 ppm 200 VCXO Tuning Characteristic ppm 150 Pull Range Linearity ppm/V 10 VCON Pin Input Impedance VCON Modulation BW TYP. 0V VCON 3.3V, -3dB % 2000 kΩ 10 kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 3 750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. Supply Current, Dynamic (with loaded outputs, 15pF) I DD LVPECL/ Fout<24MHz LVDS/ 24MHz<Fout<96MHz LVCMOS 96MHz<Fout<700MHz Operating Voltage V DD TYP. @ 50% V DD (LVCMOS) @ 1.25V (LVDS) @ V DD – 1.3V (LVPECL) UNITS 60/28/15 65/45/30 mA 100/80/40 2.97 Output Clock Duty Cycle MAX. 3.63 V 45 50 55 % MIN. TYP. MAX. UNITS 5. Jitter Specifications PARAMETERS Period Jitter, RMS Period Jitter, Peak-to-Peak Integrated Jitter, RMS CONDITIONS FREQUENCY With capacitive decoupling between V DD and GND. Over 10,000 cycles. With capacitive decoupling between V DD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz 155.52MHz 4.3 622.08MHz 5.0 155.52MHz 35 622.08MHz 45 155.52MHz 2.4 622.08MHz 2.5 ps ps ps 6. Phase Noise Specifications PARAMETERS Phase Noise, relative to carrier (typical) FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz 155.52MHz -63 -93 -117 -126 -123 622.08MHz -52 -83 -105 -113 -110 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V 7. LVCMOS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Output Drive Current (Standard Drive) I OH V OH = V DD -0.4V, V DD =3.3V 10 mA I OL V OL = 0.4V, V DD = 3.3V 10 mA Output Drive Current (High Drive) I OH V OH = V DD -0.4V, V DD =3.3V 30 mA I OL V OL = 0.4V, V DD = 3.3V 30 mA Output Clock Rise/Fall Time (Standard Drive) 0.3V ~ 3.0V with 15 pF load 2.4 Output Clock Rise/Fall Time (High Drive) 0.3V ~ 3.0V with 15 pF load 1.2 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 4 750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) 8. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change V OS 0 3 25 mV Power-Off Leakage I OXD 1 10 uA Output Short Circuit Current I OSD -5.7 -8 mA TYP. MAX. UNITS 0.7 1.0 ns 0.7 1.0 ns V out = V DD or GND V DD = 0V V 9. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS Differential Clock Rise Time tr Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) MIN. LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50? VOD VOS VDIFF RL = 100? 50? CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 5 750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) 10. LVPECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) UNITS V V DD – 1.620 V 11. LVPECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - LVPECL 0.6 1.5 ns Clock Fall Time tf @80/20% - LVPECL 0.5 1.5 ns LVPECL Levels Test Circuit OUT LVPECL Output Skew VDD 50 OUT 2.0V 50% 50 OUT tSKEW OUT LVPECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 6 750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) PAD ASSIGNMENT Pad # Name X (m) Y (m) Description 1 GND 248 109 Ground. 2 GND 361 109 Ground. 3 GND 473 109 Ground. 4 GND 587 109 Ground. 5 GND 702 109 Ground. 6 N/C 874 109 No Connection. 7 GND 1042 109 Ground. 8 GNDBUF 1171 109 Ground, buffer circuitry. 9 OE_SELECT 1400 125 Used to select between LVPECL or LVCMOS logic states for OE. Internal pull up. 10 LVDS 1400 259 LVDS Output. 11 LVPECL 1400 476 LVPECL Output. 12 VDDBUF 1400 616 3.3V power supply, Buffer circuitry. 13 VDDBUF 1400 716 3.3V power supply, Buffer circuitry. 14 LVPECLB 1400 871 Complementary LVPECL Output. 15 LVDSB 1400 1089 Complementary LVDS Output. 16 LVCMOS 1400 1227 LVCMOS Output. 17 GNDBUF 1389 1365 Ground, buffer circuitry. 18 OUTSEL1 1232 1365 Used to select LVCMOS, LVPECL or LVDS output type. Internal pull up. 19 SEL1 1042 1365 Used to select multiplication factor. Internal pull up. 20 SEL0 854 1365 Used to select multiplication factor. Internal pull up. 21 VDD 659 1365 3.3V power supply. 22 VDD 559 1365 3.3V power supply. 23 VDD 459 1365 3.3V power supply. 24 VDD 358 1365 3.3V power supply. 25 OUTSEL0 194 1365 Used to select LVCMOS, LVPECL or LVDS output type. Internal pull up. 26 XIN 109 1223 Crystal input. See crystal specification page 3. 27 XOUT 109 1017 Crystal output. See crystal specification page 3. 28 SEL3 109 858 Used to select multiplication factor. Internal pull up. 29 SEL2 109 646 Used to select multiplication factor. Internal pull up. 30 OE_CTRL 109 397 Used to enable/disable the output(s). See Output Selection and Enable table on page 1. 31 VCON 109 181 Voltage Control Input. 0V to 3.3V. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 7 750kHz – 800MHz Low Phase Noise VCXO (for 12 to 25MHz Crystals) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part Number, Package Type and Operating Temperature Range Part Number Temperature C=Commercial (0°C to 70°C) Package Type D=Die W=Wafer Part Number/Order Number Marking Package Option PLL502-30DC P502-30DC Die (Waffle Pack PLL502-30WC P502-30WC Wafer PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/10/08 Page 8