SKY72310-362LF - Skyworks Solutions, Inc.

DATA SHEET
SKY72310: Spur-Free, 2.1 GHz Single Fractional-N Frequency
Synthesizer
Applications
Description
• General purpose RF systems
Skyworks SKY72310 fractional-N frequency synthesizer provides
ultra-fine frequency resolution, fast switching speed, and low
phase-noise performance. This synthesizer is a key building block
for high-performance radio system designs that require low
power and fine step size.
• 2.5G and 3G wireless infrastructure
• Broadband wireless access
• Low bit rate wireless telemetry
• Instrumentation
• L-band receivers
• Satellite communications
Features
• Spur-free operation
• 2.1 GHz maximum operating frequency
• Ultra-fine step size, 100 Hz or less
• High internal reference frequency enables large loop bandwidth
implementations
• Very fast switching speed (e.g., below 100 µs)
• Phase noise to –91 dBc/Hz inside the loop filter bandwidth
@ 1800 MHz
• Software programmable power-down modes
• High-speed serial interface up to 100 Mbps
• Three-wire programming
• Programmable division ratios on reference frequency
• Phase detector with programmable gain to provide a
programmable loop bandwidth
• Frequency power steering further enhances rapid acquisition
time
• On-chip crystal oscillator
• Frequency adjust for temperature compensation
• 3 V operation
• 5 V output to loop filter
• QFN (24-pin, 4 x 4 mm) Pb-free (MSL3, 260 °C per JEDEC JSTD-020) package
The ultra-fine step size of less than 100 Hz allows this synthesizer
to be used in very narrowband wireless applications. With proper
temperature sensing or through control channels, the
synthesizer’s fine step size can compensate for crystal oscillator
or Intermediate Frequency (IF) filter drift. As a result, crystal
oscillators or crystals can replace temperature-compensated or
ovenized crystal oscillators, reducing parts count and associated
component cost. The device’s fine step size can also be used for
Doppler shift corrections.
The SKY72310 has a phase noise floor of –90 dBc/Hz up to
2.1 GHz operation as measured inside the loop bandwidth. This is
permitted by the on-chip low noise dividers and low divide ratios
provided by the device’s high fractionality.
Reference crystals or oscillators up to 50 MHz can be used with
the SKY72310. The crystal frequency is divided down by
independent programmable dividers (1 to 32) for the synthesizer.
The phase detector can operate at a maximum speed of 25 MHz,
which allows better phase noise due to the lower division value.
With a high reference frequency, the loop bandwidths can also be
increased. Larger loop bandwidths improve the settling times and
reduce in-band phase noise. Therefore, typical switching times of
less than 100 µs can be achieved. The lower in-band phase noise
also permits the use of lower cost Voltage Controlled Oscillators
(VCOs) in customer applications.
The SKY72310 has a frequency power steering circuit that helps
the loop filter to steer the VCO when the frequency is too fast or
too slow, further enhancing acquisition time.
The unit operates with a three-wire, high-speed serial interface. A
combination of large bandwidth, fine resolution, and the three
wire interface allows for direct frequency modulation of the VCO.
This supports any continuous phase, constant envelope
modulation scheme such as Frequency Modulation (FM),
Frequency Shift Keying (FSK), Minimum Shift Keying (MSK), or
Gaussian Minimum Shift Keying (GMSK).
Skyworks offers lead (Pb)-free, RoHS (Restriction of
Hazardous Substances) compliant packaging.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
1
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Mod_in
Clock
CS
Data
VCCdigital
The device package and pinout for the 24-pin Quad Flat No-Lead
(QFN) package are shown in Figure 1. Figure 2 shows a functional
block diagram for the SKY72310.
Mux_out
This capability can eliminate the need for In-phase and
Quadrature (I/Q) Digital-to-Analog Converters (DACs), quadrature
upconverters, and IF filters from the transmitter portion of the
radio system.
24
23
22
21
20
19
17
N/C
Fvco_main
3
16
N/C
LD/PS_main
4
15
N/C
VCCcp_main
5
14
N/C
CPout_main
6
13
N/C
7
8
9
10
11
12
GNDXtal
2
VCCxtal
Fvco_main
Xtalout/NC
N/C
Xtalin/OSC
18
Xtalacgnd/OSC
1
N/C
VCCecl/cml
S1258
Figure 1. SKY72310 Pinout, 24-Pin QFN
(Top View)
Registers
Data
Clock
Serial
Interface
MSB/LSB Dividend
Divider
Reference Frequency
Dividers
PD/Charge Pump
& Pwr-Dn/Mux Out
Control
CS
Mod_in
Modulation
Unit
Mux
Mux_out
ΔΣ
18-Bit
Fractional
Unit
Reference
Frequency
Oscillator
Fvco_main
Fvco_main
Main
Divider
Main
Divider
Fpd_main
Main
Phase/Freq.
Detector
and
Charge Pump
Fref_main
Fref
Reference
Frequency
Oscillator
CPout_main
Lock Detection or
Power Steering
LD/PS_main
S1057
Figure 2. SKY72310 Functional Block Diagram
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
2
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Technical Description
The SKY72310 is a fractional-N frequency synthesizer using a ∆Σ
modulation technique. The fractional-N implementation provides
low in-band noise by having a low division ratio and fast
frequency settling time. In addition, the SKY72310 provides
arbitrarily fine frequency resolution with a digital word, so that the
frequency synthesizer can be used to compensate for crystal
frequency drift in the RF transceiver.
Serial Interface
NOTE: The divided crystal oscillator frequency (the internal
reference frequency), Fref_main, is referred to as
“reference frequency” throughout this document.
Phase Detector and Charge Pump
The SKY72310 uses a charge pump phase detector that provides
a programmable gain, Kd, from 31.25 to 1000 µA/2π radians in
32 steps. The phase detector is programmed using the Phase
Detector/Charge Pump Control Register.
The serial interface is a versatile three-wire interface consisting of
three pin signals: Clock (serial clock), Data (serial input), and CS
(chip select). It enables the SKY72310 to operate in a system
where one or multiple masters and slaves are present. To perform
a loopback test at startup and to check the integrity of the board
and processor, the serial data is fed back to the master device
(e.g., a microcontroller or microprocessor unit) through a
programmable multiplexer. This facilitates hardware and software
debugging.
Frequency Steering
∆Σ Modulator
Lock Detection
The SKY72310 provides fractionality through the use of a
proprietary, configurable 10-bit or 18-bit ∆Σ modulator. The
output from the modulator is combined with the divider ratio
through its fractional units.
When programmed for lock detection, the SKY72310 provides an
active low, pulsing open collector output using the LD/PSmain
signal (pin 4) to indicate the out-of-lock condition. When locked,
the LD/PSmain signal is tri-stated (high impedance).
VCO Prescaler
Power Down
The VCO prescaler provides low-noise signal conditioning of the
VCO signal. It translates an off-chip, single-ended or differential
signal to an on-chip differential Current Mode Logic (CML) signal.
The SKY72310 supports a number of power-down modes through
the serial interface. For more information, see the Register
Descriptions section of this document.
VCO Divider
The SKY72310 provides a programmable divider that controls the
CML prescaler and supplies the required signal to the charge
pump phase detector. Programmable divide ratios ranging from
38 to 537 are possible in fractional-N mode and from 32 to 543 in
integer-N mode.
Reference Frequency Oscillator
The SKY72310 has a self-contained, low-noise crystal oscillator.
This crystal oscillator is followed by the clock generation circuitry
that generates the required clock for the programmable reference
frequency divider.
Reference Frequency Divider
The crystal oscillator signal can be divided by a ratio of 1 to 32 to
create the reference frequency for the phase detector. The divide
ratio is programmed using the Reference Frequency Dividers
Register.
When programmed for frequency power steering, the SKY72310
has a circuit that helps the loop filter steer the VCO using the
LD/PSmain signal (pin 4). In this configuration, the LD/PSmain
signal can provide a more rapid acquisition.
When programmed for lock detection, internal frequency steering
is implemented and provides frequency acquisition times
comparable to conventional phase/frequency detectors.
Serial Interface Operation
The serial interface consists of three pins: Clock (pin 22), Data
(pin 20), and CS (pin 21). The Clock signal controls data on the
two serial data lines (Data and CS). The Data pin shifts bits into a
temporary register on the rising edge of Clock. The CS signal
allows individual selection transfers that synchronize and sample
the information of slave devices on the same bus.
Figure 3 functionally depicts how a serial transfer takes place. A
serial transfer is initiated when a microcontroller or
microprocessor forces the CS signal to a low state. This is
followed immediately by an address/data stream sent to the Data
pin that coincides with the rising edges of the clock presented at
the Clock pin.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the registers, 16 bits
of address or data must be presented to the Data line with the
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
3
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
LSB last while the CS signal is low. If the CS signal is low for
more than 16 clock cycles, only the last address or data bits are
used to load the registers.
FVCO
Desired VCO frequency.
Fdiv_ref
Divided reference frequency presented to the phase
detector.
Register Programming
Fractional-N Applications. The desired division ratio for the
synthesizer is given by:
Register programming equations, described in this section, use
the following variables and constants:
Nfractional
Ninteger
Nreg
divider
N fractional =
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (Fref) multiplying factor so that the
resulting frequency is equal to the desired VCO
frequency.
FVCO
Fdiv _ ref
where Nfractional must be between 37.5 and 537.5.
The value to be programmed in the Divider Register is given by:
N reg = Round ( N fractional ) − 32
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (Fref) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for Nreg are from 6 to 505
inclusive.
The value to be programmed by either of the Dividend Registers
(MSB or LSB) is given by:
Nine-bit unsigned input value to the divider ranging
from 0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
dividend = Round [ divider ×( N fractional − N reg − 32 )]
This constant equals 262144 when the ∆Σ modulator
is in 18-bit mode, and 1024 when the ∆Σ modulator is
in 10-bit mode.
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
dividend When in 18-bit mode, this is the 18-bit signed input
value to the ∆Σ modulator, ranging from –131072 to
+131071 and providing 262144 steps, each step equal
to Fdiv_ref/218 Hz.
NOTE: Because of the high fractionality of the SKY72310, there is
no practical need for any integer relationship between the
reference frequency and the channel spacing or desired
VCO frequencies.
When in 10-bit mode, this is the 10-bit signed input
value to the ∆Σ modulator, ranging from –512 to +511
and providing 1024 steps, each step equal to
Fdiv_ref/210 Hz.
Sample calculations for two fractional-N applications are provided
in Figure 4.
Clock
Data
X
A3
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
CS
Last
C1413
Figure 3. Serial Transfer Timing Diagram
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
4
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Case 1: To achieve a desired Fvco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation
of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal
frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore:
Nfractional
=
Fvco_main
Fdiv_ref
= 902.4530
20
= 45.12265
The value to be programmed in the Divider Register is:
Nreg = Round[Nfractional] – 32
= Round[45.12265] – 32
= 45 – 32
= 13 (decimal)
= 000001101 (binary)
With the modulator in 18-bit mode, the value to be programmed in the Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[262144 × (45.12265 – 13 – 32)]
= Round[262144 × (0.12265)]
= Round[32151.9616]
= 32152 (decimal)
= 000111110110011000 (binary)
where 00 0111 1101 is loaded in the Dividend MSB Register and 1001 1000 is loaded in the Dividend LSB Register.
Summary:
·
·
·
·
·
Divider Register = 0 0000 1101
Dividend LSB Register = 1001 1000
Dividend MSB Register = 00 0111 1101
The resulting VCO frequency is 902.453 MHz
Step size is 76.3 Hz
Note: The frequency step size for this case is 20 MHz divided by 218, giving 76.3 Hz.
S1059
Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
5
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Case 2: To achieve a desired Fvco_main frequency of 917.7786 MHz using a crystal frequency of 19.2 MHz with operation
of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal
frequency does not require the internal division to be greater than 1, which makes Fdiv_ref = 19.2 MHz. Therefore:
Nfractional
=
Fvco_main
Fdiv_ref
= 917.7786
19.2
= 47.80097
The value to be programmed in the Divider Register is:
Nreg = Round[Nfractional] – 32
= Round[47.80087] – 32
= 48 – 32
= 16 (decimal)
= 000010000 (binary)
With the modulator in 10-bit mode, the value to be programmed in the Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[1024 × (47.80087 – 16 – 32)]
= Round[1024× (–0.1990312)]
= Round[–203.808]
= 204 (decimal)
= 1100110100 (binary)
where 11 0011 0100 is loaded in the Dividend MSB Register.
Summary:
·
·
·
·
Divider Register = 0 0001 0000
Dividend MSB Register = 11 0011 0100
The resulting VCO frequency is 917.775 MHz
Step size is 18.75 kHz
Note: The frequency step size for this case is 19.2 MHz divided by 210, giving 18.75 kHz.
S1060
Figure 4. Fractional-N Applications: Sample Calculation (2 of 2)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
6
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Integer-N Applications. The desired division ratio for the
synthesizer is given by:
N int eger =
Fvco _ main
Fdiv _ ref
where Ninteger is an integer number from 32 to 543.
The value to be programmed in the Divider Register is given by:
N reg = N int eger − 32
When in integer mode, allowed values for Nreg are from 0 to 511.
NOTE: As with all integer-N synthesizers, the minimum step size
is related to the crystal frequency and reference frequency
division ratio.
Register Loading Order. In applications where the synthesizer is
in 18-bit mode, the Dividend MSB Register holds the 10 MSBs of
the dividend and the Dividend LSB Register holds the 8 LSBs of
the dividend. The registers that control the synthesizer’s divide
ratio are to be loaded in the following order:
• Divider Register
• Dividend LSB Register
• Dividend MSB Register (at which point the new divide ratio
takes effect)
In applications where the synthesizer is in 10-bit mode, the
Dividend MSB Register holds the 10 bits of the dividend. The
registers that control the synthesizer’s divide ratio are to be
loaded in the following order:
• Divider Register
• Dividend MSB Register (at which point the new divide ratio
takes effect)
NOTE: When in integer mode, the new divide ratios take effect as
soon as the Divider Register is loaded.
Direct Digital Modulation
The high fractionality and small step size of the SKY72310 allow
the user to tune to practically any frequency in the VCO’s
operating range. This allows direct digital modulation by
programming the different desired frequencies at precise instants.
Typically, the channel frequency is programmed by the Main
Divider and MSB/LSB Dividend Registers, and the instantaneous
frequency offset from the carrier is programmed by the
Modulation Data Register.
The Modulation Data Register can be accessed in three ways as
defined in the following subsections.
Normal Register Write. A normal 16-bit serial interface write
occurs when the CS signal is 16 clock cycles wide. The
corresponding 16-bit modulation data is simultaneously
presented to the Data pin. The content of the Modulation Data
Register is passed to the modulation unit at the next falling edge
of the divided main VCO frequency (Fpd_main).
Short CS Through Data Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented to the Data pin. The Data
pin is the default pin used to enter modulation data directly in the
Modulation Data Register with shortened CS strobes.
This method of data entry eliminates the register address
overhead on the serial interface. All serial interface bits are resynchronized internally at the reference oscillator frequency. The
content of the Modulation Data Register is passed to the
modulation unit at the next falling edge of the divided main VCO
frequency (Fpd_main).
Short CS Through Mod_in Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented on the Mod_in pin, an
alternate pin used to enter modulation data directly into the
Modulation Data Register with shortened CS strobes. This mode is
selected through the Modulation Control Register.
This method of data entry also eliminates the register address
overhead on the serial interface and allows a different device than
the one controlling the channel selection to enter the modulation
data (e.g., a microcontroller for channel selection and a digital
signal processor for modulation data).
All serial interface bits are internally re-synchronized at the
reference oscillator frequency and the content of the Modulation
Data Register is passed to the modulation unit at the next falling
edge of the divided main VCO frequency (Fpd_main).
Modulation data samples in the Modulation Data Register can be
from 2 to 12 bits long, and enable the user to select how many
distinct frequency steps are to be used for the desired modulation
scheme.
The user can also control the frequency deviation through the
modulation data magnitude offset in the Modulation Control
Register. This allows shifting of the modulation data to
accomplish a 2m multiplication of frequency deviation.
NOTE: The programmable range of –0.5 to +0.5 of the main
∆Σ modulator can be exceeded up to the condition where
the sum of the dividend and the modulation data conform
to:
−0.5625 ≤ ( N mod + dividend ) ≤ + 0.5625
When the sum of the dividend and modulation data lie outside this
range, the value of Ninteger must be changed.
For a more detailed description of direct digital modulation
functionality, refer to the Skyworks Application Note, Direct Digital
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
7
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Modulation Using the SKY72300, SKY72301, and SKY72302 Dual
Synthesizers/PLLs (document number 101349).
to the main integer selected through the Divider Register. As
shown in Figures 6 and 7, values to be loaded are:
Register Descriptions
• Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs of
the 18-bit dividend for the synthesizer.
Table 1 lists the eight 16-bit registers that are used to program
the SKY72310. All register writes are programmed address first,
followed directly with data. MSBs are entered first. On power up,
all registers are reset to 0x000 except the Divider Register at
address 0x0, which is set to 0x006.
• Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs of
the 18-bit dividend for the synthesizer.
The Dividend Register MSB and LSB values are 2's complement
format.
NOTE: When in 10-bit mode, the Dividend LSB Register is not
required.
Synthesizer Registers
The Divider Register contains the integer portion closest to the
desired fractional-N (or the integer-N) value minus 32. This
register, in conjunction with the Dividend Registers (which control
the fraction offset from –0.5 to +0.5), allows selection of a
precise frequency. As shown in Figure 5, the value to be loaded
is:
• Synthesizer Divider Index = Nine-bit value for the integer
portion of the synthesizer divider. Valid values for this register
are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
The Dividend MSB and LSB Registers control the fraction part of
the desired fractional-N value and allow an offset of –0.5 to +0.5
The reference frequency divider provides the reference frequency
to the phase detector by dividing the crystal oscillator frequency.
Divide ratios from 1 to 32 are possible for the reference frequency
divider (see Table 2).
The Reference Frequency Dividers Register configures the
reference frequency divider for the synthesizer. As shown in
Figure 8, the values to be loaded are:
• Reference Frequency Divider Index = Desired oscillator
frequency division ratio –1. Default value on power up is 0,
signifying that the reference frequency is not divided for the
phase detector.
Table 1. SKY72310 Register Map
Address (Hex)
Register (Note 1)
Length (Bits)
Address (Bits)
0
Divider Register
12
4
1
Dividend MSB Register
12
4
2
Dividend LSB Register
12
4
3
Unused
4
Unused
5
Reference Frequency Dividers Register
12
4
6
Phase Detector/Charge Pump Control Register
12
4
7
Power Down/Multiplexer Output Select Control Register
12
4
8
Modulation Control Register
12
4
9
Modulation Data Register
12
4
—
Modulation Data Register (Note 2) — direct input
2 ≤ length ≤ 12 bits
0
Note 1: All registers are write only.
Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
8
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
A3
A2
A1
A0
11
10
9
8
0
0
0
0
X
X
X
MSB
7
6
5
4
3
2
1
0
LSB
Synthesizer Divider Index
S1061
Figure 5. Divider Register (Write Only)
A3
A2
A1
A0
11
10
9
0
0
0
1
X
X
MSB
8
7
6
5
4
3
2
1
0
LSB
Synthesizer Dividend (MSBs)
S1062
Figure 6. Dividend MSB Register (Write Only)
A3
A2
A1
A0
11
10
9
8
7
0
0
1
0
X
X
X
X
MSB
6
5
4
3
2
1
0
LSB
Synthesizer Dividend (LSBs)
S1063
Figure 7. Dividend LSB Register (Write Only)
Table 2. Programming the Reference Frequency Divider
Decimal
Bit 4 (MSB)
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Reference Divider
Ratio
0
0
0
0
0
0
1
1
0
0
0
0
1
2
2
0
0
0
1
0
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31
1
1
1
1
1
32
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
9
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
A3
A2
A1
A0
11
10
0
1
0
1
X
X
9
8
7
6
5
4
3
2
1
0
Reference Frequency Divider Index
S1064
Figure 8. Reference Frequency Dividers Register (Write Only)
A3
A2
A1
A0
0
1
1
0
11
10
9
8
7
6
5
4
3
2
1
0
Phase Detector Gain
Power Steering/Lock Detect Enable
S1065
Figure 9. Phase Detector/Charge Pump Control Register (Write Only)
A3
A2
A1
A0
11
10
0
1
1
1
X
X
9
8
MSB
7
6
5
4
3
2
1
0
LSB
Full Power Down
Synthesizer Power Down
Synthesizer Mode
Synthesizer ΔΣ Fractionality
Multiplexer Output Selection
Mux_out Pin Three-State Enable
S1066
Figure 10. Power Down/Multiplexer Output Select Control Register (Write Only)
The Phase Detector/Charge Pump Control Register allows control
of the gain for the phase detector and configuration of the
LD/PSmain signal (pin 4) for frequency power steering or lock
detection. As shown in Figure 9, the values to be loaded are:
The Power Down/Multiplexer Output Select Control Register
allows control of the power-down modes, internal multiplexer
output, and ∆Σ synthesizer fractionality. As shown in Figure 10,
the values to be loaded are:
• Phase Detector Gain = Five-bit value for programmable phase
detector gain. Range is from 0 to 31 decimal for 31.25 to 1000
µA/ 2π radian, respectively.
• Full Power Down = One-bit flag to power down the SKY72310
except for the reference oscillator and the serial interface. When
this bit is cleared, the SKY72310 is powered up. When this bit is
set, the SKY72310 is in full power-down mode excluding the
Mux_out signal (pin 24).
• Power Steering Enable = One-bit flag to enable the frequency
power steering circuitry of the phase detector. When this bit is
cleared, the LD/PSmain pin is configured to be a lock detect,
active low, open collector pin. When this bit is set, the
LD/PSmain pin is configured to be a frequency power steering
pin and can be used to bypass the external loop filter to provide
faster frequency acquisition.
• Synthesizer Power Down = One-bit flag to power down the
synthesizer. When this bit is cleared, the synthesizer is powered
up. When this bit is set, the synthesizer is in power-down mode.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
10
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Table 3. Multiplexer Output
Multiplexer Output Select
(Bit 8)
Multiplexer Output Select
(Bit 7)
Multiplexer Output Select
(Bit 6)
Multiplexer Output
(Mux_out, Pin 24)
0
0
0
Reference Oscillator
0
0
1
Unused
0
1
0
Reference Frequency (Fref_main)
0
1
1
Unused
1
0
0
Phase Detector Frequency (Fpd_main)
1
0
1
Serial data out
1
1
0
Serial interface test output
1
1
1
Unused
A3
A2
A1
A0
11
10
1
0
0
0
X
X
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Reserved Bits
Modulation Data Magnitude Offset
Modulation Data Input Select
Modulation Address Disable
C1425
Figure 11. Modulation Control Register (Write Only)
• Synthesizer Mode = One-bit flag to power down the ∆Σ
modulator and fractional unit. When this bit is cleared, the
synthesizer is in fractional-N mode. When this bit is set, the
synthesizer is in integer-N mode.
• Synthesizer ∆Σ Fractionality = One-bit flag to configure the size
of the ∆Σ modulator. This has a direct effect on power
consumption, and on the level of fractionality and step size.
When this bit is cleared, the ∆Σ modulator is 18-bit with a
fractionality of 218 and a step size of Fref_main/262144. When this
bit is set, the ∆Σ modulator is 10-bit with a fractionality of 210
and a step size of Fref_main/1024.
NOTE: There are no special power-up sequences required for the
SKY72310.
• Multiplexer Output Selection = Three-bit value that selects
which internal signal is output to the Mux_out pin. The following
internal signals are available on this pin:
− Reference oscillator: Fref
− Divided reference (post-reference frequency divider): Fref_main
− Phase detector frequency (post-frequency divider): Fpd_main
− Serial data out for loop-back and test purposes
Refer to Table 3 for more information.
• Mux_out Pin Tri-State Enable = One-bit flag to tri-state the
Mux_out pin. When this bit is cleared, the Mux_out pin is
enabled. When this bit is set, the Mux_out pin is tri-stated.
The Modulation Control Register is used to configure the
modulation unit of the main synthesizer. The modulation unit adds
or subtracts a frequency offset to the selected center frequency at
which the main synthesizer operates. The size of the modulation
data sample, controlled by the duration of the CS signal, can be
from 2 to 12 bits wide to provide from 4 to 4096 selectable
frequency offset steps.
The modulation data magnitude offset selects the magnitude
multiplier for the modulation data and can be from 0 to 8. As
shown in Figure 11, the values to be loaded are:
• Modulation Data Magnitude Offset = Four-bit value that
indicates the magnitude multiplier (m) for the modulation data
samples. Valid values range from 0 to 13, effectively providing a
2m multiplication of the modulation data sample.
• Modulation Data Input Select = One-bit flag to indicate the pin
on which modulation data samples are serially input when the
CS signal is between 2 and 12 bits long. When this bit is
cleared, modulation data samples are to be presented on the
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
11
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
The SKY72310 is rated to Moisture Sensitivity Level 3 (MSL3) at
260 °C. It can be used for lead or lead-free soldering.
Data pin. When this bit is set, modulation data samples are to
be presented on the Mod_in pin.
• Modulation Address Disable = One-bit flag to indicate the
presence of the address as modulation data samples are
presented on either the Mod_in or Data pins. When this bit is
cleared, the address is presented with the modulation data
samples (i.e., all transfers are 16 bits long). When this bit is set,
no address is presented with the modulation data samples (i.e.,
all transfers are 2 to 12 bits long).
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format. For packaging details, refer to the Skyworks
Application Note, Tape and Reel, document number 101568.
Electrical and Mechanical Specifications
The Modulation Data Register is used to load the modulation data
samples to the modulation unit. These values are transferred to
the modulation unit on the falling edge of Fpd_main where they are
passed to the main ∆Σ modulator at the selected magnitude
offset on the next falling edge of Fpd_main. Modulation Data Register
values are 2's complement format. As shown in Figure 12, the
value to be loaded is:
Signal pin assignments and functional pin descriptions are
described in Table 4. The absolute maximum ratings of the
SKY72310 are provided in Table 5. The recommended operating
conditions are specified in Table 6 and electrical specifications
are provided in Table 7.
• Modulation Data Bits = Modulation data samples that represent
the instantaneous frequency offset to the selected main
synthesizer frequency (selected channel) before being affected
by the modulation data magnitude offset.
Figure 13 provides a schematic diagram for the SKY72310 using
Skyworks SKY73120 890-960 MHz VCO. Figure 14 provides a
schematic diagram for the SKY72310 using a non-Skyworks VCO.
Figure 15 shows the package dimensions for the 24-pin QFN and
Figure 16 provides the tape and reel dimensions.
Package and Handling Information
Electrostatic Discharge (ESD) Sensitivity
Since the device package is sensitive to moisture absorption, it is
baked and vacuum packed before shipping. Instructions on the
shipping container label regarding exposure to moisture after the
container seal is broken must be followed. Otherwise, problems
related to moisture absorption may occur when the part is
subjected to high temperature during solder assembly.
The SKY72310 is a static-sensitive electronic device. Do not
operate or store near strong electrostatic fields. Take proper ESD
precautions.
A3
A2
A1
A0
11
1
0
0
1
MSB
10
9
8
7
6
5
4
3
2
1
0
LSB
Modulation Data Bits
C1426
Figure 12. Modulation Data Register (Write Only)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
12
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Table 4. SKY72310 Signal Descriptions
Pin #
1
Pin Name
VCCecl/cml
Type
Power and ground
Description
ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump.
2
Fvco_main
Input
Main VCO differential input.
3
Fvco_main
Input
Main VCO complimentary differential input.
4
LD/PS_main
Analog output
Programmable output pin. Indicates phase detector out-of-lock as an active low pulsing open collector
output (high impedance when lock is detected), or helps the loop filter steer the VCO. This pin is
configured using the Phase Detector/Charge Pump Control Register.
5
VCCcp_main
(Note 1)
Power and ground
Charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain and
charge pump.
6
CPout_main
Analog output
Charge pump output. The gain of the charge pump phase detector is controlled by the Phase
Detector/Charge Pump Control Register.
7
N/C
–
No connection
8
Xtalacgnd/OSC
Ground/input
Reference crystal AC ground or external oscillator differential input.
9
Xtalin/OSC
Input
Reference crystal input or external oscillator differential input.
10
Xtalout/NC
Input
Reference crystal output or no connect.
11
VCCxtal
Power and ground
Crystal oscillator ECL/CML, 3 V.
12
GNDxtal
Power and ground
Crystal oscillator ground.
13
N/C
–
No connection
14
N/C
–
No connection
15
N/C
–
No connection
16
N/C
–
No connection
17
N/C
–
No connection
18
N/C
19
VCCdigital (Note 1)
Power and ground
–
Digital supply, 3 V.
No connection
20
Data
Digital input
Serial address and data input pin. Address bits are followed by data bits.
21
CS
Digital input
Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock.
When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges
are ignored.
22
Clock
Digital input
Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the
Data pin on the rising edge of Clock.
23
Mod_in
Digital input
Alternate serial modulation data input pin. Address bits are followed by data bits.
24
Mux_out
Digital output
Internal multiplexer output. Selects from oscillator frequency, reference frequency, divided VCO
frequency, serial data out, or testability signals. This pin can be tri-stated from the synthesizer registers.
Note 1: Associated pairs of power and ground pins must be decoupled using 0.1 µF capacitors.
Table 5. Absolute Maximum Ratings
Parameter
Min
Max
Units
3.6
VDC
Maximum digital supply voltage
3.6
VDC
Maximum charge pump supply voltage
5.25
VDC
Maximum analog RF supply voltage
Storage temperature
–65
+150
°C
Operating temperature
–40
+85
°C
Note:
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal values.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
13
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Table 6. Recommended Operating Conditions
Parameter
Min
Max
Units
2.7
3.3
VDC
Analog RF supplies
Digital supply
2.7
3.3
VDC
Charge pump supplies
2.7
5.0
VDC
Operating temperature (TA)
–40
+85
°C
Table 7. Electrical Characteristics (1 of 2)
(VDD = 3 V, TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Power Consumption
Total power consumption
PTOTAL
Power-down current
ICC-PWDN
Charge pump current of
200 µA, synthesizer
fractional,
FREF_MAIN = 20 MHz
37.5
mW
10 (Note 1)
µA
Reference Oscillator
Reference oscillator frequency
FOSC
50
Oscillator sensitivity (as a buffer)
VOSC
AC coupled, single-ended
Frequency shift versus supply voltage
FSHIFT_SUPPLY
2.7 V ≤ VXTAL ≤ 3.3 V
Synthesizer operating frequency
FVCO_MAIN
Sinusoidal, –40 °C to
+85 °C
RF input sensitivity
VVCO
AC coupled
RF input impedance
ZVCO_IN
Fractional-N tuning step size
∆FSTEP_MAIN
0.1
MHz
2.0
Vpp
±0.3
ppm
100 (Note 2)
2100
MHz
50
250
mVpeak
VCO
94 – j140
@ 1200 MHz
Ω
FREF_MAIN/218 or FREF_MAIN/210
Hz
–128
+ 20 Log (N)
dBc/Hz
Noise
Phase noise floor
Pnf
Measured inside the loop
bandwidth using 25 MHz
reference frequency,
–40 °C to +85 °C
Phase detector frequency
FREF_MAIN
–40 °C to +85 °C
25
MHz
Charge pump output source current
ICP-SOURCE
VCP = 0.5 VCCCP
125
1000
µA
Charge pump output sink current
ICP-SINK
VCP = 0.5 VCCCP
–125
–1000
µA
VCCCP – 400
mV
Phase Detector and Charge Pump
Charge pump accuracy
ICP-ACCURACY
Charge pump output voltage linearity range
ICP vs VCP
0.5 V ≤ VCP ≤ (VCCCP
– 0.5 V)
±20
Charge pump current versus temperature
ICP vs T
VCP = 0.5 VCCCP
–40 °C < T < +85 °C
5
%
Charge pump current versus voltage
ICP vs VCP
0.5 V ≤ VCP ≤ (VCCCP
– 0.5 V)
8
%
GND + 400
%
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
14
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Table 7. Electrical Characteristics (2 of 2)
(VDD = 3 V, TA = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Digital Pins
High level input voltage
VIH
0.7 VDIGITAL
Low level input voltage
VIL
High level output voltage
VOH
IOH = –2 mA
Low level output voltage
VOL
IOL = +2 mA
V
0.3 VDIGITAL
V
GND + 0.2
V
100
MHz
VDIGITAL –0.2
V
Timing – Serial Interface
Clock frequency
fCLOCK
Data and CS set up time to Clock rising
tSU
3
ns
Data and CS hold time after Clock rising
tHOLD
0
ns
Note 1: A 5 V charge pump power supply on pin 5 results in higher power-down leakage current.
Note 2: The minimum synthesizer frequency is 12 x FOSC, where FOSC is the frequency at the Xtalin/OSC pin.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
15
A
6
5
4
3
GND
GND
GND
GND
GND
GND
7
8
A
RF_OUT
GND
9
24
23
10
11
12
SKY73120
GND
GND
2
GND
VTUNE
1
GND
GND
25
GND
GND
27 26
22
21
A
13
J3
14
GND
GND
28
GND
GND
C30
39 pF
GND
GND
BS0
BS1
N/C
N/C
N/C
VDD
A
JP4
1
2
×
×
×
A
A
A
C79
100 μF/16 V
VCCCPM
15
16
17
18
19
20
R39
0Ω
JP1
1
2
A
A
2
1
2
1
C49
10 nF
R70
0Ω
R69
0Ω
LOCKM_DET
A
Figure 13. SKY72310 Application Schematic (With SKY73120 VCO)
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
L12
BLM21A601S
C72
0.1 μF
L11
BLM21A601S
C61
22 pF
C50
22 pF
C48
10 pF
A
A
A
R68
0Ω
+ C71
10 μF
R71
0Ω
C66
0.1 μF
A
JP8
JP6
A
A
A
+ C65
10 μF
VCCPM_3V
R46
0Ω
C78
100 μF/16V
Tantalum 7343
TAJAE107K016
C70
0.1 μF
A
+ C68
10 μF
L10
VCCMecl/cml_3V
BLM21A601S
L8
BLM21A601S
A
L13
10 nH
A
R56
0Ω
VCCMecl/cml_3V
J1
N/A
Power Supply
L7
BLM21A601S
R42
10 kΩ
R21
0Ω
+ C75
10 μF/16V
R41
10 kΩ
C76
22 μF/10V
C77
22 μF/10V
A
VCOM_OUT
C5
68 pF
A
A
A
C45
DNI
A
C60
0.1 μF
L3
BLM21A601S
C64
0.1 μF
L6
BLM21A601S
R47
0Ω
R36
330 Ω
A
R58
0Ω
C46
1000 pF
C47
330 pF
+ C63
10 μF
A
+ C59
10 μF
VCCXA_3V
A
A
A
R30
10 Ω
C15
1 μF
A
C53
0.022 μF
R51
750 Ω
R40
10 Ω
A
C34
1 μF
R50
0Ω
A
C16
100 pF
R2
4.7 kΩ
DNI
C25
1 μF
C21
1 nF
VCCMecl/cml_3V
A
VCCCPM_3V
R37
390 Ω
R52
0Ω
DNI
R34
180 Ω
R48
3.9 kΩ
R24
0Ω
R76
0Ω
VCCD_FNFS
R33
18 Ω
C8
68 pF
JP7
1
2
A
A
A
A
C35
100 pF
C26
100 pF
A
C18
22 pF
R10
10 kΩ
R5
10 kΩ
A
20
A
19 18
×
A
A
C41
22 pF
C20
22 pF
R1
4.7 kΩ
C23
1 nF
VCC
DIR
C22
1 μF
7
6
5
4
3
2
1
24
23
22
5
17 16
15
18
R9
4.7 kΩ
A
N/C
14
6
8
24 MHz
Y1
CPout_main
VCCcp_main
LD/PS_main
Fvco_main
Fvco_main
VCCecl/cml
Mux_out
Mod_in
Clock
A2
VCCMecl/cml_3V
R3
R4
DNI
0Ω
OE
B1
A1
17
B2
4
B3
A3
16
B4
A4
3
B5
A5
15
13
A
19
12
7
11
A
20
8
A
A
21
A
9
9
10
R84
0Ω
R83
0Ω
11
SKY72310-362
R11
10 kΩ
A7
2
B7
A8
Xtalin/OSC
14
B6
A6
Xtalacgnd/OSC
B8
GND
Xtalout/NC
16
22
VCCxtal
1
A
A
Data
CS
11 24
GNDXtal
N/C
N/C
N/C
N/C
N/C
N/C
VCCdigital
A
23
C42
22 pF
C36
1 μF
10
A
×
×
14
13
C37
1 nF
A
R44
10 Ω
×
15
A
×
16
12
×
C9
× 1 μF
A
S1259
R16
10 Ω
VCCD_FNFS
C10
100 pF
VCCXA_3V
A
R12
10 kΩ
R6
4.7 kΩ
17
A
25 13
18
19
20
21
12
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
VCCMecl/cml
3V
VNA-25
DNI
VCC
7 5
4 2
R75
120 Ω
R76
18 Ω
VCCMecl/cml
3V
VCCMecl/cml
3V
4
3
VT
VCCMecl/cml
3V
R47
2 kΩ
R46
0Ω
R13
DNI
VCCCPM
3V
5
R40 C25
10 Ω 1 μF
C46
470 pF
C45
100 pF
LD/PSmain
VCCcp_main
R51
750 Ω
R58
0Ω
C53
0.022 μF
7
8
9
×
10
C34
1 μF
C64
0.1 μF
VCCCPM
3V
C63
10 μF
VCCMecl/cml
3V
R49
DNI
+
L7
BLM21A601S
C43
DNI
JP4
C66
0.1 μF
1
2
C65
10 μF
C60
0.1 μF
C71
10 μF
VCCMecl/cml
3V
L12
BLM21A601S
L10
BLM21A601S
+
C70
0.1 μF
+
A1
ERA-3SM
DNI
C68
10 μF
C59
10 μF
4
J6
DNI
C74
DNI
1
OUT
C51
DNI
L3
BLM21A601S
R71
0Ω
C72
0.1 μF
3
VCXA
3V
L11
BLM21A601S
C44
DNI
L2
DNI
+
L8
BLM21A601S
J3
C37
1 nF
Y1
24 MHz
VCCD_FNFS
R68
0Ω
VCCXA
3V
C42
22 pF
L6
BLM21A601S
R69
0Ω
C36
1 μF
R84
0Ω
C35
100 pF
C41
22 pF
Power Supply
×
R44
10 Ω
R83
0Ω
R21
0Ω
×
13
12
L1
DNI
1
2
×
14
N/C
11
×
15
N/C
CPout_main
×
16
N/C
C26
100 pF
6
C47
330 pF
GND
V614ME01
Fvco_main
VCCD_FNFS
CD10
100 pF
×
17
N/C
N/C
R48
2 kΩ
4
1
18
N/C
Fvco_main
IN
GND
2
CD9
1 μF
19
C52
DNI
GND
OSC2
VCC
C50
1 μF
C49
1 nF
R52
DNI
VCCcml_main
20
GNDXtal
GND
GND
GND
C20
22 pF
×
3
T2
2
4
3
JP1
C22
DNI
C30
39 pF
R56
DNI
C48
68 pF
1
2
5
1
N/C
R80
10 Ω
R33
18 Ω
RFOUT
1
2
7 8
4 5
2
R39
18 Ω
VCCMecl/cml
3V
JP5
OUT
C18
22 pF
ETC1-1-13
21
VCCxtal
VCCEXT1
R26
120 Ω
GND
GND
R36
120 Ω
R32
18 Ω
IN
R34
18 Ω
6
22
VCCdigital
C16
100 pF
C15
1 μF
1
VCC
3
23
CS
24
Data
R30
10 Ω
Clock
VNA-25
DNI
C13
DNI
Xtalout/NC
C14
DNI
Mod_in
R22
DNI
R16
10 Ω
R24
18 Ω
Xtalin/OSC
8
R73
120 Ω
R74
18 Ω
3
IN
GND
GND
OUT
Mux_out
1
6
To Microprocessor
C2
DNI
GND
GND
GND
C5
68 pF
J1
C1
DNI
Xtalacgnd/OCS
R4
DNI
2
R57
DNI
+
R59
DNI
R61
DNI
VCCMecl/cml
3V
TTS05V-19.2MHz
DNI
R72
DNI
C55
DNI
4
C56
DNI
2
VDD
GND
OUT
VCONT
3
C54
DNI
R60
DNI
VCCMecl/cml
3V
1
+
C57
DNI
C58
DNI
R62
R63 DNI
DNI
S1269
Figure 14. SKY72310 Application Schematic (With Non-Skyworks VCO)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
17
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
2.70 +0.10/–0.15
C
0.20 Ref
Seating Plane
B
Exposed Pad
0.02 +0.03/–0.023
See Detail A
4
3
0.15 C
2X
–B–
2.500
2.70 +0.10/–0.15
A
4
Pin 1
Indicator
0.08 C
2X
Detail C
24X
0.15 C
0.90 ± 0.10
Side View
Top View
Detail B
(4 Places)
2.500
0.10 C
Bottom View
0.5
R0.20
0.35 ± 0.10
0.25
0.25 +0.05/–0.07
0.100 M C A B
0.05 M C
Detail A
Detail C
–A–
All measurements are in millimeters.
Detail B
Dimensioning and tolerancing according to ASME Y14.5M-1994.
(Even Terminal Side)
S1054
Figure 15. SKY72310 24-Pin QFN Package Dimensions
8.00 ± 0.10
∅1.50
2.00 ± 0.05
± 0.10
1.75 ± 0.10
B
A
12.00 +0.30/–0.10
A
5.50 ± 0.05
1.13 ± 0.10
4.00 ± 0.10
Reference Pin
Indicator
4.25 ± 0.10
10o Max
B
∅1.50
± 0.25
0.229 ± 0.02
B
10o Max
Notes:
1. Carrier tape material: black conductive polycarbonate
or polysterene
2. Cover tape material: transparent conductive PSA
3. Cover tape size: 9.3 mm width
4. All measurements are in millimeters
4.25 ± 0.10
A
S1056
Figure 16. SKY72310 Tape and Reel Dimensions
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
18
July 30, 2008 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200705E
DATA SHEET • SKY72310 FREQUENCY SYNTHESIZER
Ordering Information
Model Name
SKY72310 2.1 GHz Frequency Synthesizer
Manufacturing Part Number
SKY72310-362LF
Evaluation Kit Part Number
TW17-D460 (with SKY73120 VCO)
TW14-D880 (with non-Skyworks VCO)
Copyright © 2007, 2008 Skyworks Solutions, Inc. All Rights Reserved.
Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by
Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials or the
information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to
update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.
No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or
information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks Terms and Conditions
of Sale.
THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A
PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSLY
DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS
SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION,
LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury,
death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any
damages resulting from such improper use or sale.
Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of
products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for
applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of stated published specifications or parameters.
Skyworks, the Skyworks symbol, and “Breakthrough Simplicity” are trademarks or registered trademarks of Skyworks Solutions, Inc., in the United States and other countries. Third-party brands
and names are for identification purposes only, and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at www.skyworksinc.com,
are incorporated by reference.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200705E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 30, 2008
19