DATA SHEET CX72301: Spur-Free, 1.0 GHz Dual Fractional-N Frequency Synthesizer Applications • General purpose RF systems • Low bit rate wireless telemetry • Instrumentation • Specialized Mobile Radios (SMRs) and Private Mobile Radios (PMRs) Features • Spur-free operation • 1.0 GHz maximum operating frequency • 500 MHz maximum auxiliary synthesizer • Ultra-small step size, 100 Hz or less • High internal reference frequency enables large loop bandwidth implementations • Very fast switching speed (e.g., below 100 µs) • Phase noise to –96 dBc/Hz inside the loop filter bandwidth @ 950 MHz • Software programmable power-down modes • High-speed serial interface up to 100 Mbps • Three-wire programming • Programmable division ratios on reference frequency • Phase detectors with programmable gain provide a programmable loop bandwidth • Frequency power steering further enhances rapid acquistion time synthesizer is a key building block for high-performance radio system designs that require low power and fine step size. The ultra-fine step size of less than 100 Hz allows this synthesizer to be used in very narrowband wireless applications. With proper temperature sensing or through control channels, the synthesizer’s fine step size can compensate for crystal oscillator or Intermediate Frequency (IF) filter drift. As a result, crystal oscillators or crystals can replace temperature- compensated or ovenized crystal oscillators, reducing parts count and associated component cost. The device’s fine step size can also be used for Doppler shift corrections. The CX72301 has a phase noise floor of –95 dBc/Hz up to 1.0 GHz operation as measured inside the loop bandwidth. This is permitted by the on-chip low noise dividers and low divide ratios provided by the device’s high fractionality. Reference crystals or oscillators up to 50 MHz can be used with the CX72301. The crystal frequency is divided down by independent programmable divider ratios of 1 to 32 for the main and auxiliary synthesizers. The phase detectors can operate at a maximum speed of 25 MHz, which allows better phase noise due to the lower division value. With a high reference frequency, the loop bandwidths can also be increased. Larger loop bandwidths improve the settling times and reduce in-band phase noise. Therefore, typical switching times of less than 100 µs can be achieved. The lower in-band phase noise also permits the use of lower cost Voltage Controlled Oscillators (VCOs) in customer applications. The CX72301 has a frequency power steering circuit that helps the loop filter steer the VCO when the frequency is too fast or too slow, further enhancing acquisition time. Description The unit operates with a three-wire, high-speed serial interface. A combination of a large bandwidth, fine resolution, and the threewire, high-speed serial interface allows for a direct frequency modulation of the VCO. This supports any continuous phase, constant envelope modulation scheme such as Frequency Modulation (FM), Frequency Shift Keying (FSK), Minimum Shift Keying (MSK), or Gaussian Minimum Shift Keying (GMSK). This capability can eliminate the need for In-Phase and Quadrature (I/Q) Digital-To-Analog Converters (DACs), quadrature upconverters, and IF filters from the transmitter portion of the radio system. Skyworks CX72301 direct digital modulation fractional-N frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. This Figure 1 shows a functional block diagram for the CX72301. The device package and pinout for the 28-pin Exposed Pad Thin Shrink Small Outline Package (EP-TSSOP) are shown in Figure 2. • On-chip crystal oscillator • Frequency adjust for temperature compensation • Direct digital modulation • 3 V operation • 5 V output to loop filter • 28-pin EP-TSSOP 6.4 x 9.7 mm package Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 1 DATA SHEET • CX72301 Registers Data Clock Modulator Data Serial Interface CS Mod_in Main ∆Σ Main Divider Modulator Control Ref. Divider Synth Control Aux. Divider Modulation Unit Aux. ∆Σ Mux_out Mux ∆Σ 18-Bit ∆Σ 10-Bit Fractional Unit Fractional Unit Reference Frequency Oscillator Fvco_main Fvco_main Fvco_aux Main Divider Main Divider Auxiliary Divider Fpd_main Fref_main Main Phase/Freq. Detector and Charge Pump CPout_main LD/PSmain Lock Detection or Power Steering Fref_aux Fref Reference Frequency Oscillator Auxiliary Prescaler Fvco_aux Fpd_aux Auxiliary Phase/Freq. Detector and Charge Pump CPout_aux LD/PSaux Lock Detection or Power Steering C1447 Figure 1. CX72301 Functional Block Diagram Clock 1 28 CS Mod_in 2 27 Data Mux_out 3 26 VCCdigital VSUBdigital 4 25 GNDdigital GNDcml 5 24 VCCcml_aux VCCcml_main 6 23 Fvco_aux Fvco_main 7 22 Fvco_aux Fvco_main 8 21 GNDcp_aux LD/PSmain 9 20 CPout_aux VCCcp_main 10 19 VCCcp_aux CPout_main 11 18 LD/PSaux GNDcp_main 12 17 GNDxtal Xtalacgnd/OSC 13 16 VCCxtal Xtalin/OSC 14 15 Xtalout/NC C1412 Figure 2. CX72301 Pinout, 28-Pin EP-TSSOP (Top View) Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 2 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 Technical Description The CX72301 is a fractional-N frequency synthesizer using a ∆Σ modulation technique. The fractional-N implementation provides low in-band noise by having a low division ratio and fast frequency settling time. In addition, the CX72301 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the RF transceiver. 38 to 537 are possible in fractional-N mode and from 32 to 543 in integer-N mode. Reference Frequency Oscillator The CX72301 has a self-contained, low-noise crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers. Serial Interface Reference Frequency Dividers The serial interface is a versatile three-wire interface consisting of three pins: Clock (serial clock), Data (serial input), and CS (chip select). It enables the CX72301 to operate in a system where one or multiple masters and slaves are present. To perform a loopback test at start-up and to check the integrity of the board and processor, the serial data is fed back to the master device (e.g., a microcontroller or microprocessor unit) through a programmable multiplexer. This facilitates hardware and software debugging. The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. The CX72301 has both a main and an auxiliary frequency synthesizer, and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. The divide ratios are programmed through the Reference Frequency Dividers Register. Registers There are ten 16-bit registers in the CX72301. For more information, see the Register Descriptions section of this document. Main and Auxiliary ∆Σ Modulators The fractionality of the CX72301 is accomplished by the use of a proprietary, configurable 10-bit or 18-bit ∆Σ modulator for the main synthesizer and 10-bit ∆Σ modulator for the auxiliary synthesizer. Main and Auxiliary Fractional Units The CX72301 provides fractionality through the use of main and auxiliary ∆Σ modulators. The output from the modulators is combined with the main and auxiliary divider ratios through their respective fractional units. NOTE: The divided crystal oscillator frequencies (which are the internal reference frequencies), Fref_main and Fref_aux, are referred to as the reference frequencies throughout this document. Phase Detectors and Charge Pumps The CX72301 uses a separate charge pump phase detector for each synthesizer which provides a programmable gain, Kd, from 31.25 to 1000 µA/2π radians in 32 steps programmed using the Control Register. Frequency Steering When programmed for frequency power steering, the CX72301 has a circuit that helps the loop filter steer the VCO using the LD/PSmain signal (pin 9). In this configuration, the LD/PSmain signal can provide a more rapid acquisition. When programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detectors. VCO Prescalers The VCO prescalers provide low-noise signal conditioning of the VCO signals. They translate from an off-chip, single-ended or differential signal to an on-chip differential Current Mode Logic (CML) signal. The CX72301 has independent main and auxiliary VCO prescalers. Lock Detection Main and Auxiliary VCO Dividers Power Down The CX72301 provides programmable dividers that control the CML prescalers and supply the required signals to the charge pump phase detectors. Programmable divide ratios ranging from The CX72301 supports a number of power-down modes through the serial interface. For more information, see the Register Descriptions section of this document. When programmed for lock detection, the CX72301 provides an active low, pulsing open collector output using the LD/PSmain signal (pin 9) to indicate the out-of-lock condition. When locked, the LD/PSmain signal is three-stated (high impedance). Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 3 DATA SHEET • CX72301 Operation Synthesizer Register Programming This section describes the operation of the CX72301. The serial interface is described first, followed by information on how to obtain values for the Divide Ratio Registers. Synthesizer register programming equations, described in this section, use the following variables and constants: Nfractional Desired VCO division ratio in fractional-N applications. This is a real number and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. Ninteger Desired VCO division ratio in integer-N applications. This number is an integer and can be interpreted as the reference frequency (Fref) multiplying factor so that the resulting frequency is equal to the desired VCO frequency. Nreg 9-bit unsigned input value to the divider ranging from 0 to 511 (integer-N mode) and from 6 to 505 (fractional-N mode). divider This constant equals 262144 when the ∆Σ modulator is in 18-bit mode, and 1024 when the ∆Σ modulator is in 10-bit mode. Serial Interface The serial interface consists of three signals: Clock (pin 1), Data (pin 27) and CS (pin 28). The Clock signal controls data on the two serial data lines (Data and CS). The Data pin bits shift into a temporary register on the rising edge of Clock. The CS line allows individual selection transfers that synchronize and sample the information of slave devices on the same bus. Figure 3 functionally depicts how a serial transfer takes place. A serial transfer is initiated when a microcontroller or microprocessor forces the CS line to a low state. This is followed immediately by an address/data stream sent to the Data pin that coincides with the rising edges of the clock presented on the Clock line. Each rising edge of the Clock signal shifts in one bit of data on the Data line into a shift register. At the same time, one bit of data is shifted out of the Mux_out pin (if the serial bit stream is selected) at each falling edge of Clock. To load any of the synthesizer registers, 16 bits of address or data must be presented to the Data line with the data LSB last while CS is low. If CS is low for more than 16 clock cycles, only the last address or data bits are used to load the synthesizer registers. dividend When in 18-bit mode, this is the 18-bit signed input value to the ∆Σ modulator, ranging from –131072 to +131071 and providing 262144 steps, each of Fdiv_ref/218 Hz. When in 10-bit mode, this is the 10-bit signed input value to the ∆Σ modulator, ranging from –512 to +511 and providing 1024 steps, each of Fdiv_ref/210 Hz. If the CS line is brought to a high state before the 13th clock edge on Clock, the bit stream is assumed to be modulation data samples. In this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the Modulation Data Register. FVCO Desired VCO frequency (either Fvco_main or Fvco_aux). Fdiv_ref Divided reference frequency presented to the phase detector (either Fref_main or Fref_aux). Clock Data X A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 XXX CS Last C1413 Figure 3. Serial Transfer Timing Diagram Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 4 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 Fractional-N Applications. The desired division ratio for the main and auxiliary synthesizer is given by the following equation: The value to be programmed in the Main or Auxiliary Dividend Register is given by the following equation: F VCO N f rac tion al = -----------------F di v_r ef dividend = R ound divider where Nfractional must be between 37.5 and 537.5. The value to be programmed in the Main or Auxiliary Divider Register is given by the equation: N r eg = R ound N fr actio nal – 32 NOTE: The Round function rounds the number to the nearest integer. When in fractional mode, allowed values for Nreg are from 6 to 505, inclusive. N f ra ctio nal – N reg – 32 where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. Therefore, the dividend is a signed binary value either 10 or 18 bits long. NOTE: Because of the high fractionality of the CX72301, there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired VCO frequencies. Sample calculations for two fractional-N applications are provided in Figure 4. Case 1: To achieve a desired Fvco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore: Nfractional = Fvco_main Fdiv_ref = 902.4530 20 = 45.12265 The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] – 32 = Round[45.12265] – 32 = 45 – 32 = 13 (decimal) = 000001101 (binary) With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider × (Nfractional – Nreg – 32)] = Round[262144 × (45.12265 – 13 – 32)] = Round[262144 × (0.12265)] = Round[32151.9616] = 32152 (decimal) = 000111110110011000 (binary) where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the Main Dividend Register. Summary: · · · · · Main Divider Register = 0 0000 1101 Main Dividend LSB Register = 1001 1000 Main Dividend MSB Register = 00 0111 1101 The resulting main VCO frequency is 902.453 MHz Step size is 76.3 Hz Note: The frequency step size for this case is 20 MHz divided by 218, giving 76.3 Hz. C1414 Figure 4. Fractional-N Applications: Sample Calculation (1 of 2) Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 5 DATA SHEET • CX72301 Case 2: To achieve a desired Fvco_main frequency of 917.7786 MHz using a crystal frequency of 19.2 MHz with operation of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency does not require the internal division to be greater than 1, which makes Fdiv_ref = 19.2 MHz. Therefore: Nfractional = Fvco_main Fdiv_ref = 917.7786 19.2 = 47.80097 The value to be programmed in the Main Divider Register is: Nreg = Round[Nfractional] – 32 = Round[47.80097] – 32 = 48 – 32 = 16 (decimal) = 000010000 (binary) With the modulator in 10-bit mode, the value to be programmed in the Main Dividend Registers is: dividend = Round[divider × (Nfractional – Nreg – 32)] = Round[1024 × (47.80097 – 16 – 32)] = Round[1024 × (– 0.1990312)] = Round[– 203.808] = 204 (decimal) = 1100110100 (binary) where 11 0011 0100 is loaded in the MSB of the Main Dividend Register. Summary: · · · · Main Divider Register = 0 0001 0000 Main Dividend MSB Register = 11 0011 0100 The resulting main VCO frequency is 917.775 MHz Step size is 18.75 kHz Note: The frequency step size for this case is 19.2 MHz divided by 210, giving 18.75 kHz. C1415 Figure 4. Fractional-N Applications: Sample Calculation (2 of 2) Integer-N Applications. The desired division ratio for the main or auxiliary synthesizer is given by: F VC O _m ai n N i nt ege r = --------------------------F d iv _re f where Ninteger is an integer number from 32 to 543 for both the main and auxiliary synthesizers. The value to be programmed in the Main or Auxiliary Divider Register is given by the following equation: A sample calculation for an integer-N application is provided in Figure 5. Register Loading Order. In applications where the main synthesizer is in 18-bit mode, the Main Dividend MSB Register holds the 10 MSBs of the dividend and the Main Dividend LSB Register holds the 8 LSBs of the dividend. The registers that control the main synthesizer’s divide ratio are to be loaded in the following order: • Main Divider Register • Main Dividend LSB Register N r eg = F intege r – 32 When in integer mode, allowed values for Nreg are from 0 to 511 for both the main and auxiliary synthesizers. • Main Dividend MSB Register (at which point the new divide ratio takes effect) NOTE: As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 6 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum divide ratio is 32, the reference frequency (Fdiv_ref) must be a maximum of 12.5 MHz. Choosing a reference frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore: Ninteger = Fvco_aux Fdiv_ref = 400 8 = 50 The value to be programmed in the Auxiliary Divider Register is: Nreg = Ninteger – 32 = 50 – 32 = 18 (decimal) = 000010010 (binary) Summary: · Auxiliary Divide Register = 0 0001 0010 C1416 Figure 5. Integer-N Applications: Sample Calculation In applications where the main synthesizer is in 10-bit mode, the Main Dividend Register holds the 10 bits of the dividend. The registers that control the main synthesizer’s divide ratio are to be loaded in the following order: 16-bit modulation data is simultaneously presented to the Data pin. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). • Main Divider Register Short CS Through Data Pin (No Address Bits Required). A shortened serial interface write occurs when CS is 16 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Data pin. The Data pin is the default pin used to enter modulation data directly into the Modulation Data Register with shortened CS strobes. This method of data entry eliminates the register address overhead on the serial interface. All serial interface bits are re-synchronized internally at the reference oscillator frequency. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). • Main Dividend MSB Register (at which point the new divide ratio takes effect) For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The registers that control the auxiliary synthesizer’s divide ratio are to be loaded in the following order: • Auxiliary Divider Register • Auxiliary Dividend Register (at which point the new divide ratio takes effect) NOTE: When in integer mode, the new divide ratios take effect when the Main or Auxiliary Divider Register is loaded. Direct Digital Modulation The high fractionality and small step size of the CX72301 allow the VCO to be tuned to practically any frequency in the VCO’s operating range. This frequency tuning allows direct digital modulation by programming the different desired frequencies at precise instants. Typically, the channel frequency is selected through the Main Divider and Dividend Register and the instantaneous frequency offset from the carrier is entered through the Modulation Data Register. The Modulation Data Register can be accessed in three ways, which are defined in the following subsections. Short CS Through Mod_in Pin (No Address Bits Required). A shortened serial interface write where CS is from 2 to 12 clock cycles wide and modulation data (2 to 12 bits) is presented on the Mod_in pin. The Mod_in pin is the alternate pin used to enter modulation data directly into the Modulation Data Register with shortened CS strobes. This mode is selected through the Modulation Control Register. This method of data entry also eliminates the register address overhead on the serial interface and allows a different device than the one controlling the channel selection to enter the modulation data (e.g., a microcontroller for channel selection and a digital signal processor for modulation data). All serial interface bits are re-synchronized internally at the reference oscillator frequency and the content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main). Normal Register Write. A normal 16-bit serial interface write occurs when CS is 16 clock cycles wide. The corresponding Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 7 DATA SHEET • CX72301 Modulation data samples in the Modulation Data Register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. The user can also control the frequency deviation through the modulation data magnitude offset in the Modulation Control Register. This allows shifting of the modulation data to accomplish a 2m multiplication of frequency deviation. NOTE: The programmable range of –0.5 to +0.5 of the main ∆Σ modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to the following relationship: -0.5625 N mod dividend +0.5625 When the sum of the dividend and modulation data lie outside this range, the value of Ninteger must be changed. For a more detailed description of direct digital modulation functionality, refer to the Skyworks Application Note, Direct Digital Modulation Using the CX72300, CX72301, and CX72302 Dual Synthesizers/PLLs (document number 101349). Synthesizer Registers Main Synthesizer Registers. The Main Divider Register contains the integer portion closest to the desired fractional-N (or the integer-N) value minus 32 for the main synthesizer. This register, in conjunction with the Main Dividend Registers (which control the fraction offset from –0.5 to +0.5), allows selection of a precise frequency. As shown in Figure 6, the value to be loaded is: • Main Synthesizer Divider Index = 9-bit value for the integer portion of the main synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N). The Main Dividend MSB and LSB Registers control the fraction part of the desired fractional-N value and allow an offset of –0.5 to + 0.5 to the main integer selected through the Main Divider Register. As shown in Figures 7 and 8, values to be loaded are: • Main Synthesizer Dividend (MSBs) = 10-bit value for the MSBs of the 18-bit dividend for the main synthesizer. • Main Synthesizer Dividend (LSBs) = 8-bit value for the LSBs of the 18-bit dividend for the main synthesizer. The Main Dividend MSB and LSB Register values are 2's complement format. NOTE: When in 10-bit mode, the Main Synthesizer Dividend (LSBs) is not required. Register Descriptions This section describes the CX72301 registers. All register writes are programmed address first, followed directly with data. MSBs are entered first. On power-up, all registers are reset to 0x000 except registers at address 0x0 and 0x3, which are set to 0x006. For information on programming and loading order for these registers, see the Operation section of this document. Table 1 provides a description for each of the CX72301 device registers. For more information on register loading, refer to the Synthesizer Register Programming section in this document. Table 1. CX72301 Register Map Address (Hex) Length (Bits) Address (Bits) 0 Main Divider Register Register (Note 1) 12 4 1 Main Dividend MSB Register 12 4 2 Main Dividend LSB Register 12 4 3 Auxiliary Divider Register 12 4 4 Auxiliary Dividend Register 12 4 5 Reference Frequency Dividers Register 12 4 6 Control Register—phase detector/charge pumps 12 4 7 Control Register—power down/multiplexer output select 12 4 8 Modulation Control Register 12 4 9 Modulation Data Register 12 4 — Modulation Data Register (Note 2) — direct input 2 ≤ length ≤ 12 bits 0 Note 1: All registers are write only. Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 8 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 A3 0 A2 A1 0 0 A0 11 0 X 10 9 8 X X MSB 7 6 5 4 3 2 1 0 LSB Main Synthesizer Divider Index C1417 Figure 6. Main Divider Register (Write Only) A3 0 A2 A1 0 0 A0 11 1 X 10 9 8 7 6 5 4 3 2 1 X MSB 0 LSB Main Synthesizer Dividend (MSBs) C1418 Figure 7. Main Dividend MSB Register (Write Only) A3 0 A2 A1 0 1 A0 11 0 X 10 9 8 7 X X X MSB 6 5 4 3 2 1 0 LSB Main Synthesizer Dividend (LSBs) C1419 Figure 8. Main Dividend LSB Register (Write Only) Auxiliary Synthesizer Registers. The Auxiliary Divider Register contains the integer portion closest to the desired fractional-N (or integer-N) value minus 32 for the auxiliary synthesizer. This register, in conjunction with the Auxiliary Dividend Register, which controls the fraction offset (from –0.5 to + 0.5) allows selection of a precise frequency. As shown in Figure 9, the value to be loaded is: • Auxiliary Synthesizer Divider Index = 9-bit value for the integer portion of the auxiliary synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N). The Auxiliary Dividend Register controls the fraction part of the desired fractional-N value and allows an offset of –0.5 to + 0.5 to the auxiliary integer selected through the Auxiliary Divider Register. As shown in Figure 10, the value to be loaded is: • Auxiliary Synthesizer Dividend = 10-bit value for the dividend for the auxiliary synthesizer. For information on programming and loading order for these registers, see the Operation section of this document. General Synthesizer Registers. The Reference Frequency Dividers Register configures the dual-programmable reference frequency dividers for the main and auxiliary synthesizers. The dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. The lower five bits hold the reference frequency divide index for the main phase detector. The next five bits hold the reference frequency divide index for the auxiliary phase detector. Divide ratios from 1 to 32 are possible for each reference frequency divider (see Tables 2 and 3). As shown in Figure 11, the values to be loaded are: • Main Reference Frequency Divider Index = Desired main oscillator frequency division ratio – 1. Default value on powerup is 0, signifying that the reference frequency is not divided for the main phase detector. • Auxiliary Reference Frequency Divider Index = Desired auxiliary oscillator frequency division ratio – 1. Default value on power- Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 9 DATA SHEET • CX72301 steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector. • Auxiliary Phase Detector Gain = 5-bit value for programmable auxiliary phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 µA/2π radian, respectively. The Control Register allows control of the gain for both phase detectors and configuration of the LD/PSmain and LD/PSaux pins for frequency power steering or lock detection. As shown in Figure 12, the values to be loaded are: • Auxiliary Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the auxiliary phase detector. When this bit is a 0, the LD/PSaux pin is configured to be a lock detect, active-low, open collector pin. When this bit is a 1, the LD/PSaux pin is configured to be a frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition. • Main Phase Detector Gain = 5-bit value for programmable main phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 µA/2π radian, respectively. • Main Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the main phase detector. When this bit is a 0, the LD/PSmain pin is configured to be a lock detect, active-low, open collector pin. When this bit is a 1, the LD/PSmain pin is configured to be a frequency power A3 0 A2 A1 0 1 A0 11 1 X 10 9 X X MSB 8 7 6 5 4 3 2 1 0 LSB Auxiliary Synthesizer Divider Index C1420 Figure 9. Auxiliary Divider Register (Write Only) A3 0 A2 A1 1 0 A0 11 0 X 10 9 8 7 6 5 4 X MSB 3 2 1 0 LSB Auxiliary Synthesizer Dividend C1421 Figure 10. Auxiliary Dividend Register (Write Only) Table 2. Programming the Main Reference Frequency Divider Decimal Bit 4 (MSB) Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Reference Divider Ratio 0 0 0 0 0 0 1 1 0 0 0 0 1 2 2 0 0 0 1 0 3 — — — — — — — — — — — — — — — — — — — — — 31 1 1 1 1 1 32 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 10 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 Table 3. Programming the Auxiliary Reference Frequency Divider Decimal Bit 9 (MSB) Bit 8 Bit 7 Bit 6 Bit 5 (LSB) Reference Divider Ratio 0 0 0 0 0 0 1 1 0 0 0 0 1 2 2 0 0 0 1 0 3 — — — — — — — — — — — — — — — — — — — — — 31 1 1 1 1 1 32 A3 0 A2 A1 1 0 A0 11 1 X 10 9 8 7 6 5 4 3 2 1 0 X Main Reference Frequency Divider Index Auxiliary Reference Frequency Divider Index C1422 Figure 11. Reference Frequency Dividers Register (Write Only) A3 0 A2 A1 1 1 A0 11 10 9 8 7 6 5 4 3 2 1 0 0 Main Phase Detector Gain Main Power Steering/Lock Detect Enable Auxiliary Phase Detector Gain Auxiliary Power Steering/Lock Detect Enable C1423 Figure 12. Control Register (Write Only) The Power Down and Multiplexer Output Register allows control of the power-down modes, internal multiplexer output, and main ∆Σ synthesizer fractionality. As shown in Figure 13, the values to be loaded are: • Full Power-Down = 1-bit value that powers down the CX72301 except for the reference oscillator and the serial interface. When this bit is 0, the CX72301 is powered up. When this bit is 1, the CX72301 is in full power-down mode excluding the Mux_out pin. • Main Synthesizer Power-Down = 1-bit value that powers down the main synthesizer. When this bit is 0, the main synthesizer is powered up. When this bit is 1, the main synthesizer is in power-down mode. • Main Synthesizer Mode = 1-bit value that powers down the main synthesizer’s ∆Σ modulator and fractional unit to operate as an integer-N synthesizer. When this bit is 0, the main synthesizer is in a fractional-N mode. When this bit is 1, the main synthesizer is in integer-N mode. • Main Synthesizer ∆Σ Fractionality = 1-bit value that configures the size of the main ∆Σ modulator. This has a direct effect on power consumption and on the level of fractionality and step size. When this bit is 0, the main ∆Σ modulator is 18-bit with a fractionality of 218 and a step size of Fref_main/262144. When this bit is 1, the main ∆Σ modulator is 10-bit with a fractionality of 210 and a step size of Fref_main/1024. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 11 DATA SHEET • CX72301 • Multiplexer Output Selection = 3-bit value that selects which internal signal is output to the Mux_out pin. Internal signals available on this pin are the following: − Reference Oscillator, Fref − Main or auxiliary divided reference (post reference frequency main or auxiliary dividers), Fref_main or Fref_aux − Main or auxiliary phase detector frequency (post main and auxiliary frequency dividers), Fpd_main or Fpd_aux − Serial data out, for loop-back and test purposes • Auxiliary Synthesizer Power Down = 1-bit value that powers down the auxiliary synthesizer. When this bit is 0, the auxiliary synthesizer is powered up. When this bit is 1, the auxiliary synthesizer is in power-down mode. • Auxiliary Synthesizer mode = 1-bit value that powers down the auxiliary synthesizer’s ∆Σ modulator and fractional unit to operate as an integer-N synthesizer. When this bit is 0, the auxiliary synthesizer is in fractional-N mode. When this bit is 1, the auxiliary synthesizer is in integer-N mode. See Table 4 for more information. NOTE: There are no special power-up sequences required for the CX72301. A3 0 A2 A1 1 1 A0 11 1 X 10 9 X 8 7 MSB 6 5 • Mux_out Pin Three-State Enable = 1-bit value to three-state the Mux_out pin. When this bit is 0, the Mux_out pin is enabled. When this bit is 1, the Mux_out pin is three-stated. 4 3 2 1 0 LSB Full Power Down Main Synthesizer Power Down Main Synthesizer Mode Main Synthesizer ∆Σ Fractionality Auxiliary Synthesizer Power Down Auxiliary Synthesizer Mode Multiplexer Output Selection Mux_out Pin Three-State Enable C1424 Figure 13. Power Down and Multiplexer Output Register (Write Only) Table 4. Multiplexer Output Multiplexer Output Select (Bit 8) Multiplexer Output Select (Bit 7) Multiplexer Output Select (Bit 6) Multiplexer Output (Mux_out) 0 0 0 Reference Oscillator 0 0 1 Auxiliary Reference Frequency (Fref_aux) 0 1 0 Main Reference Frequency (Fref_main) 0 1 1 Auxiliary Phase Detector Frequency (Fpd_aux) 1 0 0 Main Phase Detector Frequency (Fpd_main) 1 0 1 Serial data out 1 1 0 Serial Interface Register test output Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 12 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 The Modulation Control Register is used to configure the modulation unit of the main synthesizer. The modulation unit adds or subtracts a frequency offset to the selected center frequency at which the main synthesizer operates. The size of the modulation data sample, controlled by the duration of the CS signal, can be from 2 to 12 bits wide, to provide from 4 to 4096 selectable frequency offset steps. • Modulation Address Disable = 1-bit value that indicates the presence of the address as modulation data samples are presented on either the Mod_in or Data pins. When this bit is 0, the address is presented with the modulation data samples (i.e., all transfers are 16 bits long). When this bit is 1, no address is presented with the modulation data samples (i.e., all transfers are 2 to 12 bits long). The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8. As shown in Figure 14, the values to be loaded are: The Modulation Data Register is used to load the modulation data samples to the modulation unit. This value is transferred to the modulation unit on the falling edge of Fpd_main where it is passed to the main ∆Σ modulator at the selected magnitude offset on the next falling edge of Fpd_main. Modulation Data register values are 2's complement format. As shown in Figure 15, the value to be loaded is: • Modulation Data Magnitude Offset = 4-bit value that indicates the magnitude multiplier (m) for the modulation data samples. Valid values range from 0 to 13, effectively providing a 2m multiplication of the modulation data sample. • Modulation Data Bits = Modulation data samples that represent the desired instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the modulation data magnitude offset. • Modulation Data Input Select = 1-bit value that indicates the pin on which modulation data samples are serially input when the CS signal is between 2 and 12 bits long. When this bit is 0, modulation data samples are to be presented on the Data pin. When this bit is 1, modulation data samples are to be presented on the Mod_in pin. A3 1 A2 A1 0 0 A0 11 0 10 X 9 8 7 6 5 4 X 3 2 1 0 0 0 0 0 Reserved Bits Modulation Data Magnitude Offset Modulation Data Input Select Modulation Address Disable C1425 Figure 14. Modulation Control Register (Write Only) A3 1 A2 A1 0 0 A0 11 1 MSB 10 9 8 7 6 5 4 3 2 1 0 LSB Modulation Data Bits C1426 Figure 15. Modulation Data Register (Write Only) Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 13 DATA SHEET • CX72301 Electrical and Mechanical Specifications The CX72301 is supplied as a 28-pin EP-TSSOP. The exposed pad is located on the bottom side of the package and must be connected to ground for proper operation. The exposed pad should be soldered directly to the circuit board. Signal pin assignments and functional pin descriptions are specified in Table 5. The absolute maximum ratings of the CX72301 are provided in Table 6. The recommended operating conditions are specified in Table 7 and electrical specifications are provided in Table 8. Figure 16 provides a schematic diagram for the CX72301. Figure 17 shows the package dimensions for the 28-pin EP-TSSOP and Figure 18 provides the tape and reel dimensions. Electrostatic Discharge (ESD) Sensitivity The CX72301 is a static-sensitive electronic device. Do not operate or store near strong electrostatic fields. Take proper ESD precautions. Table 5. CX72301 Signal Descriptions (1 of 2) Pin # Pin Name Type Description 1 Clock Digital input Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the Data pin on the rising edge of Clock. 2 Mod_in Digital input Alternate serial modulation data input pin. Address bits are followed by data bits. 3 Mux_out Digital output Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main or auxiliary divided VCO frequency, serial data out, or testability signals. This pin can be three-stated from the general synthesizer registers. 4 VSUBdigital 5 GNDecl/cml (Note 1) Power and ground Emitter Coupled Logic (ECL)/Current Mode Logic (CML) ground. 6 VCCcml_main (Note 1) Power and ground ECL/CML 3 V. Removing power safely powers down the associated divider chain and charge pump. – Substrate isolation. Connect to ground. 7 Fvco_main Input Main VCO differential input. 8 Fvco_main Input Main VCO complimentary differential input. 9 LD/PSmain Analog output Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This pin is configured from the general synthesizer registers. 10 VCCcp_main (Note 1) Power and ground Main charge pump 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. 11 CPout_main Analog output Main charge pump output. The gain of the main charge pump phase detector can be controlled from the general synthesizer registers. 12 GNDcp_main (Note 1) Power and ground Main charge pump ground. 13 Xtalacgnd/OSC Ground/input Reference crystal AC ground or external oscillator differential input. 14 Xtalin/OSC Input Reference crystal input or external oscillator differential input. 15 Xtalout/NC Input Reference crystal output or no connect. 16 VCCxtal Power and ground Crystal oscillator ECL/CML 3 V. 17 GNDxtal Power and ground Crystal oscillator ground. 18 LD/PSaux Analog output Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO. This pin is configured from the general synthesizer registers. 19 VCCcp_aux (Note 1) Power and ground Auxiliary charge pump 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. 20 CPout_aux Analog output Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector can be controlled from the general synthesizer registers. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 14 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 Table 5. CX72301 Signal Descriptions (2 of 2) Pin # Pin Name Type Description 21 GNDcp_aux (Note 1) Power and ground Auxiliary charge pump ground. 22 Fvco_aux Input Auxiliary VCO complimentary differential input. 23 Fvco_aux Input Auxiliary VCO differential input. 24 VCCcml_aux (Note 1) Power and ground ECL/CML 3 V. Removing power safely powers down the associated divider chain and charge pump. 25 GNDdigital (Note 1) Power and ground Digital ground. 26 VCCdigital (Note 1) Power and ground Digital 3 V. 27 Data Digital input Serial address and data input pin. Address bits are followed by data bits. 28 CS Digital input Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock. When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges are ignored. Note 1: Associated pairs of power and ground pins must be decoupled using 0.1 µF capacitors. Table 6. Absolute Maximum Ratings Parameter Min Max Units 3.6 VDC Maximum digital supply voltage 3.6 VDC Maximum charge pump supply voltage 5.25 VDC Maximum analog RF supply voltage Storage temperature –65 +150 °C Operating temperature –40 +85 °C Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other parameters set at or below their nominal values. Table 7. Recommended Operating Conditions Min Max Units Analog RF supplies Parameter 2.7 3.3 VDC Digital supply 2.7 3.3 VDC Charge pump supplies 2.7 5.0 VDC Operating temperature (TA) –40 +85 °C Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 15 DATA SHEET • CX72301 Table 8. Electrical Characteristics (1 of 2) (VDD = 3 V, TA = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units Power Consumption Total power consumption Power-down current PTOTAL Charge pump currents of 200 µA. Both synthesizers fractional, FREF_MAIN = 20 MHz, FREF_AUX = 1 MHz 33 mW Auxiliary synthesizer power down 23 mW 10 (Note 1) µA ICC-PWDN Reference Oscillator Reference oscillator frequency FOSC 50 MHz Oscillator sensitivity (as a buffer) VOSC AC coupled, single-ended 2.0 Vpp Frequency shift versus supply voltage FSHIFT_SUPPLY 2.7 V ≤ VXTAL ≤ 3.3 V ±0.3 ppm Main synthesizer operating frequency FVCO_MAIN Sinusoidal, –40 °C to +85 °C 100 (Note 2) 1000 MHz Auxiliary synthesizer operating frequency FVCO_AUX Sinusoidal, –40 °C to +85 °C 100 (Note 2) 500 MHz RF input sensitivity VVCO AC coupled, –40 °C to +85 °C 50 250 mVpeak RF input impedance ZVCO_IN Main fractional-N tuning step size ∆FSTEP_MAIN Auxiliary fractional-N tuning step size ∆FSTEP_AUX 0.1 VCOs 150 – j168 @ 800 MHz Ω FREF_MAIN/218 or FREF_MAIN/210 Hz FREF_AUX/2 10 Hz Noise Phase noise floor Pnf Measured inside the loop bandwidth using 25 MHz reference frequency, –40 °C to +85 °C –130 + 20 Log (N) dBc/Hz Main phase detector frequency FREF_MAIN –40 °C to +85 °C 25 MHz Auxiliary phase detector frequency FREF_AUX –40 °C to +85 °C 25 MHz Phase Detectors and Charge Pumps Charge pump output source current ICP-SOURCE VCP = 0.5 VCCCP 125 1000 µA Charge pump output sink current ICP-SINK VCP = 0.5 VCCCP –125 –1000 µA Charge pump accuracy ICP-ACCURACY Charge pump output voltage linearity range ICP vs VCP 0.5 V ≤ VCP ≤ (VCCCP – 0.5 V) Charge pump current versus temperature ICP vs T Charge pump current versus voltage ICP vs VCP ±20 % VCCCP – 400 mV VCP = 0.5 VCCCP –40 °C < T < +85 °C 5 % 0.5 V ≤ VCP ≤ (VCCCP – 0.5 V) 8 % GND + 400 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 16 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H DATA SHEET • CX72301 Table 8. Electrical Characteristics (2 of 2) (VDD = 3 V, TA = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units Digital Pins High level input voltage VIH Low level input voltage VIL 0.7 VDIGITAL High level output voltage VOH IOH = –2 mA Low level output voltage VOL IOL = +2 mA V 0.3 VDIGITAL VDIGITAL –0.2 V V GND + 0.2 V 100 MHz Timing – Serial Interface Clock frequency fCLOCK Data and CS set up time to Clock rising tSU 3 ns Data and CS hold time after Clock rising tHOLD 0 ns Note 1: A 5 V charge pump power supply (on pin 10 and/or pin 19) results in higher power-down leakage current. Note 2: The minimum synthesizer frequency is 12 x FOSC, where FOSC is the frequency at the Xtalin/OSC pin. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 17 5 4 3 VCC A GND Main VCO VCC 2 RF Out Main J1 1 3 VT 1 2 RFOUT A R4 C14 A A C15 C17 R5 R1 100 k Ω Main Synthesizer Loop Filter 4 Lock Detect Main Output 3V C3 1 nF A 3V A A 3V C16 100 pF C11 1 nF A C7 C5 A C19 A 14 13 12 11 10 9 8 7 6 5 4 3 2 Xtalin/OSC Xtalacgnd/OSC GNDcp_main CPout_main VCCcp_main LD/PSmain Fvco_main Fvco_main VCCcml_main GNDecl/cml VSUBdigital Mux_out Mod_in Clock Y1 A External Pad Connection to Ground Xtalout/NC VCCxtal GNDxtal LD/PSaux VCCcp_aux CPout_aux GNDcp_aux Fvco_aux Fvco_aux VCCcml_aux GNDdigital VCCdigital Data CS A 15 16 17 18 19 20 A A C18 C17 1 nF C6 22 21 C4 A A 23 24 25 26 27 28 3V A 3V C2 1 nF R6 100 k Ω 3V C10 1 nF A 3V C8 A A A VCC C12 R3 R2 A Auxiliary VCO 4 GND Auxiliary VCO A 1 2 RF Out Auxiliary J1 3 C9 3 VCC 5 C1427 Auxiliary Synthesizer Loop Filter A C1 1 nF Lock Detect Auxiliary Output 3V 2 RFOUT 1 GND 29 4 VT 18 1 To Microprocessor DATA SHEET • CX72301 Figure 16. CX72301 Application Schematic July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com DATA SHEET • CX72301 0.65 BSC Pin 1 3.00 6.40 BSC 4.4 ± 0.10 0.25 +0.5/–0.6 9.70 BSC 5.50 Top View Exposed Pad Bottom View 0.90 ± 0.05 1.10 0.10 ± 0.05 0.60 ± 0.10 Side View All measurements are in millimeters C1428 Figure 17. CX72301 28-Pin EP-TSSOP Package Dimensions 4.00 ± 0.10 2.00 ± 0.05 8.00 ± 0.10 1.50 ± 0.10 Pin #1 B A 7.50 ± 0.10 A 16.00 +0.30/–0.10 1.75 ± 0.10 B 1.50 ± 0.25 3.96 0.318 ± 0.013 1.10 8o Max 6.75 ± 0.10 7o Max 9.95 ± 0.10 1.60 ± 0.10 Notes: 1. 2. 3. 4. A Carrier tape material: black conductive polycarbonate or polystyrene Cover tape material: transparent conductive PSA Cover tape size: 13.3 mm width All measurements are in millimeters B C1430 Figure 18. CX72301 Tape and Reel Dimensions Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 101090H • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • July 21, 2004 19 DATA SHEET • CX72301 Ordering Information Model Name CX72301 Frequency Synthesizer Manufacturing Part Number CX72301-11 Evaluation Kit Part Number PH00-D102 Copyright © 2001, 2002, 2004, Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products. These materials are provided by Skyworks as a service to its customers and may be used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes to its documentation, products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its documentation, products, specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by or under this document. Except as may be provided in Skyworks Terms and Conditions of Sale for such products, Skyworks assumes no liability whatsoever in association with its documentation, products, specifications and product descriptions. THESE MATERIALS ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED OR OTHERWISE, RELATING TO SALE AND/OR USE OF SKYWORKS PRODUCTS INCLUDING WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Product names or services listed in this publication are for identification purposes only, and may be trademarks of Skyworks or other third parties. Third-party brands and names are the property of their respective owners. Additional information, posted at www.skyworksinc.com, is incorporated by reference. Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com 20 July 21, 2004 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 101090H