SKYWORKS SKY72301-22

DATA SHEET
SKY72301-22: Spur-Free, 1.0 GHz Dual Fractional-N
Frequency Synthesizer
Applications
• 5 V output to loop filter
• General purpose RF systems
• EP-TSSOP (28-pin, 9.7 x 6.4 x 1.1 mm) Pb-free (MSL3, 260 °C
per JEDEC J-STD-020) package
• Low bit rate wireless telemetry
• Instrumentation
• Specialized Mobile Radios (SMRs) and Private Mobile Radios
(PMRs)
Features
• Spur-free operation
• 1.0 GHz maximum operating frequency
• 500 MHz maximum auxiliary synthesizer
• Ultra-small step size, 100 Hz or less
• High internal reference frequency enables large loop bandwidth
implementations
• Very fast switching speed (e.g., below 100 µs)
• Phase noise to –96 dBc/Hz inside the loop filter bandwidth
@ 950 MHz
• Software programmable power-down modes
• High-speed serial interface up to 100 Mbps
• Three-wire programming
• Programmable division ratios on reference frequency
• Phase detectors with programmable gain provide a
programmable loop bandwidth
• Frequency power steering further enhances rapid acquistion
time
• On-chip crystal oscillator
• Frequency adjust for temperature compensation
• Direct digital modulation
• 3 V operation
Skyworks offers lead (Pb)-free, RoHS (Restriction of
Hazardous Substances) compliant packaging.
Description
Skyworks SKY72301-22 direct digital modulation fractional-N
frequency synthesizer provides ultra-fine frequency resolution,
fast switching speed, and low phase-noise performance. This
synthesizer is a key building block for high-performance radio
system designs that require low power and fine step size.
The ultra-fine step size of less than 100 Hz allows this synthesizer
to be used in very narrowband wireless applications. With proper
temperature sensing or through control channels, the
synthesizer’s fine step size can compensate for crystal oscillator
or Intermediate Frequency (IF) filter drift. As a result, crystal
oscillators or crystals can replace temperature- compensated or
ovenized crystal oscillators, reducing parts count and associated
component cost. The device’s fine step size can also be used for
Doppler shift corrections.
The SKY72301-22 has a phase noise floor of –95 dBc/Hz up to
1.0 GHz operation as measured inside the loop bandwidth. This is
permitted by the on-chip low noise dividers and low divide ratios
provided by the device’s high fractionality.
Reference crystals or oscillators up to 50 MHz can be used with
the SKY72301-22. The crystal frequency is divided down by
independent programmable divider ratios of 1 to 32 for the main
and auxiliary synthesizers. The phase detectors can operate at a
maximum speed of 25 MHz, which allows better phase noise due
to the lower division value. With a high reference frequency, the
loop bandwidths can also be increased. Larger loop bandwidths
improve the settling times and reduce in-band phase noise.
Therefore, typical switching times of less than 100 µs can be
achieved. The lower in-band phase noise also permits the use of
lower cost Voltage Controlled Oscillators (VCOs) in customer
applications.
The SKY72301-22 has a frequency power steering circuit that
helps the loop filter steer the VCO when the frequency is too fast
or too slow, further enhancing acquisition time.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200706B • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • May 21, 2007
1
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
The unit operates with a three-wire, high-speed serial interface. A
combination of a large bandwidth, fine resolution, and the threewire, high-speed serial interface allows for a direct frequency
modulation of the VCO. This supports any continuous phase,
constant envelope modulation scheme such as Frequency
Modulation (FM), Frequency Shift Keying (FSK), Minimum Shift
Keying (MSK), or Gaussian Minimum Shift Keying (GMSK).
The capability to support such modulation schemes eliminates the
need for In-Phase and Quadrature (I/Q) Digital-To-Analog
Converters (DACs), quadrature upconverters, and IF filters from
the transmitter portion of the radio system.
Figure 1 shows a functional block diagram for the SKY72301-22.
The device package and pinout for the 28-pin Exposed Pad Thin
Shrink Small Outline Package (EP-TSSOP) are shown in Figure 2.
Registers
Data
Clock
Modulation
Data
Serial
Interface
CS
Mod_in
Main
MSB/LSB
Dividend
Main
Divider
Modulation
Control
Ref Freq
Dividers
PD/Charge Pump
Aux
Aux
Divider & Pwr-Dn/Mux Out Dividend
Control
Modulation
Unit
Mux_out
Mux
ΔΣ
18-Bit
ΔΣ
10-Bit
Fractional
Unit
Fractional
Unit
Reference
Frequency
Oscillator
Fvco_main
Fvco_main
Fvco_aux
Main
Divider
Main
Divider
Auxiliary
Divider
Fpd_main
Main
Phase/Freq.
Detector
and
Charge Pump
Fref_main
Fref_aux
Fref
Reference
Frequency
Oscillator
LD/PSmain
Fvco_aux
Fpd_aux
Auxiliary
Phase/Freq.
Detector
and
Charge Pump
CPout_aux
CPout_main
Lock Detection or
Power Steering
Auxiliary
Prescaler
LD/PSaux
Lock Detection or
Power Steering
C1447
Figure 1. SKY72301-22 Functional Block Diagram
Clock
1
28
CS
Mod_in
2
27
Data
Mux_out
3
26
VCCdigital
VSUBdigital
4
25
GNDdigital
GNDcml
5
24
VCCcml_aux
VCCcml_main
6
23
VCCvco_aux
Fvco_main
7
22
Fvco_aux
Fvco_main
8
21
GNDcp_aux
LD/PSmain
9
20
CPout_aux
VCCcp_main
10
19
VCCcp_aux
CPout_main
11
18
LD/PSaux
GNDcp_main
12
17
GNDxtal
Xtalacgnd/OSC
13
16
VCCxtal
Xtalin/OSC
14
15
Xtalout/NC
C1412
Figure 2. SKY72301-22 Pinout, 28-Pin EP-TSSOP
(Top View)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Technical Description
The SKY72301-22 is a fractional-N frequency synthesizer using a
∆Σ modulation technique. The fractional-N implementation
provides low in-band noise by having a low division ratio and fast
frequency settling time. In addition, the SKY72301-22 provides
arbitrarily fine frequency resolution with a digital word, so that the
frequency synthesizer can be used to compensate for crystal
frequency drift in the RF transceiver.
38 to 537 are possible in fractional-N mode and from 32 to 543 in
integer-N mode.
Reference Frequency Oscillator
The SKY72301-22 has a self-contained, low-noise crystal
oscillator. This crystal oscillator is followed by the clock
generation circuitry that generates the required clock for the
programmable reference frequency dividers.
Serial Interface
Reference Frequency Dividers
The serial interface is a versatile three-wire interface consisting of
three pins: Clock (serial clock), Data (serial input), and CS (chip
select). It enables the SKY72301-22 to operate in a system where
one or multiple masters and slaves are present. To perform a
loopback test at start-up and to check the integrity of the board
and processor, the serial data is fed back to the master device
(e.g., a microcontroller or microprocessor unit) through a
programmable multiplexer. This facilitates hardware and software
debugging.
The crystal oscillator signal can be divided by a ratio of 1 to 32 to
create the reference frequencies for the phase detectors. The
SKY72301-22 has both a main and an auxiliary frequency
synthesizer, and provides independently configurable dividers of
the crystal oscillator frequency for both the main and auxiliary
phase detectors. The divide ratios are programmed by the
Reference Frequency Dividers Register.
Registers
There are ten 16-bit registers in the SKY72301-22. For more
information, see the Register Descriptions section of this
document.
Main and Auxiliary ∆Σ Modulators
The fractionality of the SKY72301-22 is accomplished by the use
of a proprietary, configurable 10-bit or 18-bit ∆Σ modulator for
the main synthesizer and 10-bit ∆Σ modulator for the auxiliary
synthesizer.
Main and Auxiliary Fractional Units
The SKY72301-22 provides fractionality through the use of main
and auxiliary ∆Σ modulators. The output from the modulators is
combined with the main and auxiliary divider ratios through their
respective fractional units.
NOTE: The divided crystal oscillator frequencies (which are the
internal reference frequencies), Fref_main and Fref_aux,
are referred to as the reference frequencies throughout
this document.
Phase Detectors and Charge Pumps
The SKY72301-22 uses a separate charge pump phase detector
for each synthesizer which provides a programmable gain, Kd,
from 31.25 to 1000 µA/2π radians in 32 steps programmed using
the Phase Detector/Charge Pumps Control Register.
Frequency Steering
When programmed for frequency power steering, the SKY7230122 has a circuit that helps the loop filter steer the VCO using the
LD/PSmain signal (pin 9). In this configuration, the LD/PSmain
signal can provide a more rapid acquisition.
When programmed for lock detection, internal frequency steering
is implemented and provides frequency acquisition times
comparable to conventional phase/frequency detectors.
VCO Prescalers
The VCO prescalers provide low-noise signal conditioning of the
VCO signals. They translate from an off-chip, single-ended or
differential signal to an on-chip differential Current Mode Logic
(CML) signal. The SKY72301-22 has independent main and
auxiliary VCO prescalers.
Lock Detection
Main and Auxiliary VCO Dividers
Power Down
The SKY72301-22 provides programmable dividers that control
the CML prescalers and supply the required signals to the charge
pump phase detectors. Programmable divide ratios ranging from
The SKY72301-22 supports a number of power-down modes
through the serial interface. For more information, see the
Register Descriptions section of this document.
When programmed for lock detection, the SKY72301-22 provides
an active low, pulsing open collector output using the LD/PSmain
signal (pin 9) to indicate the out-of-lock condition. When locked,
the LD/PSmain signal is tri-stated (high impedance).
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200706B • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • May 21, 2007
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Serial Interface Operation
Register Programming
The serial interface consists of three signals: Clock (pin 1), Data
(pin 27) and CS (pin 28). The Clock signal controls data on the two
serial data lines (Data and CS). The Data pin bits shift into a
temporary register on the rising edge of Clock. The CS line allows
individual selection transfers that synchronize and sample the
information of slave devices on the same bus.
Register programming equations, described in this section, use
the following variables and constants:
Nfractional
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (Fref) multiplying factor such that
the resulting frequency is equal to the desired VCO
frequency.
A serial transfer is initiated when a microcontroller or
microprocessor forces the CS line to a low state. This is followed
immediately by an address/data stream sent to the Data pin that
coincides with the rising edges of the clock presented on the
Clock line.
Ninteger
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (Fref) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the registers, 16 bits
of address or data must be presented to the Data line with the
LSB last while the CS signal is low. If the CS signal is low for
more than 16 clock cycles, only the last address or data bits are
used to load the registers.
Nreg
Nine-bit unsigned input value to the divider ranging
from 0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
divider
This constant equals 262144 when the ∆Σ modulator
is in 18-bit mode, and 1024 when the ∆Σ modulator is
in 10-bit mode.
Figure 3 functionally depicts how a serial transfer takes place.
dividend When in 18-bit mode, this is the 18-bit signed input
value to the ∆Σ modulator, ranging from
–131072 to +131071 and providing 262144 steps,
each step equal to Fdiv_ref/218 Hz.
If the CS signal is brought to a high state before the 13th Clock
edge, the bit stream is assumed to be modulation data samples.
In this case, it is assumed that no address bits are present and
that all the bits in the stream should be loaded into the
Modulation Data Register.
When in 10-bit mode, this is the 10-bit signed input
value to the ∆Σ modulator, ranging from
–512 to +511 and providing 1024 steps, each step
equal to Fdiv_ref/210 Hz.
FVCO
Desired VCO frequency (either Fvco_main or Fvco_aux).
Fdiv_ref
Divided reference frequency presented to the phase
detector (either Fref_main or Fref_aux).
Clock
Data
X
A3
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
CS
Last
C1413
Figure 3. Serial Transfer Timing Diagram
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Fractional-N Applications. The desired division ratio for the
main and auxiliary synthesizer is given by the following equation:
F VCO
N f rac tion al = -----------------F di v_r ef
where Nfractional must be between 37.5 and 537.5.
The value to be programmed by the Main or Auxiliary Divider
Register is given by the equation:
N r eg = R ound [ N fr actio nal ] – 32
NOTE: The Round function rounds the number to the nearest
integer.
When in fractional mode, allowed values for Nreg are from 6 to
505, inclusive.
The value to be programmed by either of the MSB/LSB Dividend
registers or the Auxiliary Dividend Register is given by the
following equation:
dividend = R ound [ divider × ( N f ra ctio nal – N reg – 32 ) ]
where the divider is either 1024 in 10-bit mode or 262144 in
18-bit mode. Therefore, the dividend is a signed binary value
either 10 or 18 bits long.
A sample calculation for an integer-N application is provided in
Figure 5.
Register Loading Order. In applications where the main
synthesizer is in 18-bit mode, the Main Dividend MSB Register
holds the 10 MSBs of the dividend and the Main Dividend LSB
Register holds the 8 LSBs of the dividend. The registers that
control the main synthesizer’s divide ratio are to be loaded in the
following order:
• Main Divider Register
• Main Dividend LSB Register
• Main Dividend MSB Register (at which point the new divide ratio
takes effect)
In applications where the main synthesizer is in 10-bit mode, the
Main Dividend Register holds the 10 bits of the dividend. The
registers that control the main synthesizer’s divide ratio are to be
loaded in the following order:
• Main Divider Register
• Main Dividend MSB Register (at which point the new divide ratio
takes effect)
For the auxiliary synthesizer, the Auxiliary Dividend Register holds
the 10 bits of the dividend. The registers that control the auxiliary
synthesizer’s divide ratio are to be loaded in the following order:
• Auxiliary Divider Register
NOTE: Because of the high fractionality of the SKY72301-22,
there is no practical need for any integer relationship
between the reference frequency and the channel spacing
or desired VCO frequencies.
Sample calculations for two fractional-N applications are provided
in Figure 4.
Integer-N Applications. The desired division ratio for the main or
auxiliary synthesizer is given by:
F VC O _m ai n
N i nt ege r = --------------------------F d iv _re f
where Ninteger is an integer number from 32 to 543.
The value to be programmed by the Main or Auxiliary Divider
Register is given by the following equation:
N r eg = F intege r – 32
• Auxiliary Dividend Register (at which point the new divide ratio
takes effect)
NOTE: When in integer mode, the new divide ratios take effect
when the Main or Auxiliary Divider Register is loaded.
Direct Digital Modulation
The high fractionality and small step size of the SKY72301-22
allow the VCO to be tuned to practically any frequency in the
VCO’s operating range. This allows direct digital modulation by
programming the different desired frequencies at precise
instants. Typically, the channel frequency is programmed by the
Main Divider and MSB/LSB Dividend registers, and the
instantaneous frequency offset from the carrier is programmed by
the Modulation Data Register.
The Modulation Data Register can be accessed in three ways as
defined in the following subsections.
When in integer mode, allowed values for Nreg are from 0 to 511
for both the main and auxiliary synthesizers.
NOTE: As with all integer-N synthesizers, the minimum step size
is related to the crystal frequency and reference frequency
division ratio.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Case 1: To achieve a desired Fvco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation
of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal
frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore:
Nfractional
=
Fvco_main
Fdiv_ref
= 902.4530
20
= 45.12265
The value to be programmed in the Main Divider Register is:
Nreg = Round[Nfractional] – 32
= Round[45.12265] – 32
= 45 – 32
= 13 (decimal)
= 000001101 (binary)
With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[262144 × (45.12265 – 13 – 32)]
= Round[262144 × (0.12265)]
= Round[32151.9616]
= 32152 (decimal)
= 000111110110011000 (binary)
where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the
Main Dividend Register.
Summary:
·
·
·
·
·
Main Divider Register = 0 0000 1101
Main Dividend Register, LSB = 1001 1000
Main Dividend Register, MSB = 00 0111 1101
The resulting main VCO frequency is 902.453 MHz
Step size is 76.3 Hz
Note: The frequency step size for this case is 20 MHz divided by 218, giving 76.3 Hz.
C1414
Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Case 2: To achieve a desired Fvco_main frequency of 917.7786 MHz using a crystal frequency of 19.2 MHz with operation
of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal
frequency does not require the internal division to be greater than 1, which makes Fdiv_ref = 19.2 MHz. Therefore:
Nfractional
=
Fvco_main
Fdiv_ref
= 917.7786
19.2
= 47.80097
The value to be programmed in the Main Divider Register is:
Nreg = Round[Nfractional] – 32
= Round[47.80087] – 32
= 48 – 32
= 16 (decimal)
= 000010000 (binary)
With the modulator in 10-bit mode, the value to be programmed in the Main Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[1024 × (47.80087 – 16 – 32)]
= Round[1024× (–0.1990312)]
= Round[–203.808]
= 204 (decimal)
= 1100110100 (binary)
where 11 0011 0100 is loaded in the MSB of the Main Dividend Register.
Summary:
·
·
·
·
Main Divider Register = 0 0001 0000
Main Dividend Register, MSB = 11 0011 0100
The resulting main VCO frequency is 917.775 MHz
Step size is 18.75 kHz
Note: The frequency step size for this case is 19.2 MHz divided by 210, giving 18.75 kHz.
C1415
Figure 4. Fractional-N Applications: Sample Calculation (2 of 2)
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Case 1: To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum
divide ratio is 32, the reference frequency (Fdiv_ref) must be a maximum of 12.5 MHz. Choosing a reference
frequency divide ratio of 2 provides a reference frequency of 8 MHz. Therefore:
Ninteger
=
Fvco_aux
Fdiv_ref
=
400
8
=
50
The value to be programmed in the Auxiliary Divider Register is:
Nreg = Ninteger – 32
= 50 – 32
= 18 (decimal)
= 000010010 (binary)
Summary:
· Auxiliary Divide Register = 0 0001 0010
C1416
Figure 5. Integer-N Applications: Sample Calculation
Normal Register Write. A normal 16-bit serial interface write
occurs when the CS signal is 16 clock cycles wide. The
corresponding 16-bit modulation data is simultaneously
presented to the Data pin. The content of the Modulation Data
Register is passed to the modulation unit at the next falling edge
of the divided main VCO frequency (Fpd_main).
Short CS Through Data Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented to the Data pin. The Data
pin is the default pin used to enter modulation data directly into
the Modulation Data Register with shortened CS strobes.
This method of data entry eliminates the register address
overhead on the serial interface. All serial interface bits are resynchronized internally at the reference oscillator frequency. The
content of the Modulation Data Register is passed to the
modulation unit at the next falling edge of the divided main VCO
frequency (Fpd_main).
Short CS Through Mod_in Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide and modulation data (2 to 12 bits) is
presented on the Mod_in pin, an alternate pin used to enter
modulation data directly into the Modulation Data Register with
shortened CS strobes. This mode is selected through the
Modulation Control Register.
This method of data entry also eliminates the register address
overhead on the serial interface and allows a different device than
the one controlling the channel selection to enter the modulation
data (e.g., a microcontroller for channel selection and a digital
signal processor for modulation data).
All serial interface bits are internally re-synchronized at the
reference oscillator frequency and the content of the Modulation
Data Register is passed to the modulation unit at the next falling
edge of the divided main VCO frequency (Fpd_main).
Modulation data samples in the Modulation Data Register can be
from 2 to 12 bits long, and enable the user to select how many
distinct frequency steps are to be used for the desired modulation
scheme.
The user can also control the frequency deviation through the
modulation data magnitude offset in the Modulation Control
Register. This allows shifting of the modulation data to
accomplish a 2m multiplication of frequency deviation.
NOTE: The programmable range of –0.5 to +0.5 of the main
∆Σ modulator can be exceeded up to the condition where
the sum of the dividend and the modulation data conform
to the following relationship:
-0.5625 ≤ ( N mod ≤ dividend ) ≤ +0.5625
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Table 1. SKY72301-22 Register Map
Address (Hex)
0
Register (Note 1)
Main Divider Register
Length (Bits)
Address (Bits)
12
4
1
Main Dividend MSB Register
12
4
2
Main Dividend LSB Register
12
4
3
Auxiliary Divider Register
12
4
4
Auxiliary Dividend Register
12
4
5
Reference Frequency Dividers Register
12
4
6
Phase Detector/Charge Pumps Control Register
12
4
7
Power Down/Multiplexer Output Select Control Register
12
4
8
Modulation Control Register
12
4
9
Modulation Data Register
12
4
—
Modulation Data Register (Note 2) — direct input
2 ≤ length ≤ 12 bits
0
Note 1: All registers are write only.
Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
When the sum of the dividend and modulation data lie outside this
range, the value of Ninteger must be changed.
• Main Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs
of the 18-bit dividend for the main synthesizer.
For a more detailed description of direct digital modulation
functionality, refer to the Skyworks Application Note, Direct Digital
Modulation Using the SKY72300, SKY72301-22, and SKY72302
Dual Synthesizers/PLLs (document number 101349).
• Main Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs
of the 18-bit dividend for the main synthesizer.
Register Descriptions
NOTE: When in 10-bit mode, the Main Dividend LSB Register is
not required.
Table 1 lists the 10 16-bit registes that are used to program the
SKY72301-22. All register writes are programmed address first,
followed directly with data. MSBs are entered first. On power-up,
all registers are reset to 0x000 except registers at address 0x0
and 0x3, which are set to 0x006.
Main Synthesizer Registers
The Main Divider Register contains the integer portion closest to
the desired fractional-N (or the integer-N) value minus 32 for the
main synthesizer. This register, in conjunction with the Main
Dividend MSB/LSB registers (which control the fraction offset
from –0.5 to +0.5), allows selection of a precise frequency. As
shown in Figure 6, the value to be loaded is:
• Main Synthesizer Divider Index = Nine-bit value for the integer
portion of the main synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
The Main Dividend MSB/LSB Registers control the fraction part of
the desired fractional-N value and allow an offset of –0.5 to + 0.5
to the main integer selected through the Main Divider Register. As
shown in Figures 7 and 8, values to be loaded are:
The Main Dividend MSB/LSB Register values are 2's complement
format.
Auxiliary Synthesizer Registers
The Auxiliary Divider Register contains the integer portion closest
to the desired fractional-N (or integer-N) value minus 32 for the
auxiliary synthesizer. This register, in conjunction with the
Auxiliary Dividend Register (which controls the fraction offset from
–0.5 to + 0.5) allows selection of a precise frequency. As shown
in Figure 9, the value to be loaded is:
• Auxiliary Synthesizer Divider Index = Nine-bit value for the
integer portion of the auxiliary synthesizer dividers. Valid values
for this register are from 6 to 505 (fractional-N) or from 0 to 511
(integer-N).
The Auxiliary Dividend Register controls the fraction part of the
desired fractional-N value and allows an offset of –0.5 to + 0.5 to
the auxiliary integer selected through the Auxiliary Divider
Register. As shown in Figure 10, the value to be loaded is:
• Auxiliary Synthesizer Dividend = Ten-bit value for the auxiliary
synthesizer dividend.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
A3
0
A2 A1
0
0
A0 11
0
X
10
9
8
X
X MSB
7
6
5
4
3
2
1
0
LSB
Main Synthesizer Divider Index
C1417
Figure 6. Main Divider Register (Write Only)
A3
0
A2 A1
0
0
A0 11
1
X
10
9
8
7
6
5
4
3
2
1
X MSB
0
LSB
Main Synthesizer Dividend (MSBs)
C1418
Figure 7. Main Dividend MSB Register (Write Only)
A3
0
A2 A1
0
1
A0 11
0
X
10
9
8
7
X
X
X MSB
6
5
4
3
2
1
0
LSB
Main Synthesizer Dividend (LSBs)
C1419
Figure 8. Main Dividend LSB Register (Write Only)
General Synthesizer Registers
The dual-programmable reference frequency dividers provide the
reference frequencies to the phase detectors by dividing the
crystal oscillator frequency. The lower five bits hold the reference
frequency divide index for the main phase detector. The next five
bits hold the reference frequency divide index for the auxiliary
phase detector. Divide ratios from 1 to 32 are possible for each
reference frequency divider (see Tables 2 and 3).
The Reference Frequency Dividers Register configures the dualprogrammable reference frequency dividers for the main and
auxiliary synthesizers. As shown in Figure 11, the values to be
loaded are:
• Main Reference Frequency Divider Index = Desired main
oscillator frequency division ratio – 1. Default value on powerup is 0, signifying that the reference frequency is not divided for
the main phase detector.
• Auxiliary Reference Frequency Divider Index = Desired auxiliary
oscillator frequency division ratio – 1. Default value on powerup is 0, signifying that the reference frequency is not divided for
the auxiliary phase detector.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
A3
0
A2 A1
0
1
A0 11
1
X
10
9
X
X MSB
8
7
6
5
4
3
2
1
0
LSB
Auxiliary Synthesizer Divider Index
C1420
Figure 9. Auxiliary Divider Register (Write Only)
A3
0
A2 A1
1
0
A0 11
0
X
10
9
8
7
6
5
4
X MSB
3
2
1
0
LSB
Auxiliary Synthesizer Dividend
C1421
Figure 10. Auxiliary Dividend Register (Write Only)
Table 2. Programming the Main Reference Frequency Divider
Decimal
Bit 4 (MSB)
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Reference Divider
Ratio
0
0
0
0
0
0
1
1
0
0
0
0
1
2
2
0
0
0
1
0
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31
1
1
1
1
1
32
Table 3. Programming the Auxiliary Reference Frequency Divider
Decimal
Bit 9 (MSB)
Bit 8
Bit 7
Bit 6
Bit 5 (LSB)
Reference Divider
Ratio
0
0
0
0
0
0
1
1
0
0
0
0
1
2
2
0
0
0
1
0
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31
1
1
1
1
1
32
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
A3
0
A2 A1
1
0
A0 11
1
X
10
9
8
7
6
5
4
3
2
1
0
X
Main Reference Frequency Divider Index
Auxiliary Reference Frequency Divider Index
C1422
Figure 11. Reference Frequency Dividers Register (Write Only)
A3
0
A2 A1
1
1
A0 11
10
9
8
7
6
5
4
3
2
1
0
0
Main Phase Detector Gain
Main Power Steering/Lock Detect Enable
Auxiliary Phase Detector Gain
Auxiliary Power Steering/Lock Detect Enable
C1423
Figure 12. Phase Detector/Charge Pumps Control Register (Write Only)
The Phase Detector/Charge Pumps Control Register allows control
of the gain for both phase detectors and configuration of the
LD/PSmain and LD/PSaux signals for frequency power steering or
lock detection. As shown in Figure 12, the values to be loaded
are:
• Main Phase Detector Gain = Five-bit value for programmable
main phase detector gain. Range is from 0 to 31 decimal for
31.25 to 1000 µA/2π radian, respectively.
• Main Power Steering Enable = One-bit flag to enable the
frequency power steering circuitry of the main phase detector.
When this bit is cleared, the LD/PSmain pin is configured to be
a lock detect, active-low, open collector pin. When this bit is
set, the LD/PSmain pin is configured to be a frequency power
steering pin and can be used to bypass the external main loop
filter to provide faster frequency acquisition.
• Auxiliary Phase Detector Gain = Five-bit value for
programmable auxiliary phase detector gain. Range is from 0 to
31 decimal for 31.25 to 1000 µA/2π radian, respectively.
• Auxiliary Power Steering Enable = One-bit flag to enable the
frequency power steering circuitry of the auxiliary phase
detector. When this bit is cleared, the LD/PSaux pin is
configured to be a lock detect, active-low, open collector pin.
When this bit is set, the LD/PSaux pin is configured to be a
frequency power steering pin and may be used to bypass the
external auxiliary loop filter to provide faster frequency
acquisition.
The Power Down/Multiplexer Output Select Control Register
allows control of the power-down modes, internal multiplexer
output, and main ∆Σ synthesizer fractionality. As shown in Figure
13, the values to be loaded are:
• Full Power-Down = One-bit flag to power down the SKY7230122 except for the reference oscillator and the serial interface.
When this bit is cleared, the SKY72301-22 is powered up. When
this bit is set, the SKY72301-22 is in full power-down mode
excluding the Mux_out signal.
• Main Synthesizer Power-Down = One-bit flag to power down
the main synthesizer. When this bit is cleared, the main
synthesizer is powered up. When this bit is set, the main
synthesizer is in power-down mode.
• Main Synthesizer Mode = One-bit flag to power down the main
synthesizer’s ∆Σ modulator and fractional unit to operate as an
integer-N synthesizer. When this bit is cleared, the main
synthesizer is in a fractional-N mode. When this bit is set, the
main synthesizer is in integer-N mode.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
A3
A2
A1
A0
11
10
0
1
1
1
X
X
9
8
MSB
7
6
5
4
3
2
1
0
LSB
Full Power Down
Main Synthesizer Power Down
Main Synthesizer Mode
Main Synthesizer ΔΣ Fractionality
Auxiliary Synthesizer Power Down
Auxiliary Synthesizer Mode
Multiplexer Output Selection
Mux_out Pin Tri-State Enable
C1424
Figure 13. Power Down/Multiplexer Output Select Control Register (Write Only)
Table 4. Multiplexer Output
Multiplexer Output Select
(Bit 8)
Multiplexer Output Select
(Bit 7)
Multiplexer Output Select
(Bit 6)
0
0
0
Reference Oscillator
0
0
1
Auxiliary Reference Frequency (Fref_aux)
0
1
0
Main Reference Frequency (Fref_main)
0
1
1
Auxiliary Phase Detector Frequency (Fpd_aux)
1
0
0
Main Phase Detector Frequency (Fpd_main)
1
0
1
Serial data out
1
1
0
Serial interface test output
1
1
1
Unused
• Main Synthesizer ∆Σ Fractionality = One-bit flag to configure
the size of the main ∆Σ modulator. This has a direct effect on
power consumption and on the level of fractionality and step
size. When this bit is cleared, the main ∆Σ modulator is 18-bit
with a fractionality of 218 and a step size of Fref_main/262144.
When this bit is set, the main ∆Σ modulator is 10-bit with a
fractionality of 210 and a step size of Fref_main/1024.
• Auxiliary Synthesizer Power Down = One-bit value to power
down the auxiliary synthesizer. When this bit is cleared, the
auxiliary synthesizer is powered up. When this bit is set, the
auxiliary synthesizer is in power-down mode.
• Auxiliary Synthesizer mode = One-bit value to power down the
auxiliary synthesizer’s ∆Σ modulator and fractional unit to
operate as an integer-N synthesizer. When this bit is cleared,
the auxiliary synthesizer is in fractional-N mode. When this bit is
set, the auxiliary synthesizer is in integer-N mode.
Multiplexer Output
(Mux_out)
NOTE: There are no special power-up sequences required for the
SKY72301-22.
• Multiplexer Output Selection = Three-bit value that selects
which internal signal is output to the Mux_out pin. Internal
signals available on this pin are the following:
− Reference Oscillator, Fref
− Main or auxiliary divided reference (post reference
frequency main or auxiliary dividers), Fref_main or Fref_aux
− Main or auxiliary phase detector frequency (post main and
auxiliary frequency dividers), Fpd_main or Fpd_aux
− Serial data out, for loop-back and test purposes
See Table 4 for more information.
• Mux_out Pin Tri-State Enable = One-bit flag to tri-state the
Mux_out pin. When this bit is cleared, the Mux_out pin is
enabled. When this bit is set, the Mux_out pin is tri-stated.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
A3
1
A2 A1
0
0
A0 11
0
10
X
9
8
7
6
5
4
X
3
2
1
0
0
0
0
0
Reserved Bits
Modulation Data Magnitude Offset
Modulation Data Input Select
Modulation Address Disable
C1425
Figure 14. Modulation Control Register (Write Only)
A3
1
A2 A1
0
0
A0 11
10
9
8
7
6
1 MSB
5
4
3
2
1
0
LSB
Modulation Data Bits
C1426
Figure 15. Modulation Data Register (Write Only)
The Modulation Control Register is used to configure the
modulation unit of the main synthesizer. The modulation unit adds
or subtracts a frequency offset to the selected center frequency at
which the main synthesizer operates. The size of the modulation
data sample, controlled by the duration of the CS signal, can be
from 2 to 12 bits wide, to provide from 4 to 4096 selectable
frequency offset steps.
The modulation data magnitude offset selects the magnitude
multiplier for the modulation data and can be from 0 to 8. As
shown in Figure 14, the values to be loaded are:
• Modulation Data Magnitude Offset = Four-bit value that
indicates the magnitude multiplier (m) for the modulation data
samples. Valid values range from 0 to 13, effectively providing a
2m multiplication of the modulation data sample.
• Modulation Data Input Select = One-bit flag to indicate the pin
on which modulation data samples are serially input when the
CS signal is between 2 and 12 bits long. When this bit is
cleared, modulation data samples are to be presented on the
Data pin. When this bit is set, modulation data samples are to
be presented on the Mod_in pin.
• Modulation Address Disable = One-bit flag to indicate the
presence of the address as modulation data samples are
presented on either the Mod_in or Data pins. When this bit is
cleared, the address is presented with the modulation data
samples (i.e., all transfers are 16 bits long). When this bit is set,
no address is presented with the modulation data samples (i.e.,
all transfers are 2 to 12 bits long).
The Modulation Data Register is used to load the modulation data
samples to the modulation unit. These values are transferred to
the modulation unit on the falling edge of Fpd_main where they are
passed to the main ∆Σ modulator at the selected magnitude
offset on the next falling edge of Fpd_main. Modulation Data register
values are 2's complement format. As shown in Figure 15, the
value to be loaded is:
• Modulation Data Bits = Modulation data samples that represent
the desired instantaneous frequency offset to the selected main
synthesizer frequency (selected channel) before being affected
by the modulation data magnitude offset.
Package and Handling Information
Since the device package is sensitive to moisture absorption, it is
baked and vacuum packed before shipping. Instructions on the
shipping container label regarding exposure to moisture after the
container seal is broken must be followed. Otherwise, problems
related to moisture absorption may occur when the part is
subjected to high temperature during solder assembly.
The SKY72301-22 is rated to Moisture Sensitivity Level 3 (MSL3)
at 260 °C. It can be used for lead or lead-free soldering.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format. For packaging details, refer to the Skyworks
Application Note, Tape and Reel, document number 101568.
operating conditions are specified in Table 7 and electrical
specifications are provided in Table 8.
Electrical and Mechanical Specifications
Electrostatic Discharge (ESD) Sensitivity
The SKY72301-22 is supplied as a 28-pin EP-TSSOP. The
exposed pad is located on the bottom side of the package and
must be connected to ground for proper operation. The exposed
pad should be soldered directly to the circuit board.
The SKY72301-22 is a static-sensitive electronic device. Do not
operate or store near strong electrostatic fields. Take proper ESD
precautions.
Figure 16 provides a schematic diagram for the SKY72301-22.
Figure 17 shows the package dimensions for the 28-pin
EP-TSSOP and Figure 18 provides the tape and reel dimensions.
Signal pin assignments and functional pin descriptions are
specified in Table 5. The absolute maximum ratings of the
SKY72301-22 are provided in Table 6. The recommended
Table 5. SKY72301-22 Signal Descriptions (1 of 2)
Pin #
Pin Name
Type
Description
1
Clock
Digital input
Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the
Data pin on the rising edge of Clock.
2
Mod_in
Digital input
Alternate serial modulation data input pin. Address bits are followed by data bits.
3
Mux_out
Digital output
Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main
or auxiliary divided VCO frequency, serial data out, or testability signals. This pin can be tri-stated from
the synthesizer registers.
4
VSUBdigital
5
GNDecl/cml (Note 1)
Power and ground
Emitter Coupled Logic (ECL)/Current Mode Logic (CML) ground.
6
VCCcml_main
(Note 1)
Power and ground
ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump.
–
Substrate isolation. Connect to ground.
7
Fvco_main
Input
Main VCO differential input.
8
Fvco_main
Input
Main VCO complimentary differential input.
9
LD/PSmain
Analog output
Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open
collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This
pin is configured using the Phase Detector/Charge Pumps Control Register.
10
VCCcp_main
(Note 1)
Power and ground
Main charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain
and charge pump.
11
CPout_main
Analog output
Main charge pump output. The gain of the main charge pump phase detector is controlled by the Phase
Detector/Charge Pumps Control Register.
12
GNDcp_main
(Note 1)
Power and ground
Main charge pump ground.
13
Xtalacgnd/OSC
Ground/input
Reference crystal AC ground or external oscillator differential input.
14
Xtalin/OSC
Input
Reference crystal input or external oscillator differential input.
15
Xtalout/NC
Input
Reference crystal output or no connect.
16
VCCxtal
Power and ground
Crystal oscillator ECL/CML, 3 V.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Table 5. SKY72301-22 Signal Descriptions (2 of 2)
Pin #
Pin Name
Type
Description
17
GNDxtal
Power and ground
Crystal oscillator ground.
18
LD/PSaux
Analog output
Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open
collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO.
This pin is configured using the Phase Detector/Charge Pumps Control Register.
19
VCCcp_aux (Note 1)
Power and ground
Auxiliary charge pump supply, 3 to 5 V. Removing power safely powers down the associated divider chain
and charge pump.
20
CPout_aux
Analog output
Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector is controlled by the
Phase Detector/Charge Pumps Control Register.
21
GNDcp_aux (Note 1)
Power and ground
Auxiliary charge pump ground.
22
Fvco_aux
Input
Auxiliary VCO complimentary differential input.
23
Fvco_aux
Input
Auxiliary VCO differential input.
24
VCCcml_aux
(Note 1)
Power and ground
ECL/CML, 3 V. Removing power safely powers down the associated divider chain and charge pump.
25
GNDdigital (Note 1)
Power and ground
Digital ground.
26
VCCdigital (Note 1)
Power and ground
Digital 3 V.
27
Data
Digital input
Serial address and data input pin. Address bits are followed by data bits.
28
CS
Digital input
Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock.
When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges
are ignored.
Note 1: Associated pairs of power and ground pins must be decoupled using 0.1 µF capacitors.
Table 6. Absolute Maximum Ratings
Parameter
Min
Max
Units
3.6
VDC
Maximum digital supply voltage
3.6
VDC
Maximum charge pump supply voltage
5.25
VDC
Maximum analog RF supply voltage
Storage temperature
–65
+150
°C
Operating temperature
–40
+85
°C
Note:
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal values.
Table 7. Recommended Operating Conditions
Parameter
Min
Max
Units
Analog RF supplies
2.7
3.3
VDC
Digital supply
2.7
3.3
VDC
Charge pump supplies
2.7
5.0
VDC
Operating temperature (TA)
–40
+85
°C
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Table 8. Electrical Characteristics (1 of 2)
(VDD = 3 V, TA = 25 °C, Unless Otherwise Noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Power Consumption
Total power consumption
Power-down current
PTOTAL
Charge pump currents of
200 µA. Both synthesizers
fractional,
FREF_MAIN = 20 MHz,
FREF_AUX = 1 MHz
33
mW
Auxiliary synthesizer
power down
23
mW
10 (Note 1)
µA
ICC-PWDN
Reference Oscillator
Reference oscillator frequency
FOSC
50
Oscillator sensitivity (as a buffer)
VOSC
AC coupled, single-ended
Frequency shift versus supply voltage
FSHIFT_SUPPLY
2.7 V ≤ VXTAL ≤ 3.3 V
Main synthesizer operating frequency
FVCO_MAIN
Sinusoidal, –40 °C to
+85 °C
Auxiliary synthesizer operating frequency
FVCO_AUX
RF input sensitivity
VVCO
RF input impedance
ZVCO_IN
Main fractional-N tuning step size
∆FSTEP_MAIN
Auxiliary fractional-N tuning step size
∆FSTEP_AUX
0.1
MHz
2.0
Vpp
±0.3
ppm
100 (Note 2)
1000
MHz
Sinusoidal, –40 °C to
+85 °C
100 (Note 2)
500
MHz
AC coupled, –40 °C to
+85 °C
50
250
mVpeak
VCOs
150 – j168 @
800 MHz
Ω
FREF_MAIN/218 or FREF_MAIN/210
Hz
FREF_AUX/2
10
Hz
Noise
Phase noise floor
Pnf
Measured inside the loop
bandwidth using 25 MHz
reference frequency,
–40 °C to +85 °C
FREF_MAIN
–40 °C to +85 °C
–130
+ 20 Log (N)
dBc/Hz
Phase Detectors and Charge Pumps
Main phase detector frequency
Auxiliary phase detector frequency
FREF_AUX
–40 °C to +85 °C
Charge pump output source current
ICP-SOURCE
VCP = 0.5 VCCCP
125
Charge pump output sink current
ICP-SINK
VCP = 0.5 VCCCP
–125
Charge pump accuracy
ICP-ACCURACY
Charge pump output voltage linearity range
ICP vs VCP
0.5 V ≤ VCP ≤ (VCCCP
– 0.5 V)
Charge pump current versus temperature
ICP vs T
Charge pump current versus voltage
ICP vs VCP
25
MHz
25
MHz
1000
µA
–1000
µA
±20
%
VCCCP – 400
mV
VCP = 0.5 VCCCP
–40 °C < T < +85 °C
5
%
0.5 V ≤ VCP ≤ (VCCCP
– 0.5 V)
8
%
GND + 400
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Table 8. Electrical Characteristics (2 of 2)
(VDD = 3 V, TA = 25 °C, Unless Otherwise Noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Digital Pins
High level input voltage
VIH
Low level input voltage
VIL
0.7 VDIGITAL
V
0.3 VDIGITAL
High level output voltage
VOH
IOH = –2 mA
Low level output voltage
VOL
IOL = +2 mA
VDIGITAL –0.2
V
V
GND + 0.2
V
100
MHz
Timing – Serial Interface
Clock frequency
fCLOCK
Data and CS set up time to Clock rising
tSU
3
ns
Data and CS hold time after Clock rising
tHOLD
0
ns
Note 1: A 5 V charge pump power supply (on pin 10 and/or pin 19) results in higher power-down leakage current.
Note 2: The minimum synthesizer frequency is 12 x FOSC, where FOSC is the frequency at the Xtalin/OSC pin.
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DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
To Microprocessor
RF Out Auxiliary
J1
3V
1
3
Mod_in
Data
Mux_out
VCCdigital
27
26
5
C3
1 nF
6
RF Out Main
J1
C5
7
1
4
3
3V
2
C7
8
R1
100 kΩ
3V
10
VCC
C11
1 nF
2
1
11
RFOUT
VCC
VT
3
GND
12
4
13
Main VCO
14
R4
C14
GNDecl/cml
VCCcml_aux
VCCcml_main
Fvco_aux
Fvco_main
Fvco_aux
Fvco_main
GNDcp_aux
LD/PSmain
CPout_aux
VCCcp_main
VCCcp_aux
LD/PSaux
CPout_main
GNDcp_main
GNDxtal
Xtalacgnd/OSC
VCCxtal
Xtalin/OSC
25
5
24
23
22
C4
2
Auxiliary
VCO
C6
4
21
VCC
VCC
GND
3
Xtalout/NC
20
3V
R2
C8
19
18
C9
R3
C10
1 nF
C12
3V
17
16
15
C17
1 nF
Auxiliary Synthesizer Loop Filter
External Pad
Connection to
Ground
C15
R5
C2
1 nF
1
9
Lock Detect
Main Output <
GNDdigital
GND
5
VSUBdigital
4
A
3V
4
C1
1 nF
3V
3
28
2
CS
VT
2
Clock
RFOUT
1
C16
100 pF
C17
C19
Y1
C18
Main Synthesizer Loop Filter
3V
R6
100 kΩ
Lock Detect
> Auxiliary Output
C1427
Figure 16. SKY72301-22 Application Schematic
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200706B • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • May 21, 2007
19
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
0.65 BSC
Pin 1
3.00
6.40 BSC
4.4 ± 0.10
0.25 +0.5/–0.6
9.70 BSC
3.50
Top View
Exposed Pad
Bottom View
0.90 ± 0.05
1.10
0.10 ± 0.05
0.60 ± 0.10
Side View
All measurements are in millimeters
C1428
Figure 17. SKY72301-22 28-Pin EP-TSSOP Package Dimensions
4.00 ± 0.10
8.00 ± 0.10
2.00 ± 0.05
1.50 ± 0.10
Pin #1
1.75 ± 0.10
A
16.00 +0.30/–0.10
B
7.50 ± 0.10
A
B
1.50 ± 0.25
3.96
0.318 ± 0.013
1.10
8o Max
7o Max
6.75 ± 0.10
9.95 ± 0.10
1.60 ± 0.10
Notes:
1.
2.
3.
4.
A
B
Carrier tape material: black conductive polystyrene
Cover tape material: transparent conductive PSA
Cover tape size: 13.3 mm width
All measurements are in millimeters
C1430
Figure 18. SKY72301-22 Tape and Reel Dimensions
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
20
May 21, 2007 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200706B
DATA SHEET • SKY72301-22 FREQUENCY SYNTHESIZER
Ordering Information
Model Name
SKY72301-22 1.0 GHz Frequency Synthesizer
Manufacturing Part Number
SKY72301-22 (Pb-free package)
Evaluation Kit Part Number
PH00-D102
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Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
200706B • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • May 21, 2007
21