SC2614 Complete DDR Power Solution With BF_CUT and PGOOD POWER MANAGEMENT Description Features The SC2614 is a fully integrated DDR power solution providing power for the VDDQ and the VTT rails. The SC2614 also completely adheres to the ACPI sleep state power requirements. A synchronous buck controller provides the high current of the VDDQ at high efficiency, while a linear sink/source regulator provides the termination voltage with 2 Amp Source/Sink capability . This approach makes the best trade-off between cost and performance. Additional logic and UVLOs complete the functionality of this single chip DDR power solution in compliance with S3 and S5 motherboard signals. A BF_CUT output signal prevents Back Feeding Input Rail during S3 while a PGOOD output signals correct voltage Rails. Uses Latched BF_Cut from Glue Chip to se The SC2614 is capable of sourcing up to 20A at the switcher output, and 2A at the VTT output. The MLP package provides excellent thermal impedance while keeping small footprint. VDDQ current limit as well as 3 independent thermal shutdown circuits assure safe operation under all fault conditions. quence the three regulators High efficiency (90%) switcher for VDDQ supplies 20 Amps Single chip solution complies fully with ACPI power sequencing Specifications 2 Amp VTT Source/Sink Capability High current gate drives Internal S3 state LDO for VDDQ UVLO on 5V and 12V Independent Thermal Shutdown for VDDQ and VTT Fast transient response 18 pin MLP package Applications Power Solution for DDR memory per Intel ® motherboard specification High speed data line termination Typical Application Circuit 10k 12V 0.1uF 10k 100uF 5V Cin 1uF 10k 5V STBY L 16 0.1uF 4 BF_CUT 5VCC 9 5VSBY TG 15 BF_CUT BG 14 10 PWRGD PGND 13 18 SS/EN VDDQSTBY 7 17 COMP VDDQIN 8 12 AGND FB 1 3 LGND VTT 6 VTTSNS THPAD VTT 5 11 PWRGD 12VCC 0.1uF 2 0.1uF Cout VTT 0.1uF 19 SC2614 Revision 6, July 2004 VDDQ 1 www.semtech.com SC2614 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Supply Voltage, 5VCC to AGND V5VCC 7 V Supply Voltage, 12VCC to AGND V12VCC 15 V Standby Input Voltage V5VSBY 7 V I/O 5VSTBY +0.3, AGND -0.3 V 0.3 V IO(VTT) +/ - 2 A Operating Ambient Temperature Range TA 0 to 70 o Operating Junction Temperature TJ 125 o Thermal Resistance Junction to Ambient * θJA 25 o Thermal Resistance Junction to Case * θJC 4 o TSTG -65 to 150 Inputs AGND to PGND or LGND VTT Output Current Storage Temperature Range C C C/W C/W o C TG/BG DC Voltage 12Vcc + 0.3, AGND -0.5 V TG/BG AC Voltage 12Vcc + 1.0, AGND -1.0 V 2 kV ESD Rating (Human Body Model) ESD * See Mounting Considerations. Electrical Characteristics Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Symbol Conditions Min Typ Max Units 5V Supply Voltage V5VCC 4.5 5 5.5 V 12V Supply Voltage V12VCC 10.8 12 13.2 V 5V Standby Voltage V5VSBY 4.5 5 5.5 V BF_CUT low 1.8 2.5 Quiescent Current IQ(5VSBY) BF_CUT High 3.5 5.0 mA BF_CUT Threshold TTL V 12VCC Under Voltage Lockout UVLO12VCC 7 8.2 10 V 5VCC Under Voltage Lockout UVLO5VCC 3.5 3.7 4 V Feedback Reference Feedback Current SS/EN Shutdown Threshold © 2004 Semtech Corp. VREF 1.25 IFB VFB = 1.25V 2 0.3 VEN(TH) 2 V uA V www.semtech.com SC2614 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless specified: TA = 25°C, 12VCC = 12V, 5VCC = 5V, 5VSBY = 5V. Parameter Symbol Conditions Min Typ Max Units Thermal Shutdown TJ-SHDN 150 o Thermal Shutdown Hysteresis TJ-HYST 10 o C C Switcher IVDDQ = 0A to 10A Load Regulation Oscillator Frequency fOSC Soft Start Current ISS 0.2 225 250 % 275 25 Duty Cycle 0 KHz uA 80 % 70 % Overcurrent Trip Voltage VTRIP % of VDDQ Setpoint Top Gate Rise Time TGR Gate capacitance = 4000pF 25 nS Top Gate Fall Time TGF Gate capacitance = 4000pF 25 nS Bottom Gate Rise Time BGR Gate capacitance = 4000pF 35 nS Bottom Gate Fall Time BGF Gate capacitance = 4000pF 35 nS 50 nS 0.8 mS 38 dB 5 MHz +/-60 uA VIN = 5V 19 dB IPWRGD = 1mA, sink 50 400 mV VPWRGD = 5V; BF_CUT = 0 0.1 2 uA Dead Time td Error Amplifier Transconductance gm Error Amplifier Gain @ DC AEA Error Amplifier Bandwidth GBW 50 20 RCOMP = open Error Amplifier Source/Sink Current Modulator Gain AM Power Good Low Power Good High Leakage 60 ST BY LDO Output Current IVDDQSTBY Load Regulation ∆V/∆I IVDDQ = 0A to 650mA 0.5 % ILIM BF_CUT = high, VTT floating 1 A VTT VVDDQ = 2.500V Current Limit 750 mA VT T LDO Output Voltage Source and Sink Currents Load Regulation IVTT ∆VTT/ ∆I Error Amplifier Gain AEA_VTT Current Limit VTTILIM © 2004 Semtech Corp. 1.235 1.250 1.265 +/-1.8 A IVTT =+1.8A to -1.8A BF_CUT = low 3 V +/ - 1 % 75 dB 3 A www.semtech.com SC2614 POWER MANAGEMENT Pin Configuration Ordering Information TOP VIEW FB 1 18 SS/EN VTTSNS 2 17 COMP LGND 3 16 12VCC 5VSBY 4 15 TG VTT 5 14 BG VTT 6 13 PGND VDDQSTBY 7 12 AGND VDDQIN 8 11 BF_CUT 5VCC 9 10 PWRGD Part Numbers P ackag e SC2614MLTR(1) MLP-18 Notes: (1) Only available in tape and reel packaging. A reel contains 3000 devices. (18 Pin MLP) Note: Pin19 is the thermal Pad on the bottom of the device Pin Descriptions Pin # Pin Name 1 FB 2 VTTSNS 3 LGND VTT return. Connect to point of load return. The trace connecting to this pin must be able to carry 2 Amps. 4 5V S B Y Bias supply for the chip. Connect to 5V standby. 5, 6 VTT 7 VDDQSTBY 8 VDDQIN 9 5V C C 10 PWRGD Switcher powergood and internal enable to VTT LDO. 11 BF_CUT This pin will enable the STBY LDO in S3. 12 AGND Analog ground. 13 PGND Gate drive return. Keep this pin close to bottom FET source. 14 BG Bottom gate drive. 15 TG Top gate drive. 16 12V C C Supply to the upper and lower gate drives. 17 COMP Compensation pin for the PWM transconductance amplifier. 18 SS/EN Soft start capacitor to GND. Pull low to disable. 19 TH_PAD © 2004 Semtech Corp. Pin Function Feedback for the STBY LDO and the switcher for VDDQ. VTT LDO feedback and remote sense input. Regulator output. Regulates to 1/2 VDDQ. Sources or sinks current. 2 Amp source capability. S3 VDDQ output. VDDQ power input to VTT LDO. Must carry 2 Amps. Supply to the lower gate drive. Internally Connected to AGND. 4 www.semtech.com SC2614 POWER MANAGEMENT Timing Diagram © 2004 Semtech Corp. 5 www.semtech.com SC2614 POWER MANAGEMENT Block Diagram © 2004 Semtech Corp. 6 www.semtech.com SC2614 POWER MANAGEMENT Typical Characteristics 100% 40 35 80% DUTY CYCLE (%) Gain (dB) 30 25 20 15 10 60% 40% 20% 5 0% 0 1E+3 10E+3 100E+3 1.2 1E+6 1.3 1.4 1.5 1.6 1.7 VCOMP (V) Frequency (Hz) VCOMP vs Duty Cycle Switching Section Error Amplifier Gain Vo Error (%) 0.0% -0.1% -0.2% 0.0 2.0 4.0 6.0 8.0 10.0 12.0 Io (A) VDDQ Load Regulation 1.0% VTT Error (%) 0.5% 0.0% -0.5% -1.0% -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 Io (A) VTT Load Regulation, Source and Sink © 2004 Semtech Corp. 7 www.semtech.com SC2614 POWER MANAGEMENT Evaluation Board Schematic R1 1K 12V J1 12V Q1 2N2222 R2 10k C14 100uF C15 0.1uF J3 5V 1500uF 1500uF 1500uF 1500uF C1 C4 J2 GND 5V C2 C5 J4 GND C3 1uF J5 5V STBY U1A SI4420 C16 J6 GND U2A R9 2.8uH 10k 10uF R3 2.2 L1A U4 SC2614 5VSBY 4 BF_CUT 11 PWRGD 10 1K J7 BF_CUT/S3 J11 PWR GD/S5 18 J12 SS/EN 17 12 R6 TBD 3 C10 2 C11 TBD 5VCC 5VSBY TG BF_CUT BG PWRGD SGND SS/EN VDDQSBY COMP VDDQIN AGND FB LGND VTTO 0.1uF VTTSN VTTO U3 SI4420 9 15 R4 2.2 14 J8 13 7 R5 10.0k/1% 8 J9 VDDQ J10 1 6 5 R7 10.0k/1% VTT J13 VTT C17 19 C12 12VCC THPAD 16 1500uF 1500uF 1500uF VDDQ C7 SI4420 C9 C6 C8 0.1uF J15 C13 TBD 0.1uF 330uF J14 GND J16 GND J17 J18 GND R8 10k 5VSBY JP2 MAN PS_ON 12V 1 2 J19 ATX M/B MOLEX 39-29-9202 Jumper Placed at factory 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3.3V 3.3V COM 5V COM 5V COM PWR_OK 5VSB 12V 3.3V -12V COM PS_ON COM COM COM -5V 5V 5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5V JP1 HEADER 20 Figure 2: Evaluation Board Schematic © 2004 Semtech Corp. 8 www.semtech.com SC2614 POWER MANAGEMENT Applications Information S3 and S5 States Description During S3 and S5 sleep states, The BF_CUT signal is pulled high (see the timing diagram). The operation of the VDDQ and VTT supplies is governed by the internal sequencing logic in strict adherence with intel TM specifications with regards to the BF_CUT sgnal. The timing diagram demonstrates the state of the controller, and each of the VDDQ and VTT supplies during S3 and S5 transitions. When S3 is low, the VDDQ supplies the “Suspend To RAM” current of 650 mA (max) to maintain the information in memory while in standby mode. The VTT termination voltage is not needed during this state, and is thus tri-stated. Once BF_CUT goes low, the VDDQ switcher recovers and takes control of the VDDQ supply voltage. The SS/EN pin must be pulled low and high again to restart the SC2614. This can be achieved by cycling the input supplies, 5V or 12V. The Semtech SC2614 DDR power supply controller is the latest and most complete, three in one, switching and linear regulator, providing the necessary functions to comply with S3 and S5 sleep state signals generated by the Desktop Computer Motherboards. The SC2614 uses the BF_CUT input signal which is generated externally on Intel P4 Motherboard glue chip to comply with the power sequencing requirements. Logically, the BF_CUT signal can be represented as: BF_CUT=S0 .NAND.P_OK Where S0 is the state of the operation, S0=high for S0 and Low for S3. P_OK is a signal generated by the Silverbox supply, indicating that all rails are within specification . The BF_CUT signal is inverted to drive a Back_Feed_Cut MOSFET. The Back_Feed_Cut MOSFET prevents current flow from the VDDq supply back to the 5V supply during S3 state (when BF_CUT is high). VDDQ supply and the VTT termination voltages are supplied to the Memory bus during S0 (normal operation). During S0, VDDQ is supplied via the Switching regulator, sourcing high output currents to the VDD bus which in turn sources the termination supply current. The SC2614 is capable of driving a 4000pf capacitor in 25ns (typical, top gate). This drive capability allows 15-20A DC load on the VDDQ supply. The VTT termination voltage is an internal sink/source linear regulator, which during S0 state receives its power from the VDDQ bus. It is capable of sourcing and sinking 2 Amps (max). The current limit on this pin is set to 3 Amps (typical). The current handling capacity of this pin depends upon the amount of heat the PC board can sink from the SC2614 thermal pad. (See mounting instructions). The PC board layout must take into consideration the high current paths, and ground returns for both the VDDQ and VTT supply pins. VTT, LGND, VDDQ, 5VCC and PGND traces must also be routed using wide traces to minimize power loss and heat in these traces, based on the current handling requirements. Initial Conditions With the S5 and S3 go high (BF_CUT goes low) for the first time, the VDDQ is supplied by the Switcher, thus removing the burden of charging the output capacitors via the linear VDDQ regulator. Back-feeding the Input Supply When in S3 state, VDDQ is supplied by the linear regulator and current can flow back from the VDDQ supply through the body diode of the Top switching MOSFET to the 5V supply in the Silver Box. Since the 5VCC is off during this state, this back flow of current in effect shorts out the VDDQ supply and is not desirable. The blocking MOSFET is driven from the inverted BF_CUT signal, as shown in figure 2 (Evaluation Board Schematic). When the gate voltage for this series MOSFET is low, the current can not flow from the VDDQ supply back into the input power source. Current Limit Current limit is implemented by sensing the VDDQ voltage If it falls to 60% off its nominal voltage, as sensed by the FB pin, the TG and BG pins are latched off and the switcher and the linear controllers are shutdown. To © 2004 Semtech Corp. 9 www.semtech.com SC2614 POWER MANAGEMENT Applications Information (Cont.) recover from the current limit condition, either the power rails, 5VCC /12VCC have to be recycled, or the SS/EN pin must be pulled low and released to restart switcher operation. Thermal Shutdown There are three independent Thermal Shutdown protection circuits in the SC2614: The VDDQ linear regulator, the VTT source regulator, and the VTT sink regulator. If any of the three regulators’ temperature rises above the threshold, that regulator will turn off independently, until the temperature falls below the thermal shutdown limit. Power Good An open collector output provides indication that the VDDq switcher is in regulation. This is accomplished by monitoring the SS/EN pin. When the voltage on this pin has risen above 1.0V, PGOOD goes high (open). When BF_CUT goes high (standby), the 5V and 12V rails go low, and the SS/EN also goes low. Subsequsntly, PWRGD will also go low, and stays low until the 5V and 12V rails are recycled and rise above their respective UVLO thresholds. The compensation network includes a resistor and a capacitor in series, which terminates from the output of the error amplifier to the ground. This device uses voltage mode control with input voltage feed forward. The peak-to-peak ramp voltage is proportional to the input voltage, which results in an excellent performance to reject input voltage variation. The PWM gain is inversion of the ramp amplitude, and this gain is given by: 1 G pwm V ramp where the ramp amplitude (peak-to-peak) is 0.55 volts when input voltage is 5 volts. The total control loop-gain can then be derived as follows: 1 s. R. C . T( s) T o . s. R. C 1 s. R c. C o L 1 s. R c. C o Ro 2 s . L. C o . 1 Rc Ro where ⎛ V bg ⎞ T o := G m⋅ G pwm ⋅ V in⋅ R⋅ ⎜ ⎝ Vo ⎠ The task here is to properly choose the compensation network for a nicely shaped loop-gain Bode plot. The following design procedures are recommended to accomplish the goal: Compensation Components Gpwm L EA R1 R Vbg 1.25Vdc Rc Vin (1) Calculate the corner frequency of the output filter: Ro Co C R2 F o := 1 2⋅ π⋅ L⋅ C o (2) Calculate the ESR zero frequency of the output filter capacitor: Fig. 1. SC2614 control model. 1 The control model of SC2614 can be depicted in Fig. 1. This model can also be used in Spice kind of simulator to generate loop gain Bode plots. The bandgap reference is 1.25 V and trimmed to +/-1% accuracy. The desired output voltage can be achieved by setting the resistive divider network, R1 and R2. (3) Check that the ESR zero frequency is not too high. The error amplifier is transconductance type with fixed gain of: 0.0008A ⋅ If this condition is not met, the compensation structure may not provide loop stability. The solution is to add some electrolytic capacitors to the output capacitor bank G m := © 2004 Semtech Corp. V F esr := 2⋅ π⋅ R c⋅ C o F esr < 10 F sw 5 www.semtech.com SC2614 POWER MANAGEMENT Applications Information (Cont.) to correct the output filter corner frequency and the ESR zero frequency. In some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. It is not recommended to use only high frequency multi-layer ceramic capacitors for output filter. V V I (4) Choose the loop gain cross over frequency (0 dB frequency). It is recommended that the crossover frequency is always less than one fifth of the switching frequency : F x_over ≤ 1 G pwm ⋅ V in⋅ G m ⎛ F esr ⎞ ⎛ F x_over ⎞ ⎛ V o ⎞ ⋅⎜ ⋅⎜ ⎝ F o ⎠ ⎝ F esr ⎠ ⎝ V bg ⎠ ⋅⎜ C R R or R := G pwm ⋅ V in⋅ G m ⎛ F o ⎞ ⎛ F x_over ⎞ ⎛ V o ⎞ ⋅⎜ ⋅⎜ ⎝ F esr ⎠ ⎝ F o ⎠ ⎝ V bg ⎠ ⋅⎜ := 20 A := 250 KHz o := 6600 µF c := 0.006 Ω 1 := 1.0 KΩ := 1.0 KΩ 2 Step 1. Output filter corner frequency Fo = 1.13 KHz Step 2. ESR zero frequency: Fesr = 4.019 KHz 2 1 := 2.5 V R when F o < F esr < F x_over o Step 3. Check the following condition: F esr < when F esr < F o < F x_over (5) The compensation capacitor is determined by choosing the compensator zero to be about one fifth of the output filter corner frequency: F zero C F o © 2004 Semtech Corp. 5 Step 4. Choose crossover frequency and calculate compensator R: Fx_over = 50 KHz 1 2 . π . R . F zero An example is given below to demonstrate the procedure introduced above. The parameters of the power supply are given as: F sw Which is satisfied in this case. 5 (6) The final step is to generate the Bode plot, either by using the simulation model in Fig. 1 or using the equations provided here with Mathcad. The phase margin can then be checked using the Bode plot. Usually, this design procedure ensures a healthy phase margin. := 5 V L := 3 µH 5 2 o sw F sw If the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. The resistor in the compensation network can then be calculated as: R := F in R = 43.197 KΩ Step 5. Calculate the compensator C: C = 16.287 nF Step 6. Generate Bode plot and check the phase margin. In this case, the phase margin is about 85°C that ensures the loop stability. Fig. 2 shows the Bode plot of the loop. 11 www.semtech.com SC2614 POWER MANAGEMENT Loop Gain Mag (dB) 100 mag ( i ) 50 0 50 10 100 3 1 . 10 4 1 . 10 5 1 . 10 6 1 . 10 Fi Loop Gain Phase (Degree) 0 45 phase ( i ) 90 135 180 10 100 3 1 . 10 4 1 . 10 5 1 . 10 6 1 . 10 Fi Fig. 2. Bode plot of the loop © 2004 Semtech Corp. 12 www.semtech.com SC2614 POWER MANAGEMENT Mounting Considerations Description Exposed Pad Stencil Design The MLP18 is a leadless package whose electrical connections are made by lands on the bottom surface of the component. These lands are soldered directly to the PC board. The MLP has an exposed die attach pad, which enhances the thermal and electrical characteristics enabling high power applications. Power handling capability of the MLP package is typically >2x the power of other common SMT packages, such as the TSSOP and SOIC packages. In order to take full advantage of this feature the exposed pad must be physically connected to the PCB substrate with solder. It is good practice to minimize the presence of voids within the exposed pad inter-connection. Total elimination is difficult but the design of the exposed pad stencil is important, a single slotted rectangular pattern is recommended. (If large exposed pads are screened with excessive solder, the device may “float”, thus causing a gap between the MLP terminal and the PCB land metalization.) The proposed stencil designs enables outgassing of the solder paste during reflow as well as controlling the finished solder thickness. Thermal Pad Via Design Thermal data for the MLP18 is based on a 4 layer PCB incorporating vias which act as the thermal path to other layers. (Ref: Jedec Specification JESD 51-5). Based on thermal performance, four-layer PCB’s with vias are recommended to effectively remove heat from the device. Vias should be 0.3mm diameter on a 1.2mm pitch, and should be plugged to prevent voids being formed between the exposed pad and PCB thermal pad due to solder escaping by capillary action. Plugging can be accomplished by “tenting” the via during the solder mask process. The via solder mask diameter should be 100µm larger than the via diameter. Two layer boards have less copper and thus typically require an increase in the PC board area for effective heatsinking. The copper area immdiately surrounding the thermal pad connection must not be interupted by routing traces. © 2004 Semtech Corp. 13 www.semtech.com SC2614 POWER MANAGEMENT Outline Drawing - MLP-18 TERMINAL 1 IDENTIFIER TOP VIEW TERMINAL 1 BOTTOM VIEW 1 CONTROLLING DIMENSIONS: MILLIMETERS © 2004 Semtech Corp. 14 www.semtech.com SC2614 POWER MANAGEMENT Land Pattern - MLP-18 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 © 2004 Semtech Corp. 15 www.semtech.com