Technical Note TN8000.02
XE8801A/05A Programming
TN8000.02
Technical Note
XE8801A/05A Programming
Rev 1 February 2006
www.semtech.com
1
Technical Note TN8000.02
XE8801A/05A Programming
Contents
1.
2.
3.
4.
4.1.
4.2.
4.3.
5.
5.1.
5.1.1.
5.1.2.
5.1.3.
5.2.
5.3.
5.4.
Introduction ............................................................................................................................................. 3
Abbreviations .......................................................................................................................................... 3
Physical programming interface. .......................................................................................................... 3
Programming parameters. ..................................................................................................................... 4
Operating conditions ................................................................................................................................. 4
Timing Parameters.................................................................................................................................... 4
Power-up and down sequences ............................................................................................................... 7
Programming the whole MTP array using default settings................................................................ 8
Programming sequences.......................................................................................................................... 9
Introduction ............................................................................................................................................... 9
Define constante ....................................................................................................................................... 9
Define macro............................................................................................................................................. 9
Programming the whole array................................................................................................................. 13
Error description...................................................................................................................................... 14
Checksum computing ............................................................................................................................. 15
Table 1: Abbreviation description ........................................................................................................................ 3
Table 2: Pins in flash programming mode and their functions ............................................................................ 3
Table 3: programming conditions ........................................................................................................................ 4
Table 4 Clock timing constraints.......................................................................................................................... 4
Table 5 high voltage pulses timing constraints.................................................................................................... 5
Table 6 Sequence description for the shift_signature and cycle_cr_ck .............................................................. 9
Table 7: programming errors ............................................................................................................................. 14
Figure 1: Top view in testmode .......................................................................................................................... 4
Figure 2 : Timing diagram for crck clock.............................................................................................................. 5
Figure 3 : Timing diagram for ptck clock.............................................................................................................. 5
Figure 4 : Timing diagram for ptck clock during the erase verify......................................................................... 5
Figure 5 : Timing diagram for shift_instruction .................................................................................................... 5
Figure 6 : Timing diagram write_cr_normal ......................................................................................................... 6
Figure 7 : Timing diagram write_cr ...................................................................................................................... 6
Figure 8 : Timing diagram for pulse_high_voltage, for (A) short and (B) long pulses......................................... 6
Figure 9 : Timing diagram for the read_fault ....................................................................................................... 6
Figure 10 : Timing diagram for the checksum ..................................................................................................... 7
Figure 11: Timing diagram for the lock_test ........................................................................................................ 7
Figure 12: Timing diagram for the power-on ....................................................................................................... 7
Figure 13: Timing diagram for the power-down................................................................................................... 7
Figure 14 : Complete programming flow chart .................................................................................................... 8
Figure 15 : Example of sequence for the shift_signature following by cycle_crck .............................................. 9
© Semtech 2006
www.semtech.com
2
Technical Note TN8000.02
XE8801A/05A Programming
1. Introduction
This document describes the programming flow of the XE8801/01A, and 05/05A products.
Firstly, the conditions and parameters are described. Then the programming flow will be given followed by the main
routines implemented, and finally the correct usage of both to obtain a correctly programmed and verified device.
2. Abbreviations
Table 1 shows the different abbreviations used in this document.
Abbreviation
name
MTP
Crck
Ptck
HV
Testck
Testin
Testout
Description
Multiple Time Programmable
Coolrisc clock
Peripheral test clock
High Voltage
serial clock for shift instruction
serial input for shift instruction
serial output for shift instruction
Table 1: Abbreviation description
3. Physical programming interface.
The CoolRisc must be in test mode to perform the programming. Table 2 shows the function of the pins used in this
test mode.
PAD name
Type
Vbat
Vss
RESET
Vreg
OscIn
OscOut
VPP
PortA(0)
PortA(1)
Power supply input
Power supply input
Digital input under Vbat
Power supply output
Digital input under Vbat
Digital input under Vbat
Power supply input
Digital input under Vbat
Digital input under Vbat
Digital output under
Vbat
PortB(0)
Function
prog mode
Vdd
Vss
Reset
Crck
Ptck
HV
Testin
Testck
Testout
in
value
Vdd
Vss
Vss
Vreg (capacitance = 1 uF)
Vss or Vdd
Vss or Vdd
Vdd or Vddt or Vddhigh
Vss or Vdd
Vss or Vdd
Vss or Vdd
Signal type
Static
Static
Static
dynamic
dynamic
dynamic
dynamic
dynamic
dynamic
Table 2: Pins in flash programming mode and their functions
The PortB(0) is used as serial output to check programming results.
Other input pins of the device should ideally be tied to either the Vdd or Vss potential. This prevents currents in
input buffers.
© Semtech 2006
www.semtech.com
3
Technical Note TN8000.02
XE8801A/05A Programming
crck
OscIn
Vbat
ptck
OscOut
Vreg
HV
VPP
testin
PortA(0)
testck
PortA(1)
testout
PortB(0)
VDD
RESET
1 uF
VssVreg*
Vss
XE88LCxx
VSS
* : VssVreg pin is only available on some packages.
Figure 1: top view in testmode
4. Programming parameters.
4.1.
OPERATING CONDITIONS
The VPP pad in program mode takes the value of Vdd or Vddt or Vddhigh following the programming state. (see
timing diagram in the chapter 4.2 Timing Parameters)
Table 3 specifies the programming conditions of the device.
parameter
Vdd
Vddt
VddHigh
VREG capacitance
Temperature
Min
4.5
Vdd+2.0
11.55
0.9
10
Max
5.5
Vdd+2.5
11.65
1.1
40
Unit
V
V
V
µF
Deg. Celcius
Remark
Iprog ≤ 30 mA
Typical = 25
Table 3: programming conditions
4.2.
TIMING PARAMETERS
This chapter describes the timing constraints for device programming. The Table 4 shows all clock timing
constraints and the Table 5 shows the high voltage pulses timing constraints.
Parameter
ta
tb
tr
tf
th
tl
tc
trfc
ttf
Description
Testin stable before rise of testck
Testin stable after rise of testck
Testck rise time
Testck fall time
Testck high
Testck low
Crck and ptck clock high/low
Crck and ptck clock rise/fall
Fast ptck clock during erase verify
min
50
50
max
10
10
125
125
800
115
10
125
unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4 Clock timing constraints
© Semtech 2006
www.semtech.com
4
Technical Note TN8000.02
XE8801A/05A Programming
Parameter
trh
tfh
tsh
tlh
Description
Rise time
Fall time
First short pulse duration
Next short pulse duration
Long pulse duration
min
0.5
0.5
9
64
0.45
max
3
3
11
77
0.55
unit
us
us
us
us
S
Table 5 high voltage pulses timing constraints
Figure 2 to Figure 11 show the timing diagrams related to the low-level macros described in 5.1.3.
trfc
trfc
vdd
vss
tc
tc
Figure 2 : Timing diagram for crck clock
trfc
trfc
vdd
vss
tc
tc
Figure 3 : Timing diagram for ptck clock
trfc
trfc
vdd
vss
ttf
ttf
ttf
ttf
Figure 4 : Timing diagram for ptck clock during the erase verify
testin
0
1
2
19
20
21
tb ta
testck
tf
tr
th
tl
Figure 5 : Timing diagram for shift_instruction
© Semtech 2006
www.semtech.com
5
Technical Note TN8000.02
XE8801A/05A Programming
testin
0
1
2
19
20
21
testck
crck
ptck
Figure 6 : Timing diagram write_cr_normal
testin
0
1
2
19
20
21
testck
crck
ptck
Figure 7 : Timing diagram write_cr
A)
B)
trh
vddhigh
tfh
vddhigh
tfh
trh
vdd
vdd
tlh
tsh
Figure 8 : Timing diagram for pulse_high_voltage, for (A) short and (B) long pulses
testin
testout
0
0
1 2
1 2
18 19 20 21
Check_testout
19 20 21
0
0
1 2
1 2
18 19 20 21
19 20 21
0
0
1 2
1 2
18 19 20 21
19 20 21
testck
crck
Figure 9 : Timing diagram for the read_fault
© Semtech 2006
www.semtech.com
6
Technical Note TN8000.02
XE8801A/05A Programming
testin
Check_testout
21 20 19
testout
2
1 0
testck
crck
shift_signature
Figure 10 : Timing diagram for the checksum
Vddt
Vdd
HV
crck
testin
0 1
2
19 20 21
testck
Figure 11: Timing diagram for the lock_test
4.3.
POWER-UP AND DOWN SEQUENCES
Figure 12 and Figure 13 show the the timing diagrams related to the low-level macros power-on and power-down
described in 5.1.3
Vdd
Vbat
Vddt
HV
crck
testck
100 ms
Figure 12: Timing diagram for the power-on
Vbat
HV
Vdd
Vdd
crck
10 ms
testck
Figure 13: Timing diagram for the power-down
© Semtech 2006
www.semtech.com
7
Technical Note TN8000.02
XE8801A/05A Programming
5. PROGRAMMING THE WHOLE MTP ARRAY USING DEFAULT SETTINGS
The programming process of the whole flash array using default settings runs as follows (check algorithm at the
end of this chapter for detailed operation and up-to-date algorithm):
1.
2.
3.
4.
5.
6.
The programming procedure starts with a chip power-on sequence. (see chapter 4.3)
The programmer locks the chip in test mode (see macro lock_test, chapter 5.1.3).
The programmer erases and prepares the chip to receive data (see macro erase, chapter 5.1.3).
The programmer writes the data in the device memory (see macro write_data, chapter 5.1.3).
The programmer stops and restarts with a chip power-down and power-on. (see chapter 4.3)
The programmer verifies the complete programming result with the checksum (see the checksum macro,
chapter 5.1.3).
7. The programming procedure finishes by power-down. (see chapter 4.3)
Full_programming
1. Power-on reset
2. Lock in test mode
3. Erase and prepare
MTP
4. Write and verify
data in MTP
5. Power-down
Power-on
6. Test signature
7. Power-down
Figure 14 : Complete programming flow chart
© Semtech 2006
www.semtech.com
8
Technical Note TN8000.02
XE8801A/05A Programming
5.1.
PROGRAMMING SEQUENCES
5.1.1.
Introduction
In the following meta language sequences, we use procedural macro definitions to describe the programming
algorithm. Basic ‘set’ pattern lines represent the values put on the crck, testck, testin, ptck and high_voltage lines.
Function ‘check_testout(x)’ is a comparison of testout pin with the parameter ‘x’. The variable ctrl2reg is a list of
values for programming registers during the writing of the data.
5.1.2.
Define constant
RegEEP
RegEEP1
RegEEP2
RegEEP3
=
=
=
=
0b00111000
0b00111001
0b00111010
0b00111011
ctrl2reg{0}
ctrl2reg{1}
ctrl2reg{2}
ctrl2reg{3}
ctrl2reg{4}
ctrl2regblk
=
=
=
=
=
=
11101111
11101101
11101110
11101100
11101000
10101000
5.1.3.
Define macro
Most timings are not expressed in the macros, only the sequences are described. Please refer to the timing
diagrams of chapter 4.2 for reference.
testin
testout
21
20
19
0
1
2
testck
a
b
c
d
e
g
f
h
i
j
k
l
m
n
crck
Figure 15 : Example of sequence for the shift_signature following by cycle_crck
Point
a
b
C
D
E
F
G
H
I
J
K
L
M
N
function
set(1 0 1 0 vdd) and check_testout
set(1 1 1 0 vdd)
set(1 0 1 0 vdd) and check_testout
set(1 1 1 0 vdd)
set(1 0 1 0 vdd) and check_testout
set(1 1 1 0 vdd)
set(1 0 1 0 vdd) and check_testout
set(1 1 1 0 vdd)
set(1 0 1 0 vdd) and check_testout
set(1 1 1 0 vdd)
set(1 0 1 0 vdd) and check_testout
set(1 1 1 0 vdd)
set(0 1 1 0 vdd)
set(1 1 1 0 vdd)
Description
set to vss testck and read testout (signature [21])
set to vdd testck
set to vss testck and read testout (signature [20])
set to vdd testck
set to vss testck and read testout (signature [19])
set to vdd testck
set to vss testck and read testout (signature [2])
set to vdd testck
set to vss testck and read testout (signature [1])
set to vdd testck
set to vss testck and read testout (signature [0])
set to vdd testck
set to vss crck
set to vdd crck
Table 6 Sequence description for the shift_signature and cycle_cr_ck
macro set(crck; testck; testin; ptck; vpp)
© Semtech 2006
www.semtech.com
9
Technical Note TN8000.02
XE8801A/05A Programming
sets the corresponding pin to Vss if value is 0 or Vdd if value is 1. For the crck,
testck, testin, and ptck signals.
Sets the Vpp pin to the specified value (either Vdd, Vddt or VddHigh.
macro wait(value)
Waits for the specified time with all input signals frozen in their current state.
macro check_testout(status)
returns 0 or 1 depending on the testout line potential
0 means an error, the value read on testout is not the same that the value of
status(status is 0 and potential on testout is vdd or status is 1 and potential on
testout is vss)
1 means no error(status is 0 and potential is vss or status is 1 and potential is vdd)
macro cycle_crck(nbcycles)
repeat nbcycles
set(0 1 0 0 vdd)
set(1 1 0 0 vdd)
end repeat
end macro
; Toggle CoolRISC clock nbcycles times
macro cycle_ptck(nbcycles)
repeat nbcycles
set(1 1 0 1 vdd)
set(1 1 0 0 vdd)
end repeat
end macro
;Toggle periperal test clock nbcycles times
macro cycle_crck_ptck(nbcycles)
times
repeat nbcycles
set(0 1 0 0 vdd)
set(0 1 0 1 vdd)
set(1 1 0 0 vdd)
end repeat
end macro
;Toggle CoolRISC clock and periperal test clock nbcycles
macro shift_instruction(inst(21:0)) ; Repeat shift bit to input full
for index=0 to 21 ; 22 bits intruction
set(1 0 inst(index) 0 vdd)
set(1 1 inst(index) 0 vdd)
end for
end macro shift_instruction
macro write_cr (address(7:0), data(7:0))
shift_instruction(000000 not(data) not(address))
cycle_crck_ptck(1)
end macro
macro write_cr_normal (address(7:0), data(7:0))
shift_instruction(000000 not(data) not(address))
cycle_crck(1)
end macro
function read_fault (address(7:0)) ; returns 0 or 1
define test_result: boolean (0 or 1)
shift_instruction(00010010101110 not(address))
cycle_crck(1)
test_result = check_testout(0)
shift_instruction(00010010101110 not(address))
cycle_crck(1)
shift_instruction(00010010101110 not(address))
cycle_crck(1)
return(test_result)
end macro
macro lock_test
; Got to test mode, then lock it
define inst: instruction (22 bits wide) ; set Vpp to Vddt
© Semtech 2006
www.semtech.com
10
Technical Note TN8000.02
XE8801A/05A Programming
repeat 5
set(0 1 0 0 vddt)
set(1 1 0 0 vddt)
end repeat
inst=(000000 not(0x80) not(0x19))
for index=0 to 21 ; 22 bits intruction
set(1 0 inst(index) 0 vddt)
set(1 1 inst(index) 0 vddt)
end for
set(0 1 0 0 vddt)
set(1 1 0 0 vddt)
set(1 1 0 0 vdd) ; set Vpp to Vdd
end macro
macro shift_signature
for index=21 to 0
set(1 0 1 0 vdd)
signature(index)=check_testout(1)
set(1 1 1 0 vdd)
end for
; signature(index) = testout
if signature is not equal at the expected value given by programmer, then device is
defective, see chapter 5.3 Error4
end macro
macro signature
shift_instruction(1111111111111111111111)
cycle_crck(1)
shift_signature
cycle_crck(1)
end macro
macro checksum
shift_instruction(1110100000000000000001)
cycle_crck(1)
shift_instruction(0010111110111111111111)
cycle_crck(1)
shift_instruction(1111111111111111111111)
cycle_crck(1)
for address = 0 to 8191
if check_testout(0) then jump to signature
shift_instruction(1111111111111111111111)
cycle_crck(1)
end for
signature
end macro
macro pulse_high_voltage (duration) ; Put high voltage on VPP
set(1 1 0 0 vddhigh)
wait(duration)
set(1 1 0 0 vdd)
end macro
macro wait_cr_short
define inst: short instruction (9 bits wide)
inst = (000100101)
for index=0 to 8 ; 9 bits
set(1 0 inst(index) 0 vdd)
set(1 1 inst(index) 0 vdd)
end for
cycle_crck(1)
end macro
© Semtech 2006
www.semtech.com
11
Technical Note TN8000.02
XE8801A/05A Programming
macro erase
define ok : boolean (0=false, 1=true)
erase_again:
write_cr_normal (0x1D, 00110000)
wait(100 ms)
write_cr(RegEEP, 00001000)
write_cr(RegEEP2, 00000000)
write_cr(RegEEP2, 00000000)
write_cr(RegEEP3, 00000000)
write_cr(RegEEP3, 00000000)
write_cr(RegEEP3, 00000000)
write_cr_normal(RegEEP1, ctrl2reg{4})
write_cr(RegEEP1, ctrl2reg{4})
wait_cr_short
cycle_ptck(1)
pulse_high_voltage(500 ms)
;tlh parameter
cycle_ptck(2)
pulse_high_voltage(500 ms)
;tlh parameter
write_blocking:
write_cr_normal(RegEEP1,ctrl2regblk)
write_cr(RegEEP1,ctrl2regblk)
write_cr(RegEEP,00001110)
wait_cr_short
cycle_ptck(1)
for address = 0 to 8191
write_cr(RegEEP2, address_LSB)
write_cr(RegEEP2, address_MSB)
wait_cr_short
for counter = 0 to 3
cycle_ptck(1)
pulse_high_voltage(70 us)
cycle_ptck(4)
end for
end for
; write blocking bits
; parameter tsh (always long tsh)
ok = read_fault(RegEEP)
; check error bit
if (not ok) then jump to write_blocking ; *** If not successful in 12 times,
device is defective, see chapter 5.3 Error1
***
write_cr_normal(0x1D, 00100000)
wait(500 ms)
write_cr(RegEEP,00000010)
for address = 0 to 8191
write_cr(RegEEP2, address_LSB)
write_cr(RegEEP2, address_MSB)
wait_cr_short
cycle_ptck(2)
; check blocking bits
; must be realised with ttf timing
; see Table 4 and Figure 4
end for
ok = read_fault(RegEEP)
if (not ok) then jump to erase_again
; check error bit
; *** If not successful in 3 times,
device
is defective, see chapter 5.3 Error2 ***
end macro
© Semtech 2006
www.semtech.com
12
Technical Note TN8000.02
XE8801A/05A Programming
macro write_data
define ok : boolean (0=false, 1=true)
data_load:
write_cr_normal(0x1D, 00110000)
wait(100 ms)
; 100 ms
data_again:
write_cr(RegEEP, 01100000)
write_cr_normal(RegEEP1,ctrl2reg{0})
write_cr(RegEEP1,ctrl2reg{0})
for address = 0 to 8191
; write instructions in memory
write_cr(RegEEP2, address[7..0])
write_cr(RegEEP2, address[15..8])
write_cr(RegEEP3, instruction_data(address)[7..0])
write_cr(RegEEP3, instruction_data(address)[15..8])
write_cr(RegEEP3, 00 instruction_data(address)[21..16])
for counter = 0 to 7
if counter < 5
write_cr(RegEEP1,ctrl2reg{counter})
wait_cr_short
end if
cycle_ptck(1)
if counter = 0
pulse_high_voltage(10 us) ; parameter tsh (short tsh)
else
pulse_high_voltage(70 us) ; parameter tsh (long tsh)
end if
cycle_ptck(4)
end for
end for
ok = read_fault(RegEEP)
; check error bit
if (not ok) then jump to data_again ; *** If not successful in 3 times, ignore
error bit and quit macro ***
end macro
macro test_signature
lock_test
checksum
end macro
5.2.
PROGRAMMING THE WHOLE ARRAY
This part describes the full sequence needed to programme the device by using the macro instruction.
sequence full_programming
power-on
; power-on the IC
lock_test
; initialize programming mode
erase
; erase and prepare device
write_data
; write and verify data
power-down
power-on
; power-on the IC
test_signature
power-down
end sequence
© Semtech 2006
www.semtech.com
13
Technical Note TN8000.02
XE8801A/05A Programming
5.3.
ERROR DESCRIPTION
Table 7 shows the different errors that arrive in the full programming sequence.
Error No
Error1
Error2
Error4
Source macro
erase
erase
checksum
Description
Data erase is incorrect (error type 1)
Data erase is incorrect (error type 2)
Checksum is incorrect after programming
Comment
Table 7: programming errors
© Semtech 2006
www.semtech.com
14
Technical Note TN8000.02
XE8801A/05A Programming
5.4.
CHECKSUM COMPUTING
This chapter shows the C program that calculates the signature to be compared with the result of the
shift_signature macro.
#include
#include
#include
#include
<stdio.h>
<math.h>
<stdlib.h>
<string.h>
FILE *f_ptr;
long int bist;
// Contains the CheckSum
void XmxCheckSum (long data){
int j;
long int sum, bist17, bist6, data_lsb, bist_lsb;
for (j = 0; j < 22; j++){
// invert the incomming bit
// data starts from lsb to msb
// data % 2 = data modulo 2 = Division reminder (data/2)
if (data % 2 == 0)
data_lsb = 1;
else
data_lsb = 0;
bist17 = (bist >> 17) % 2;
bist6 = (bist >> 6) % 2;
bist = bist * 2; // shift left
bist = bist % (1 << 18);
// just keep remainder
sum= bist17 + bist6 + data_lsb;
// XOR function
if ((sum == 1) + (sum == 3)) {
bist_lsb = 1;
}
else {
bist_lsb = 0;
}
bist = bist + bist_lsb;
data = data / 2;
}
}
int main(int argc, char *argv[]){
int i;
long int address, data;
if(argc == 2){
f_ptr = fopen(argv[1], "r");
if(f_ptr == NULL) {
perror("File Read or Write error");
exit(1);
}
data = 0;
bist = 0;
XmxCheckSum(data);
while (fscanf(f_ptr, "%x %x", &address, &data) == 2){
XmxCheckSum(data);
}
printf(“ The program signature is (in hexa) : 0x%x \n”, bist);
fclose(f_ptr);
}
else{
printf(“ SYNTAX ERROR : XE8000CheckSum filename \n”);
exit(1);
}
return 0;
}
© Semtech 2006
www.semtech.com
15
Technical Note TN8000.02
XE8801A/05A Programming
© Semtech 2006
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech. assumes no
responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation,
repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH
PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK.
Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and
hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and
attorney fees which could arise.
Contact Information
Semtech Corporation
Wireless and Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone (805) 498-2111 Fax : (805) 498-3804
© Semtech 2006
www.semtech.com
16