AN10923 1.5 GHz Doherty power amplifier for base station applications using the BLF6G15L-250PBRN Rev. 1 — 14 March 2011 Application note Document information Info Content Keywords RF power transistor, Doherty architecture, LDMOS, Power amplifier, W-CDMA, LTE, Base station, BLF6G15L-250PBRN Abstract This application note describes the design and performance of a power amplifier for 1.5GHz 3GPP E-UTRA LTE base stations using two BLF6G15L-250PBRN LDMOS power transistors in Doherty architecture AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN Revision history Rev Date Description v.1 20110314 initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 2 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 1. Introduction This application note describes the design and performance of a Doherty power amplifier optimized for use in 1.5 GHz 3GPP E-UTRA LTE base stations applications. The amplifier design, characteristics and the test methods used to determine the RF performance are also described. The amplifier uses two BLF6G15L-250PBRN LDMOS power transistors in a Doherty architecture. The design ensures high efficiency while providing a peak power capability very similar to two parallel Class AB amplifiers. The input and output sections are internally matched, giving high gain with good gain flatness and phase linearity over a wide frequency band. The BLF6G15L-250PBRN transistor is a sixth generation device using NXP Semiconductors’ advanced LDMOS process. 2. Circuit description The 1.5 GHz Doherty power amplifier employing two BLF6G15L-250PBRN power transistors is shown in the photograph of Figure 1. The main amplifier is biased to operate in Class-AB mode and the peak amplifier is biased to operate in Class-C mode. The input signal is split by a 3 dB power divider and fed to each amplifier with a 90 degree phase difference. The amplified signals are recombined at the output with a power combiner. Both amplifiers operate when the input signal peaks, and each is presented with the load impedance that enables maximum output power. If the input signal amplitude drops below a preset threshold level, the Class-C peaking amplifier turns off and only the Class-AB remains active. At these lower power levels the Class-AB main amplifier is presented with higher load impedance that enables higher efficiency and gain. The result is an extremely efficient solution for amplifying the complex modulation schemes employed in current and emerging wireless systems. AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 3 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 019aab216 Fig 1. Photograph of the BLF6G15L-250PBRN Doherty power amplifier 3. Design and Tuning The two-way symmetrical Doherty amplifier comprising a main amplifier and a peak amplifier, input phase splitter and power combiner was designed and optimized using the following target specification: • Frequency band 1476 MHz to 1511 MHz • 2-carrier W-CDMA 3 GPP, 64 DPCH, PAR = 7.5 dB at 0.01% probability per carrier, 5 MHz carrier spacing • • • • AN10923 Application note Drain-source voltage (VDS) = 32 V PL(3db) = 58 dBm PL(AV) = 49 dBm Linear gain = 15 dB All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 4 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN • • • • • Gain ripple 0.5 dB RLin 15 dB ACPR at 5 MHz offset and PL(AV) = −30 dBc Efficiency at PL(AV) = 36 % PCB material RO4350 30 mils The description of the design of the single stage (Class-AB) amplifier is given in Section 3.1, and the description of the Doherty design is given in Section 3.2. 3.1 Design of the single stage amplifiers The design began with calculation of the input and output requirements of a single stage amplifier working in Class-AB matched to 50 Ω (main amplifier). Table 1 gives the typical source and load impedances used in the matching circuit of the single stage amplifier. The peak amplifier uses the same input and output matching design as the main amplifier. The only difference between the two amplifiers is in the bias conditions. The main amplifier is biased in Class-AB with IDq current of 1450 mA while the peak amplifier is biased in Class-C with VGS of 0.4V. Table 1. Typical impedance per section Frequency (GHz) ZS (Ω) ZL (Ω) 1.48 1.12 - j2.80 1.67 - j3.33 1.51 1.32 - j2.79 1.59 - j3.73 drain ZL gate ZS 001aaf059 Fig 2. Definition of transistor impedance 3.2 Doherty design For Doherty operation, the output-matching network of the main amplifier should also have the property of an impedance inverter. In order to achieve this a 50 Ω stripline is added to the output matching circuit. The peak amplifier in inactive mode has finite off-state impedance and will therefore absorb power from the main amplifier. This loss is minimized by inserting a 50 Ω stripline whose length is chosen for the maximum impedance at the combining point of the power combiner when the peak amplifier is in off-state. In order to get maximum output power from the Doherty amplifier it is necessary to provide the correct input drive level and phase to the peak and main amplifiers. Because the main and the peak amplifiers have similar gains, a symmetrical 3 dB, 90 degrees phase difference hybrid coupler is used to split the signal at the input. AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 5 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN It is essential that the signals from the main and peak amplifiers arrive in phase at the combining point of the power combiner. The phase difference introduced by the length of impedance inverter stripline and the off-state maximum impedance stripline therefore needs to be compensated for at the input. The phase difference caused by the different classes of operation is very small and can be ignored. The drain bias line is one of the strongest contributors to the memory effects by the amplifiers. Making the bias line as short as possible will have a positive effect on the memory performance. In order to further reduce the drain video impedance, two parallel bias lines are placed symmetrically on both sides of every transistor. 3.3 Tuning Adjusting the bias of the peak amplifier can further optimize the back-off efficiency of the Doherty amplifier, however this will be at the cost of linearity. Another way to optimize linearity is by adjusting the input phase shift while monitoring the AM-AM and AM-PM characteristics. This however will be at the cost of peak power and peak efficiency. 3.4 Transistor biasing There are two ways to bias the BLF6G15-250PBRN transistor. The first is standard bias without using the sense FETs integrated in the package. In this case the sense FET leads can be removed and the bias can be applied directly to the power transistor(s) (see Section 5 “Appendix A: PCB layout and bill of materials (no auto bias)”. The second way of biasing is by using the sense leads. An auto bias circuit is required to provide a fixed IDq to the main RF FET. The FET is biased by a sense transistor mounted in the same package which is used as a current mirror. Details of the circuit and layout are given in Section 6 “Appendix B: PCB layout and bill of materials with auto bias”, Figure 12 and Figure 13. The peak amplifier operates in Class-C and has a fixed gate-source voltage of 0.4 V. 4. Test results 4.1 Network analyzer frequency sweep The network analyzer frequency sweep measurement results for the Doherty test board are shown in Figure 3. The test conditions were as follows: • • • • AN10923 Application note PL= 49 dBm VDS = 32 V IDq (main) = 1450 mA VGS = 0.4 V (peak amplifier) All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 6 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 019aaa257 19 Gp (dB) f = 1.476 GHz f = 1.511 GHz −4 IRL (dB) −8 17 (1) (3) −12 15 (2) −16 13 11 1.45 1.47 1.49 −20 1.53 1.51 f (GHz) (1) Power gain in band of operation: minimum 16.3 dB (2) Input return loss in band of operation: maximum −14 dB (3) Gain ripple in band of operation: maximum 0.3 dB Fig 3. Power gain and input return loss as functions of frequency 4.2 Large signal power sweeps 4.2.1 CW network analyzer power sweep (AM-AM and AM-PM) The network analyzer measurement results for the test board are shown in Figure 4 and Figure 5. The test conditions were as follows: • • • • AN10923 Application note VDS = 32 V IDq (main) = 1450 mA VGS = 0.4 V (peak amplifier) Network analyzer sweep time = 27.1 ms All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 7 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 019aaa258 20 G (dB) (3) 18 (2) (1) 16 PL(3dB) 14 12 43 47 51 55 59 PL (dBm) (1) f = 1476 MHz; P3db minimum 58 dBm (2) f = 1494 MHz; P3db minimum 58 dBm (3) f = 1511 MHz; P3db minimum 58 dBm Fig 4. Network analyzer gain power sweep (AM-AM) 019aaa259 45 ϕ (deg) (1) Δ1 25 (2) Δ2 5 (3) Δ3 −15 −35 43 47 51 55 59 PL (dBm) (1) f = 1476 MHz; AM-PM compression at P3dB maximum 15 degrees (2) f = 1494 MHz; AM-PM compression at P3dB maximum 15 degrees (3) f = 1511 MHz; AM-PM compression at P3dB maximum 15 degrees Fig 5. Network analyzer phase power sweep (AM-PM) 4.2.2 2-tone W-CDMA The 2-carrier W-CDMA (5 MHz spacing) measurement results for the test board are shown in Figure 6 and Figure 7. The test conditions were as follows: • VDS = 32 V • IDq (main) = 1450 mA AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 8 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN • VGS = 0.4 V (peak amplifier) • 3 GPP, Test Model 1, 64 DPCH, PAR = 7.5 dB at 0.01% probability per carrier, 5 MHz carrier spacing 019aaa260 20 G (dB) η (%) (1) (2) (3) 18 (6) (5) (4) 50 40 16 30 PL = 49 dBm 14 20 12 10 38 42 46 50 54 PL (dBm) Efficiency at PL = 49 dBm minimum 36 % Gain at PL = 49 dBm minimum 16 dB (1) % efficiency at f = 1476 MHz (2) % efficiency at f = 1494 MHz (3) % efficiency at f = 1511 MHz (4) dB gain at f = 1476 MHz (5) dB gain at f = 1494 MHz (6) dB gain at f = 1511 MHz Fig 6. AN10923 Application note 2-carrier W-CDMA power sweep: gain as a function of output power All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 9 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 019aaa261 −28 ACPR (dBc) −32 −36 (1) (2) (3) −40 PL = 49 dBm (4) (5) (6) −44 38 42 46 50 54 PL (dBm) ACPR at PL = 49 dBm minimum 34 dBc (1) 5 MHz, ACPR Hi, dBc at 1476 MHz (2) 5 MHz, ACPR Lo, dBc at 1476 MHz (3) 5 MHz, ACPR Hi, dBc at 1494 MHz (4) 5 MHz, ACPR Lo, dBc at 1494 MHz (5) 5 MHz, ACPR Hi, dBc at 1511 MHz (6) 5 MHz, ACPR Lo, dBc at 1511 MHz Fig 7. 2-carrier W-CDMA power sweep: ACPR as a function of output power 4.3 Residual memory magnitude and phase surface plots large signal power sweeps The residual memory surface versus tone spacing and mean output power measurement results for the test board are shown in Figure 8. and Figure 9. The test conditions were as follows: • VDS = 32 V • IDq (main) = 1450 mA • VGS = 0.4 V (peak amplifier) AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 10 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 40 −30 −40 residual IM3 (dBc) −50 50 −60 60 −70 −80 70 −90 −100 50 80 48 46 50 44 mean output power (dBm) 40 42 30 40 38 10 36 20 modulation f (MHz) 90 0 019aaa262 Up to 25 MHz residual magnitude IM3 remains below −40 dBc at 49 dBm Fig 8. Residual memory magnitude surface 500 400 300 400 residual IM3 phase (°) 200 200 100 0 0 −200 −100 −400 50 −200 48 46 50 44 mean output power 42 (dBm) 40 −300 30 40 38 10 36 20 modulation f (MHz) 0 019aaa263 Phase plot is smooth, indication of good predistortability Fig 9. AN10923 Application note Residual memory phase surface All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 11 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 5. Appendix A: PCB layout and bill of materials (no auto bias) R3 R4 Q1 R5 R6 R2 L1 C2 C3 C8 C7 R1 C9 R7 C1 C6 R8 L2 R9 C5 C4 Q2 C10 C11 C12 R10 C13 C14 C15 R11 2 x BLF6G15L-250PBRN Input Rev 1 RO4350 30mils Q3 2 x BLF6G15L-250PBRN Output Rev 1 RO4350 30mils C18 C19 R12 C17 C16 Q4 C20 C21 C22 R14 R13 R16 C23 L4 R27 C30 C24 R15 C25 R17 R26 Q5 R18 C26 R20 L3 R19 R24 R21 R23 R22 C27 C32 C29 C28 C31 R25 019aaa280 Q6 Fig 10. Component layout for application circuit with no auto bias AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 12 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN Table 2. Parts list for application circuit (no auto bias) Component Value Description Manufacturer C1, C2, C25, C26 100 nF capacitor Murata GRM21BR71H104KA01L C3, C24, C27, C28 1 μF capacitor Murata GRM31MR71H105KA88L C4, C8, C12, C16, C22, C31 10 μF; 50 V capacitor Murata GRM32ER71H106KA12L C5, C6, C10, C11, C13, C14, C17, C18, C20, C21, C23, C29 27 pF capacitor, ATC 100B American Technical Ceramics C7, C15, C19, C30 470 nF; 50 V ceramic capacitor C9, C32 470 μF; 63 V electrolytic capacitor Q1, Q6 Regulator JRC 78L08 Q5 NPN transistor PMBT2222 NXP Semiconductors Q3 15 mm × 13 mm 3 dB hybrid XC1400P-03S Anaren Q2, Q4 LDMOS BLF6G15L-250PBRN NXP Semiconductors L1, L2, L3, L4 26 mm × 5 mm inductor R1, R18 2 kΩ, 1% resistor, 0805 R2, R19 200 Ω potentiometer R20 75 Ω, 1% resistor, 0805 R3, R4, R21, R23 430 Ω, 1% resistor, 0805 R15, R22 1.1 kΩ, 1% resistor, 0805 R14 11 kΩ, 1% resistor, 0805 R13 820 Ω, 1% resistor, 0805 R8 5.1 Ω, 1% resistor, 0805 R9, R10, R12, R16 10 Ω, 1% resistor, 0805 R5, R7, R24, R27 9.1 Ω, 1% resistor, 0805 R6, R25 499 Ω, 0.5W, 5% resistor, 2010 R17 5.1 kΩ resistor, 0805 R26 910 Ω resistor, 0805 R11 50 Ω 50 Ω load AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 13 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 6. Appendix B: PCB layout and bill of materials with auto bias R3 R4 R5 Q1 R6 R2 L1 C2 C3 C6 C10 C7 C9 R1 C11 R7 C1 C8 R8 C5 R9 L2 VDS L3 R16 VDS C4 Q2 C12 C13 C14 C15 R10 C18 C19 C16 R11 C17 2 x BLF6G15L-250PBRN Input Rev 1 RO4350 30mils Q3 2 x BLF6G15L-250PBRN Output Rev 1 C23 RO4350 30mils C22 C21 C24 C25 R12 C20 Q4 C26 C27 C28 R13 C29 R15 C33 R14 C30 C31 C35 C32 C34 019aaa281 GND VGS VDS GND +Vln autobias circuit Fig 11. Component layout for application circuit with auto bias AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 14 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN Table 3. Parts list for application circuit (auto bias) Component Value Description Manufacturer C1, C2 100 nF capacitor Murata GRM21BR71H104KA01L C3 1 μF capacitor Murata GRM31MR71H105KA88L C4, C10, C14, C20, C28, C34 10 μF capacitor Murata GRM32ER71H106KA12L C5, C6, C7, C8, C12, 27 pF C13, C15, C16, C17, C18, C21, C22, C23, C24, C26, C27, C29, C30, C31, C32 capacitor C9, C19, C25, C33 470 nF; 50 V ceramic capacitor C11, C35 470 μF; 63 V electrolytic capacitor Q1 regulator JRC 78L08 Q2, Q4 LDMOS BLF6G15-250PBRN NXP Semiconductors Q3 15 mm × 13 mm 3 dB hybrid XC1400P-03S Anaren L1, L2, L3 26 mm × 5 mm inductor R1, R14 2 kΩ, 1% resistor, 0805 R2 200 Ω potentiometer R3, R4 430 Ω, 1% resistor, 0805 R5, R7, R16 9.1 Ω resistor, 0805 R6 499 Ω, 0.5 W, 5% resistor, 2010 R8 5.1 Ω, 1% resistor, 0805 R9, R10, R12, R15 10 Ω, 1% resistor, 0805 R11 50 Ω 50 Ω load R13 820 Ω, 1% resistor, 0805 AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 Bourns © NXP B.V. 2011. All rights reserved. 15 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 7. Appendix C: Component layout auto bias board Vi = +13.5 V R6 R4 C3 IC1 6 11 2 C2 R1 R5 9 7 3 4 R2 C4 R7 R8(1) (2) R3 C1 IC2 C6 R13 IC3 R10 C7(2) C5 R14 C8(2) R15 R9 R12(2) RF FET R11 820 Ω 4.7 μF 22 Ω sense FET 2.2 kΩ 019aaa304 (1) R8 represents a batch of 1 to 9 resistors (a to j see Figure 13) which are used to set current. (2) Not mounted. The components within the bounding frame are to be mounted on the auto bias board; all other components are to be mounted on the RF boards. Feed throughs are used to take the wires into the screened housing. Fig 12. Circuit diagram of auto bias board AN10923 Application note All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 16 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN IC1 R1 (1) R3 R2 R4 C3 C2 C1 R5 R6 R7 C4 R8a R8b R8c R8d R8e R8f R8g R8h R8j IC2 (1) R9 C5 R11 C8 R10 (1) R12 C8 (1) IC3 C7 R15 R13 R14 019aaa303 (1) Not mounted Fig 13. Component layout of auto bias board Table 4. Parts list for auto bias board Component Application note Description Manufacturer C1 1 nF ceramic capacitor C2 2.2 μF electrolytic capacitor C3 100 μF electrolytic capacitor C4 10 μF electrolytic capacitor C5 2.2 nF ceramic capacitor C6 100 nF ceramic capacitor IC1 - LT3011 Linear Technology IC2 - LM4051 National Semiconductor IC3 - LM7341 National Semiconductor R1, R6 1 MΩ resistor, 0603 R2, R3[1] 100 kΩ resistor, 0603 R4 4.7 kΩ resistor, 0603 R5 47 kΩ resistor, 0603 R7 4.7 Ω resistor, 1206 R8 57 Ω up to 9 off; resistor, 0603 R9 2.7 kΩ resistor, 0603 R10 56 kΩ resistor, 0603 R11, R12[1] 6.8 kΩ resistor, 0603 R13, R14, R15 10 kΩ resistor, 0603 [1] AN10923 Value Not mounted All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 17 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 8. Abbreviations Table 5. AN10923 Application note Abbreviations Acronym Description ACPR Adjacent Channel Power Ratio CCDF Complementary Cumulative Distribution Function CDMA Code Division Multiple Access EDGE Enhanced Data rates for GSM Evolution GSM Global System for Mobile communication IS-95 Interim Standard 95 LDMOS Laterally Diffused Metal-Oxide Semiconductor LDMOST Laterally Diffused Metal-Oxide Semiconductor Transistor PAR Peak-to-Average power Ratio RF Radio Frequency UMTS Universal Mobile Telecommunications System VSWR Voltage Standing-Wave Ratio W-CDMA Wideband Code Division Multiple Access All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 18 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 9. Legal information 9.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 9.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product AN10923 Application note design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Evaluation products — This product is provided on an “as is” and “with all faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 9.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 1 — 14 March 2011 © NXP B.V. 2011. All rights reserved. 19 of 20 AN10923 NXP Semiconductors 1.5 GHz Doherty power amplifier using the BLF6G15L-250PBRN 10. Contents 1 2 3 3.1 3.2 3.3 3.4 4 4.1 4.2 4.2.1 4.2.2 4.3 5 6 7 8 9 9.1 9.2 9.3 10 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Circuit description . . . . . . . . . . . . . . . . . . . . . . . 3 Design and Tuning. . . . . . . . . . . . . . . . . . . . . . . 4 Design of the single stage amplifiers . . . . . . . . 5 Doherty design . . . . . . . . . . . . . . . . . . . . . . . . . 5 Tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transistor biasing . . . . . . . . . . . . . . . . . . . . . . . 6 Test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Network analyzer frequency sweep . . . . . . . . . 6 Large signal power sweeps . . . . . . . . . . . . . . . 7 CW network analyzer power sweep (AM-AM and AM-PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-tone W-CDMA . . . . . . . . . . . . . . . . . . . . . . . . 8 Residual memory magnitude and phase surface plots large signal power sweeps. . . . . . . . . . . 10 Appendix A: PCB layout and bill of materials (no auto bias) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Appendix B: PCB layout and bill of materials with auto bias . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Appendix C: Component layout auto bias board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 March 2011 Document identifier: AN10923