Click to see this datasheet in Simplified Chinese! FSA2467 0.4Ω Low-Voltage Dual DPDT Analog Switch Features Description Typical 0.4Ω On Resistance (RON) for +2.7V Supply 0.25Ω Maximum RON Flatness for +2.7V Supply The FSA2467 is a dual Double-Pole, Double-Throw (DPDT) analog switch. The FSA2467 operates from a single 1.65V to 4.3V supply. The FSA2467 features an ultra-low on resistance of 0.4Ω at a +2.7V supply and 25°C. This device is fabricated with sub-micron CMOS technology to achieve fast switching speeds and is designed for break-before-make operation. Features Less then12µA ICCT Current when Sn Input is Lower than VCC 3 x 3mm 16-Lead MLP Package 1.8x2.6mm 16-Lead UMLP Package Broad VCC Operating Range Low THD (0.02% Typical for 32Ω Load) Applications FSA2467 features very low quiescent current even when the control voltage is lower than the VCC supply. This feature allows mobile handset applications direct interface with baseband processor general-purpose I/Os. Cell Phone PDA Portable Media Player Ordering Information Part Number Top Mark FSA2467MPX FSA 2467 FSA2467UMX GC Package Description 16-lead Molded Leadless Package (MLP), JEDEC MO-220, 3 x 3mm Square 16-lead Ultrathin Molded Leadless Package (UMLP), 1.8 x 2.6mm Application Diagram Figure 1. Application Diagram © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch April 2012 1B0 1A 1B1 VCC 4B0 16 15 14 13 12 4A 1 1S 2 11 4B1 2B1 3 10 2S 2A 4 9 3B0 Figure 2. MLP (Top Through View) 5 6 7 8 2B0 GND 3B1 3A Figure 3. UMLP (Top View) Truth Table Pin Descriptions Control Inputs Function Name Function LOW nB0 Connected to nA nA，nB0，nB1 Data Ports HIGH nB1 Connected to nA nS Control Input FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Pin Assignments Analog Symbol Figure 4. Analog Symbol © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCC Supply Voltage -0.5 5.0 V VS Switch Voltage -0.5 VCC+0.3 V VIN Input Voltage -0.5 5.0 IIK Input Diode Current -50 ISW Switch Current ISWPEAK TSTG Peak Switch Current (Pulsed at 1ms duration, <10% Duty Cycle) Storage Temperature Range -65 V mA 350 mA 500 mA +150 ºC TJ Junction Temperature +150 ºC TL Lead Temperature, Soldering 10 Seconds +260 ºC 5.5 kV ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Absolute Maximum Ratings Unit VCC Supply Voltage 1.65 4.30 V VIN Control Input Voltage(1) 0 VCC V Vs Switch Input Voltage 0 VCC V TA Operating Temperature -40 +85 ºC Note： 1. Unused inputs must be held HIGH or LOW. They may not float. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 3 Typical values are at 25ºC unless otherwise specified. TA = -40 to +85ºC TA = +25ºC Symbol Parameter Condition VCC (V) Min. VIH VIL Input Voltage High Input Voltage Low IIN Control Input Leakage INO(OFF) INC(OFF) Off Leakage Current of Port nB0 and nB1 IA(ON) On Leakage Current of Port A VIN=0V to VCC Typ. Max. Min 4.3 1.4 2.7 to 3.6 1.3 2.3 to 2.7 1.1 1.65 to 1.95 0.9 Max. V 4.3 0.7 2.7 to 3.6 0.5 2.3 to 2.7 0.4 1.65 to 1.95 0.4 1.65 to 4.30 Unit V -0.5 0.5 μA nA=0.3V, VCC-0.3V 1.95 to 4.30 -10 10 -50 50 nA 1.95 to 4.30 -10 10 -50 50 nA nB0 or nB1=0.3V, VCC0.3V or floating nA=0.3V,VCC-0.3V RON ∆RON Switch On (2) Resistance On Resistance Matching Between (3) Channels On Resistance RFLAT(ON) Flatness(4) ICC Quiescent Supply Current ICCT Increase in ICC Current per Control Voltage FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch DC Electrical Characteristics nB0 or nB1=0.3V, VCC0.3V or Floating IOUT=100mA 4.3 0.4 0.6 nB0 or nB1=0V,0.8V, 1.8V,2.7V 2.7 0.4 0.6 IOUT=100mA, nB0 or nB1=0V,0.7V, 1.2V, 2.3V 2.3 0.55 0.95 IOUT=100mA, nB0 or nB1=1.0V 1.8 0.8 2.0 IOUT=100mA, nB0 or nB1=0.8V 2.7 0.04 0.10 IOUT=100mA, nB0 or nB1=0.7V 2.3 0.03 0.10 Ω Ω IOUT=100mA, B0 or nB1=0V to VCC 2.7 0.25 2.3 0.3 VIN=0V to VCC IOUT=0V 4.3 VIN=1.8V 4.3 7 12 15 VIN=2.6V 4.3 3 6 7 -100 100 -500 500 Ω nA μA Notes: 2. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch. 3. ∆ RON=RON max – RON min measured at identical VCC, temperature and voltage. 4. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 4 Typical values are at 25ºC unless otherwise specified. Symbol Parameter Condition Min. tON tOFF tBBM Q OIRR Xtalk BW THD Turn-On Time Turn-Off Time Break-BeforeMake Time Charge Injection Off Isolation Crosstalk -3dB Bandwidth Total Harmonic Distortion TA = -40 to +85ºC TA = +25ºC VCC Typ. Max. Min. 3.6 to 4.3 50 60 RL=50Ω, CL=35pF 2.7 to 3.6 65 75 2.3 to 2.7 80 90 nB0 or nB1=1.5V 3.6 to 4.3 32 40 RL=50Ω, CL=35pF 2.7 to 3.6 42 50 2.3 to 2.7 52 60 3.6 to 4.3 12 RL=50Ω, CL=35pF 2.7 to 3.6 15 2.3 to 2.7 20 CL=100pF, VGEN=0V, RGEN=0Ω 3.6 to 4.3 15 CL=100pF, VGEN=0V, RGEN=0Ω 2.7 to 3.6 10 CL=100pF, VGEN=0V, RGEN=0Ω 2.3 to 2.7 8 3.6 to 4.3 -75 2.7 to 3.6 -75 2.3 to 2.7 -75 f=100KHz, RL=50Ω,CL=5pF 3.6 to 4.3 -75 f=100KHz, RL=50Ω, CL=5pF 2.7 to 3.6 -75 2.3 to 2.7 -75 RL=50Ω 2.3 to 4.3 85 RL=32Ω, VIN=2VPP, f=20 to 20kHZ 3.6 to 4.3 0.02 RL=32Ω, VIN=2VPP, f=20 to 20kHZ 2.7 to 3.6 0.02 RL=32Ω, VIN=2VPP, f=20 to 20kHZ 2.3. to 2.7 0.02 Figure ns Figure 8 ns Figure 8 ns Figure 9 pC Figure 11 dB Figure 10 dB Figure 10 MHZ Figure 13 % Figure 14 Max. nB0 or nB1=1.5V nB0 or nB1=1.5V Unit FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch AC Electrical Characteristics Capacitance Symbol Parameter Condition VCC TA = +25ºC Typical Unit Figure Control Pin Input Capacitance f=1MHZ 0 1.5 pF Figure 8 COFF B Port Off Capacitance f=1MHZ 3.3 32 pF Figure 8 CON A Port On Capacitance f=1MHZ 3.3 118 pF Figure 8 CIN © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 5 Figure 5. RON at 2.7V VCC FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Typical Applications Figure 6. RON at 2.3V VCC Figure 7. RON at 1.8V VCC © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 6 Figure 8. Turn-On / Turn-Off Timing FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch AC Loadings and Waveforms Figure 9. Break-Before-Make Timing Figure 10. Off Isolation and Crosstalk © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 7 Figure 11. Figure 12. Charge Injection On / Off Capacitance Measurement Setup Figure 13. Figure 14. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch AC Loadings and Waveforms (Continued) Bandwidth Harmonic Distortion www.fairchildsemi.com 8 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Package Dimensions Figure 15. 16-Lead, Molded Leadless Package (MLP), JEDEC MO-220 3x3mm Square Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/3x3MLP16_Pack_TNR.pdf. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 9 1.80 0.10 C A 2.10 B 0.563 (15X) 0.663 2X 1 2.60 PIN#1 IDENT 0.10 C TOP VIEW 0.10 C 2.90 0.40 0.55 MAX. 0.08 C 0.225 (16X) 2X RECOMMENDED LAND PATTERN 0.152 TERMINAL SHAPE VARIANTS SEATING C PLANE 0.05 0.00 0.40 0.60 SIDE VIEW 0.15 0.25 0.45 0.35 15X 0.10 0.10 PIN 1 5 0.30 15X 0.50 0.15 0.25 NON-PIN 1 Supplier 1 9 0.40 0.30 0.50 0.15 0.25 1 0.15 15X 0.25 PIN 1 PIN#1 IDENT 16 0.55 0.45 BOTTOM VIEW NON-PIN 1 Supplier 2 13 0.25 0.15 0.10 C A B 0.05 C R0.20 PACKAGE EDGE NOTES: A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. E. DRAWING FILENAME: MKT-UMLP16Arev4. F. TERMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL SHAPE VARIANTS. Figure 16. 0.3015X 0.50 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch Package Dimensions LEAD OPTION 1 SCALE : 2X LEAD OPTION 2 SCALE : 2X 16-Lead, Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 10 FSA2467 — 0.4Ω Low-Voltage Dual DPDT Analog Switch © 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.8 www.fairchildsemi.com 11