www.fairchildsemi.com AN-9090 PFC SPM® 3 Series Ver. 2 for Boost PFC Topology Summary This application note supports the PFC SPM® 3 series ver. 2 for boost PFC topology (boost PFC SPM 3 series). It should be used in conjunction with the Boost PFC SPM 3 series datasheet and Inductor Design Guide (AN-9091). Design Concept Countries have recently tried to tighten energy regulations. For example, U.S. Department of Energy announced that it will enforce a seasonal energy efficiency rating (SEER) standard of 13 for residential central air conditioners starting in January 2006. This represents a 30 percent increase in energy efficiency compared to the previous SEER standard of 10. The Japanese government announced the need of 20% higher efficiency than present efficiency level to meet the Kyoto Protocol from 2010, particularly in airconditioners and refrigerators, “Energy-saving” has become most important in the world of air-conditioners and various technologies are being developed to increase efficiency. Fairchild has recently developed a new series of Power Factor Correction (PFC) modules. Power factor correction circuits are needed to meet international harmonics regulations (such as IEC 61000-3-2). This application note describes boost PFC modules; focusing on internal structure, operation of internal components, typical application circuit design, control method of active PFC, and package installation method. In addition, this application note provides technical information about boost PFC SPM 3 series and included design examples enable design engineers to create efficient and optimized designs in a short design cycle with the Fairchild boost PFC SPM 3 series. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 The detailed features and integrated functions are: 600 V/20 A and 600 V/30 A ratings in the same package Major target of the Boost PFC SPM® 3 series in midpower air-conditioner applications (1.5~3 kW) Compact and cost-effective transfer mold package enable miniaturization of converter design High reliability due to the coordination of fully tested IC and IGBT Integrated full-bridge diode rectifier Built-in IC for IGBT gate driving and protection Fast-recovery boost diode minimizes reverse-recovery loss Under-Voltage Lockout (UVLO) and Over-Current Protection (OCP), through an external shunt resistor with a fault signal output (VFO) Built-in thermistor Optimized IGBT switching characteristics with reduced switching loss and low EMI noise Low leakage current and high isolation voltage because of Direct Bonded Copper (DBC)-based substrate Active-HIGH input signal logic resolves the startup and shutdown sequence constraint between VCC (control supply voltage) and signal input, providing fail-safe operations. A direct connection between the boost PFC SPM 3 series and a 3.3 V or 5 V MCU/DSP is possible without additional external sequence logic. Isolation voltage rating of 2000 Vrms for one minute www.fairchildsemi.com AN-9090 APPLICATION NOTE Boost PFC Technology Power Devices The improvement of boost PFC SPM® 3 series ver. 2 results primarily from the technological advancement of the power devices (i.e., IGBT and FRD) in the boost circuit. The design goal was to reduce power losses and increase current density of these power devices. See below for details. Insulated-Gate Bipolar Transistor (IGBT) The IGBT of the boost PFC SPM 3 series includes Fairchild's robust technology. Through optimized nonpunch-through (NPT) technology of IGBT, the package keeps a suitable Safe Operating Area (SOA) for each converter application, while dramatically reducing on-state conduction loses and turn-on/off switching losses. Figure 3. IGBT Turn-Off Switching Waveform Comparison [Ver. 2.0 IGBT Turn Off] Figure 1 shows the IGBT switching test circuit. Figure 2 and Figure 3 show the IGBT turn-off waveform comparison between ver. 1 and ver. 2. The ver.1 IGBT is SPMS IGBT and the ver. 2 IGBT is NPT IGBT. Boost PFC SPM P Fast Recovery Diode (FRD) The FRD adopts “hyper-fast” diodes with low forwardvoltage drops, high breakdown voltages, and soft recovery characteristics. Figure 4 show the typical forward-voltage drop at TC=-40°C, 25°C, and 150C. Figure 5 illustrates reverse recovery time tRR at TC=100C. Line stray Inductance < 100nH Inductor 15V 220µF VDC = 300V VCC 0.1µF IN Switching Pulse LO COM N Line stray Inductance < 100nH Figure 1. IGBT Switching Test Circuit Diagram (Switching Conditions: VDC=400 V, VCC=15 V, CVCC=220 μF, Inductor = 500 μH Total Stray L<200 nH) Figure 4. Typical Forward-Voltage Drop of FRD (Hyper-Fast Diode) at TC =-40°C, 25°C, 150°C Figure 2. IGBT Turn-Off Switching Waveform Comparison [Ver. 1.0 IGBT Turn Off] Figure 5. Reverse Recovery Time tRR of Fast-Recovery Diode (FRD) at TC=100℃ © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 2 AN-9090 APPLICATION NOTE Rectifier Diode Figure 7 and Figure 7 show the typical forward-voltage drop of the rectifier diodes at TC=-40°C, 25°C, and 150°C. Ver. 1 and Ver. 2 use the same diodes in the given current rating. Figure 8 and Figure 9 Figure 9show non-repetitive peak surge current (IFSM) at 60 Hz. IFSN is peak forward surge current at a specified current waveform (normally 10 ms / 50 Hz half-sine-wave, sometimes 8.3 ms / 60 Hz half-sinewave). Figure 8. FPAB20BH60B Non-Repetitive Peak Surge Current (IFSM) at 60 Hz Non-Repetitive Surge Current of Rectifier(FPAB30BH60B)) Forward Surge Current, Ifsm[A] 500 Figure 6. Typical 20 A Forward-Voltage Drop of Input Rectifier Diode at TC =-40°C, 25°C, 150°C 400 300 200 100 0 10 20 30 40 50 Number of Cycles at 60Hz Figure 9. FPAB30BH60B Non-Repetitive Peak Surge Current (IFSM) at 60 Hz Gate Drive IC This gate drive IC for IGBT was designed to have only the minimum functionality required for low-power drives. It has low standby current and the logic input can work with 3.3 V or 5.0 V. This IC has built-in Under-Voltage Lockout (UVLO) for VCC and Over-Current Protection (OCP) for internal power components. Figure 7. Typical 30 A Forward-Voltage Drop of Input Rectifier Diode at TC =-40°C, 25°C, 150°C © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 3 AN-9090 APPLICATION NOTE outstanding heat dissipation characteristics compromising the isolation rating. Package Heat dissipation capability is an important factor that limits current ratings of power modules. A trade-off exists among heat dissipation characteristics, package size, and isolation characteristics. The key to a good package technology is to accomplish optimized package size while maintaining without In the boost PFC SPM 3 package, technology bare direct bonded copper (DBC) with good heat dissipation characteristics is attached directly to the lead frame. Figure 10 shows the package outline and the cross sections of the boost PFC SPM 3 package. Figure 10. Vertical Structure of Boost PFC SPM 3 Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 4 AN-9090 APPLICATION NOTE Outline & Pin Description Figure 11. Outline Drawings © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 5 AN-9090 APPLICATION NOTE Figure 12. Outline Drawings © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 6 AN-9090 APPLICATION NOTE Figure 13. Detailed Package Outline Drawing © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 7 AN-9090 APPLICATION NOTE Common Supply Ground Pin (COM) The boost PFC SPM® 3 series common pin connects to the control ground for the internal LVIC. Important! To avoid noise influences, the main power current should not flow through this pin. Signal Input Pins (IN) Input signal to the gate drive IC for IGBT. This is activated by voltage input signal. The terminal is internally connected to a Schmitt trigger circuit composed of 5 V-class CMOS. The signal logic of this pin is active HIGH. The IGBT associated with this pin turns ON when a sufficient logic voltage is applied to this pin. The input wiring should be as short as possible to prevent noise influences. To prevent signal oscillations, an RC coupling is recommended, as illustrated in Figure 28. Over-Current Detection Pin (CSC) The current sensing shunt resistor should be connected between the pin CSC and the low-side ground COM to detect any over current event (see Figure 29). A shunt resistor should be selected to meet the detection level required for the specific application. An RC filter should be connected to pin CSC to eliminate noise. Typically, a 1- 2 µs filter time constant is recommended. Minimize the connection length between the shunt resistor and CSC pin. Fault Output Pin (VFO) This is the fault output alarm pin. An active LOW output is asserted on this pin to indicate a fault state condition in the converter. The alarmed condition is either Over-Current Protection (OCP) or Under-Voltage Lockout (UVLO). The VFO output is an open-drain configuration. The fault (FO) signal line should be pulled up to the 5 V logic power supply with a 4.7 k resistor. Fault-Out Duration Selection Pin (CFOD) This pin is used to select the duration of fault-out pulse. An external capacitor should be connected between this pin and COM to set the fault-out duration (tFOD), which is expressed as the following equation: CFOD = 18.3 x 10-6 x tFOD [s] (1) -6 where 18.3 x 10 is an internal value of IC. Description of Input and Output Pins Figure 14 and 0 show the pin map of the boost PFC SPM® 3 series. The detailed functional descriptions follow. Figure 14. Pin Configuration (Top View) Table 1. Pin Definitions Pin # Name Description 1 VCC 2, 3, 4 COM 5 IN Signal Input for IGBT 6 VFO Fault Output 7 CFOD Capacitor for Fault-Output Duration Time Selection 8 CSC Capacitor (Low-Pass Filter) for OverCurrent Detection Input 9 RTH NTC Thermistor Terminal 10 VTH NTC Thermistor Terminal No Connection Common Bias Voltage for IC and IGBT Driving Common Supply Ground 11, 12 N.C. 13~16 N 17~20 NR 21, 22 P 23 N.C 24 L 25 PR 26 R AC Input for R-Phase 27 S AC Input for S-Phase IGBT Emitter Negative DC-Link of Rectifier Positive DC-Link of Semi-Converter No Connection Inductor Connection Terminal Positive DC-Link of Rectifier Positive DC-Link Pin (P) This is the DC-link positive power supply pin of the converter. Internally connected to the cathode of the boost diode. To suppress the surge voltage caused by the DC-link wiring or PCB pattern parasitic inductance, connect a filter capacitor close to this pin. (Typically a metal film capacitor with 0.1 ~ 1.0 µF value can be used.) Common Bias Voltage Pin (VCC) This is a control supply pin for the built-in LVIC. To prevent malfunctions caused by noise and ripple in the supply voltage, a good-quality filter capacitor (low ESR, low ESL) should be mounted close to these pins. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 8 AN-9090 APPLICATION NOTE Positive DC-Link Pin of Full-Bridge Diode Rectifier (PR) This is the DC-link positive power supply pin of the full-bridge diode rectifier. Internally connected to the cathodes of the high-side rectifier diodes. An external boost inductor needs to be connected between this pin and the L pin. (L) This is the collector pin of IGBT for the PFC. This is connected to DC-link pin PR of full-bridge diode rectifier through an external inductor for PFC. Emitter Pins of IGBT (N) These pins are connected to the emitter of the IGBT. Typically a shunt resistor can be connected between this pin and NR to sense the IGBT current Negative DC-Link Pins of Full-Bridge Diode Rectifier (NR) These are DC-link negative power supply pins (power ground) of the full-bridge rectifier. These pins are connected to the anodes of low-side rectifier diodes. AC Input Pins (R,S) These are the input pins of the full-bridge rectifier. Connect these pins to an AC power source. Thermistor Bias Voltage (V(TH)) This is the bias voltage pin of the internal thermistor. It should be connected to the 5 V logic power supply. Series Resistor for Thermistor (Temperature Detection) (R(TH)) For temperature detection, this pin should be connected to an external series resistor. The external series resistor should be selected to meet the detection range based on the specification of each application (for details, refer to Figure 21). This configuration linearizes the relationship between the temperature and the voltage sensed. Internal Circuit Figure 15 illustrates the internal block diagram of the boost PFC SPM® 3 series. Note that the boost PFC SPM 3 series consists of single boost stage with an IGBT and a diode, a drive LVIC for gate drive, rectifier diodes, and an NTC thermistor for temperature detection. Figure 15. Internal Block Diagram © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 9 AN-9090 APPLICATION NOTE Ordering Information FPAB30BH60B IGBT Technology Blank : Ver1.0 IGBT B : Ver2.0 IGBT Voltage Rating 60 : 600V rating BH : Boost PFC PH : Bridgeless PFC Package Option B : DBC based S : Ceramic based F : Full pack based Thermistor Option A : Built-in Thermistor D : No Thermistor Current Rating 20 : 20A rating 30 : 30A rating 40 : 40A rating 60 : 60A rating Product Category S : Partial PFC module P : Active PFC module F : Fairchild Semiconductor Figure 16. Order Information Product Lineup Table 2. Lineup of Boost PFC SPM® 3 Series Ver. 1 and Ver. 2 Rating Part Number Package Isolation Voltage (Vrms) Main Applications Current (A) Voltage (V) FPAB30BH60 30 600 DBC Substrate (SPM27-lA) 2500 Vrms Sinusoidal, 1min Air Conditioner, High-Power Home Appliance FPAB20BH60BNew 20 600 DBC Substrate (SPM27-lC) 2500 Vrms Sinusoidal, 1 min Air Conditioner FPAB30BH60BNew 30 600 DBC Substrate (SPM27-lC) 2500 Vrms Sinusoidal, 1min Air Conditioner © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 10 AN-9090 APPLICATION NOTE Key Parameter Design Guidance Over-Current Protection (OCP) The boost PFC SPM® 3 series needs an external shunt resistor for over-current detection, as shown in Figure 17. The LVIC has a built-in over-current protection (OCP) function that senses the voltage of the CSC pin. If this voltage exceeds the VSC(REF) (the threshold voltage trip level of the over-current) specified in the device datasheets (VSC(REF),Typ. is 0.5 V), a fault signal is asserted and the IGBT is turned off. To avoid nuisance trips associated with switching noise, an RC filter is required. The maximum over-circuit trip level generally needs to be below 1.5 times the nominal rated collector current. The IC over-current protection timing chart is shown in Figure 18. Boost PFC SPM 5V 15V Over-Current, ShortCircuit, Saturation VDC VCC IC . Gate Drive . UVLO . OCP VFO RSHUNT COM CSC RF Low Pass Filter Circuit of OCP VCSC Over-Current & Short Circuit Current (IOC) CSC Operates Protection Function (IC Shutdown) OC Trip Level : VSC(REF) IOC (Over Current) Figure 17. Operation of Over-Current Protection (OCP) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 11 AN-9090 APPLICATION NOTE IGBT Control Input C6 Protection Circuit State C7 SET RESET External filter delay + Internal IC delay + IGBT off delay < OCWT (typical 2~3µsec) C4 Gate Voltage C2 C3 Soft turn-off small voltage spike (to prevent of L*di/dt effect) OC External filter needed with 1~2µsec time constant C1 Output Current C8 OC Reference Voltage (Typ 0.5[V]) Sensing Voltage ( of the shunt resistance ) Fault Output Signal IC Filtering < 500nsec Fault-Out Width(TFOD) : 1.8ms, CFOD = 18.3 X 10-6 X tFOD[F] CR circuit time constant delay C5 How Long? Figure 18. Timing Chart of Over-Current Protection Function C1. Normal operation: IGBT ON and carrying current C2. Over-current detection (OC trigger) C3. IGBT gate interrupt C4. Fault signal generation / IGBT slowly turns OFF C5. Fault output timer operation starts. The pulse width of the fault output signal is set by the external capacitor CFOD. C6. Input “L”: IGBT OFF state C7. Input “H”: IGBT ON state. During the active period of fault output, the IGBT doesn’t turn ON. C8. IGBT OFF state © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 12 AN-9090 APPLICATION NOTE Selection of Shunt Resistor Notes: 1. RSHUNT(min): VOC(max) / OC(max)=0.55 / 30 =18.33 mΩ 2. OC(min): VOC(min) / RSHUNT(max) = 0.45 / (0.0192x1.05) =22.24 A 3. OC(typ): VOC(typ) / RSHUNT(typ) = 0.50 / (0.0183/0.95) = 25.91 4. Maximum OC trip level: 1.5 x IC = 1.5 x 20 = 30 A Figure 17 shows an example circuit of the OCP using one shunt resistor. The IGBT emitter current is monitored and passed through the RC filter. If the current exceeds the OCP reference level, the gate of the IGBT is switched to OFF state and the FO, fault output, signal can be transmitted to MCU. Since an OC event should not repeat, PWM input for IGBT operation should be immediately halted by MCU when the FO fault signal is given. The power rating of shunt resistor calculation examples: Maximum load current of inverter (IRMS): 14 ARMS Shunt resistor value at TC=25°C (RSHUNT,min): 18.33°mΩ Derating ratio of shunt resistor at TSHUNT=100°C: 70% (see Figure 19) Safety margin: 20% PSHUNT: The value of the shunt resistor is calculated by the following equations: Maximum OC current trip level: IOC(max)=1.5 x IC (rated current) or determined by application requirement. (I2rmsX RSHUNTX Margin)/Derating Ratio = (142X0.01833X1.2)/0.7 = 6.16 W Therefore, the proper power rating of shunt resistor is 10.0 W. Current feedback range: IRMSMAX x 1.414 + ripple considering inductor core saturation OC trip referenced voltage: VOC=min. 0.45 V, typ. 0.5 V, max. 0.55 V Shunt resistance: IOC(max)=VOC(max)/RSHUNT(min) RSHUNT(min)=VOC(max)/IOC(max) If the deviation of shunt resistor is limited below ±5%: RSHUNT(typ) = RSHUNT(min)/0.95, RSHUNT(max) = RSHUNT(typ) X 1.05 The actual OC trip current level becomes: IOC(typ)=VOC(typ) / RSHUNT(typ), IOC(min) = VOC(min) / RSHUNT(max) The power rating of shunt resistor is calculated by: Figure 19. Derating Curve Example of Shunt Resistor (from RARA ELEC.) PSHUNT = (I2RMS X RSHUNT X Margin) / Derating Ratio where: Irms = Maximum load current of converter; RSHUNT = Shunt resistor typical value at TC=25°C; Derating ratio of shunt resistor at TSHUNT=100°C (from datasheet of shunt resistor); and Margin = Safety margin: 20% is recommended. Time Constant of Internal Time Delay An RC filter (reference RFCSC in Figure 17) is necessary to prevent noise related to OCP circuit malfunction. The RC time constant is determined by the applied noise time and the Short-Current Withstanding Time (tSCWT) of the IGBT. The value of shunt resistor calculation examples: FPAB20BH60B, Shunt Resistor dispersion: ±5%. When the external shunt resistor voltage drop exceeds the OCP level, this is applied to the CSC pin via the RC filter. The RC filter delay time (t1) is the time required for the CSC pin voltage to rises to the referenced OCP level. Table 5 shows the specification of the OCP level. The IC has an internal filter time (logic filter time for noise elimination: t2). Therefore, consider this type of filter time when designing the RC filter of VSC. Table 3. Specification for OCP level (VSC(ref)) Conditions Min. Typ. Max. Unit Specification at TJ =25oC, VCC =15 V 0.45 0.50 0.55 V Table 4. Operating Over Current Range (RSHUNT=18.33 mΩ (Min.)(1), 19.26 mΩ (Typ.), 20.23 mΩ (Max.)) Table 5. Specification for OCP Level (VSC(ref)) Conditions Min.(2) Typ.(3) Max.(4) Unit Operating OC Level at TJ =25oC 22.24 25.91 30.00 A © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 Conditions Min. Typ. Max. Unit Specification at TJ =25°C, VCC =15 V 0.45 0.50 0.55 V www.fairchildsemi.com 13 AN-9090 APPLICATION NOTE t1 t2 t3 t4 t5 VIN tIC VSC VFO VIN: Voltage of input signal tIC: IC delay VSC: Voltage of CSC pin VFO: Voltage of VFO pin IOC: Over-current (short-circuit) t1: Filtering time of RC filter of VSC t2: Filtering time of CSC. If VCSC width is less than t2, OCP cannot operate. t3: Delay from CSC triggering to IC delay. t4: Delay from CSC triggering to fault-out signal. t5: Delay from CSC triggering to over-current. IOC Figure 20. Internal Delay Chart of OC Protection Table 6. Internal Delay Time of OC Protection Circuit Item Min. Typ. Max. Unit Internal Filter Delay Time (t2) 0.5 0.8 s IC & FO Transfer Delay Time (t3) 0.8 1.8 s FO Fault-Out Signal Time (t4) 4.0 4.5 s Notes: 5. To guarantee safe over-current protection (OCP) under all operating conditions, CSC should be triggered within 2.0 μs after an over-current event occurs. 6. It is recommended that delay from over-current event to CSC triggering should be minimized. Figure 21 and Figure 22 show operating waveforms of the Over-Current Protection (OCP) function. Normally, τ (time constant of RC filter of CSC) doesn’t accurately operate due to fast di/dt of IOC (over-current). Therefore, consider this kind of situation when deciding the time constant of the RC filter of CSC. Figure 21. Waveform of Over-Current Protection (OCP) Function Operation (Time Constant of RC Filter: 1.5 μs (RSC=1.5 [kΩ], CSC=1 [nF]), RSHUNT=15 [mΩ]) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 14 AN-9090 APPLICATION NOTE Figure 22. Waveform of Over-Current Protection (OCP) Function Operation. (Time Constant of RC Filter: 3.8 μs (RSC=3.8 [KΩ], CSC=1 [nF]), RSHUNT=15 [mΩ]) Therefore, the tTOTAL (total time) from the detection of the OC trip current to the gate off of the IGBT becomes: immediately by turning the gate signal (VIN_L) off via the gate driver block. The pre-driver turns on the output buffer of the gate driver block to discharge the gate charge through path 1 (① in Figure 24). When the IGBT is turned off by a protection function, the gate driver is disabled by the protection function signal via output of the protection circuit (disable output buffer, high-Z). The output of the protection circuit turns on the switch of the soft-off function. Therefore, VGE is discharged slowly via the soft-off, path 2 (②in Figure 24). 𝐭 𝐓𝐎𝐓𝐀𝐋 = 𝐑𝐂 𝐟𝐢𝐥𝐭𝐞𝐫 𝐝𝐞𝐥𝐚𝐲 𝐭𝟏 + 𝐃𝐞𝐥𝐚𝐲 𝐟𝐫𝐨𝐦 𝐂𝐒𝐂 𝐭𝐫𝐢𝐠𝐠𝐞𝐫 𝐭𝐨 𝐈𝐎𝐂 𝐭𝟒 Therefore, total delay time (tTOTAL) should be less than OCWT of the SCSOA curve. 𝐎𝐯𝐞𝐫 − 𝐂𝐮𝐫𝐫𝐞𝐧𝐭 𝐖𝐢𝐭𝐡𝐬𝐭𝐚𝐧𝐝𝐢𝐧𝐠 𝐓𝐢𝐦𝐞 𝐭𝐎𝐂𝐖𝐓 > 𝐭 𝐓𝐎𝐓𝐀𝐋 𝐭𝟏 + 𝐭𝟒 The time constant of the RC filter should be set in the range of 1.5 ~ 2.0 μs because the IGBT and other devices should be protected under all operating conditions. VCC Soft Turn-Off VCC SCP CSC Output Buffer (Short-Circuit Current Protection) The LVIC has a soft turn-off function to protect the IGBT from over-voltage of VPN (supply voltage) induced by overcurrent hard off. “Over-current hard off” means IGBT gets turned off by the input signal before a protection function (UVLO, OCP) starts under fault conditions. In this case, VPN (supply voltage) may rapidly rise by high di/dt of ISC (over current). This kind of rapid rise of VPN causes destruction of the IGBT through over-voltage stress. Softoff function prevents the IGBT rapid turn-off by slowly discharging VGE (gate to emitter voltage of IGBT). VIN_L Restart 1.0kΩ PreDriver Lo 5.0kΩ Gate Driver Protection Circuit Timer Soft-off VFO COM CFOD An internal block diagram of LVIC and the operation sequence of the soft turn-off function are shown in Figure 23 and Figure 24. The function operates by two internal protection functions (Under-Voltage Lockout (UVLO) and Over-Current Protection (OCP)). When IGBT is turned off under normal conditions, the IC turns off the IGBT © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 LVIC UVLO (Under-Voltage Lockout) Figure 23. Internal Block Diagram of LVIC www.fairchildsemi.com 15 AN-9090 APPLICATION NOTE protection circuit becomes active and softly turns off the IGBT to prevent excessive overshoot voltage. LVIC IGBT VCC Gate Driver Pre Driver Output Buffer On Off Restart Figure 25 is an experimental result of the safe operating area test. It is strongly recommended that the boost PFC SPM 3 series not be operated under these conditions (VPN =400 V, TJ=150°C, IC = 45 A, current rating * 1.5times at turn-off and parasitic inductance = about 10 nF). Low side IGBT Off On TJ=150 [℃] VGE ① Soft-off Off On VPN(SURGE) @ Hard-off, ΔVPN=100V VPN(SURGE) @ Soft-off, ΔVPN=70V ② VPN=100[V/div] VFO CFOD IC @ Hard-off Figure 24. Operation Sequence of Soft Turn-Off IC @ Soft-off The difference between the hard and soft turn-off switching operation is shown in Figure 30. The hard turn-off of the IGBT creates a large overshoot (up to 100 V). The DC-link capacitor supply voltage should be limited to 400 V in this case to safely protect the boost PFC SPM® 3 series (FPAB20BH60B datasheet shows that VPN is 450 V and VPN (SURGE) is 500 V). VPN (SURGE) comes from line stray inductance, as shown in Figure 1. A hard turn-off with a duration of less than approximately 2 μs may occur in case of an over-current fault. For a normal over-current fault, the IC=20[A/div] Time [200ns/div] Figure 25. Over-Current Turn-Off Waveform of FPAB30BH60B at VPN=400 V, TJ=150℃ Table 7. Detail Description of Absolute Maximum Ratings (for FPAB30BH60B) Item Symbol Rating Vi 264 VMAX Vi(surge) 500 V The maximum input AC surge voltage between R-S. VPN 450 V The maximum steady-state (non-switching mode) voltage between P-N. A brake circuit is necessary if P-N voltage exceeds this value. VPN(surge) 500 V The maximum surge voltage (non-switching mode) between P-N. A snubber circuit is necessary if P-N surge voltage exceeds this value due to stray inductance. VCES 600 V The maximum collector-emitter voltage of built-in IGBT. Each IGBT Collector Current ±IC 30 A The maximum allowable DC continuous IGBT collector current at TC=25°C, TJ <150°C. Each IGBT Collector Current (Peak) ICP 60 A The maximum allowable DC continuous IGBT collector current at TC=25°C, TJ <150°C, under 1 ms pulse width. Input Supply Voltage Input Supply Voltage (Surge) Output Voltage Output Voltage (Surge) Collector-Emitter Voltage Junction Temperature Self-Protection Supply Voltage Limit (OCP Capability) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 TJ VPN(PROT) Description The maximum input AC voltage between R-S. The maximum junction temperature rating of the power chips integrated within the PFC SPM® is 150°C. However, to ensure -40~150°C safe operation, the average junction temperature should be limited to 125°C. Although IGBT and FRD chip are not damaged immediately at TJ=150°C, power cycles capability decreases. 400 V Under the conditions that VCC=13.5 ~ 16.5 V, non-repetitive, less than 2 μs. The maximum supply voltage for safe IGBT turn-off under over-current condition. www.fairchildsemi.com 16 AN-9090 APPLICATION NOTE Fault Output Circuit Table 8. Fault-Output Maximum Ratings Parameter Symbol Condition Fault Output Supply Voltage VFO Applied between VFO-COM Fault Output Current IFO Sink Current at VFO Pin Rating Unit -0.3~VCC+0.3 V 5.0 mA Table 9. Electric Characteristics Parameter Symbol Fault Output Voltage Conditions VFOH VSC=0 V, VFO Circuit: 4.7 kΩ to 5 V Pull-up VFOL VSC=1 V, VFO Circuit: 4.7 kΩ to 5 V Pull-up Min. Max. 4.5 Unit V 0.8 V Because FO terminal is an open-drain type, it should be pulled up to 5 V or 15 V level via a pull-up resistor. The resistor must satisfy the above specifications. Figure 26. Voltage-Current Characteristics of VFO Terminal © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 17 AN-9090 APPLICATION NOTE Under-Voltage Lockout Protection The LVIC has a under-voltage lockout (UVLO) protection function to prevent IGBT operations with insufficient gate driving voltage. A timing chart for this protection is shown in Figure 27. Input Signal Protection Circuit State RESET SET UVCCR Control Supply Voltage Need LOW-to-HIGH input transition to turn on the IGBT again (“edge trigger) Built-in typical15 μs filter to prevent malfunction by noise RESET Filtering? a1 Restart UVCCD a2 a6 a3 a4 Fault-out width (tFOD) : keep fault signal (0 V) until VCC recovers a7 Output Current a5 IGBT gate is locked off while VFO stays LOW Fault Output Signal How Long? Figure 27. Timing Chart of Low-Side Under-Voltage Protection Function a1: Control supply voltage rise: after the voltage rises UVCCR, the circuit starts when next input is applied a2: Normal operation: IGBT ON and carrying current a3: Under-voltage detection (UVCCD) a4: IGBT OFF in spite of control input condition a5: Fault output operation starts a6: Under voltage reset (UVCCR) a7: Normal operation: IGBT ON and carrying current Table 10. Specification for UVLO (Under-Voltage Lockout) Function Symbol UVCCD UVCCR Parameter Supply Circuit Under-Voltage Protection © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 Condition Min. Typ. Max. Unit Detection Level 10.7 11.9 13.0 V Reset Level 11.2 12.4 13.2 V www.fairchildsemi.com 18 AN-9090 APPLICATION NOTE Circuit of Input Signal (IN) Figure 28 shows the I/O interface circuit between MCU and boost PFC SPM® 3 series. Because the PFC SPM 3 series input logic is active-HIGH and there are built-in pull-down resistors, external pull-down resistors are not needed. Boost PFC SPM® 1k IN MCU Restart Gate Driver 5k(typ) 5V-Line RPF=4.7kΩ Figure 29. Internal Structure of Signal Input Terminal Boost PFC SPM The boost PFC SPM 3 series employs active-HIGH input logic. This removes the sequence restriction between the control supply and the input signal during startup or shutdown operation, which makes the system fail-safe. In addition, pull-down resistors are built into each input circuit, making external pull-down resistors unnecessary and reducing the external component count. The input noise filter (100 Ω+1 nF) inside the boost PFC SPM 3 series suppresses short pulse noise and prevents the IGBT from malfunction and excessive switching loss. Furthermore, by lowering the turn-on and turn-off threshold voltages of the input signal, as shown in Table 12, a direct connection to 3.3 V-class MCU or DSP is possible. IN MCU VFO CPF=1nF COM Figure 28. Recommended CPU I/O Interface Circuit Table 11. Maximum Ratings of Input and FO Pins Item Symbol Condition Rating Unit Control Supply Voltage VCC Applied between VCC(L)-COM 20 Input Signal Voltage VIN Applied between IN-COM -0.3 ~ VCC +0.3 V Fault Output Supply Voltage VFO Applied between VFO-COM -0.3 ~ VCC +0.3 V V Table 12. Input Threshold Voltage Ratings (at VCC=15 V, TJ=25°C) Item The input and fault output maximum rating voltages are shown in Table 11. Since the fault output is an open-drain port, its rating is VCC+0.3 V; 15 V supply interface is possible. However, it is recommended that the fault output be configured with the 5 V logic supply, which is the same as the input signals. It is also recommended that the decoupling capacitors be placed at both the MCU and boost PFC SPM 3 series ends of the VFO. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 Symbol Condition Min. Max. Unit Turn-on Threshold Voltage VIN(ON) Turn-off Threshold Voltage VIN(OFF) 2.8 V IN-COM 0.8 V As shown in Figure 29, the input signal section of the boost PFC SPM 3 series integrates a 5 kΩ (typical) pulldown resistor. Therefore, when using an external filtering resistor between the MCU output and the boost PFC SPM 3 series input, attention should be given to the signal voltage drop at the boost PFC SPM® 3 series input terminals to satisfy the turn-on threshold voltage requirement. For instance, the RC filter shown in Figure 22 with dashed lines uses 100 Ω and 1 nF. www.fairchildsemi.com 19 AN-9090 APPLICATION NOTE Circuit of NTC Thermistor (Monitoring of TC) The boost PFC SPM® 3 series includes a Negative Temperature Coefficient (NTC) thermistor for module temperature sensing. This thermistor is located in DBC substrate, together with power chips (IGBT/FRD) and can reflect the temperature of power chips well (see Figure 30). VDD NTC VTH RTH ADC Port Boost PFC SPM® MCU RTH NTC Thermistor Figure 32. OT Protection Circuit by MCU IC IGBT EMC Epoxy Adhesive Lead Frame FRD VDD DBC Substrate Figure 30. Location of NTC Thermistor in Boost PFC SPM 3 Package VDD NTC VTH R1 R3 R-T Curve RTH 600 I/O Port MIN TYP MAX 550 500 Resistance[k] 450 Boost PFC SPM MCU C2 R2 RTH C1 400 350 300 250 Figure 33. OT Protection Circuit by Comparator 200 150 VOUT(min) 100 -10 0 10 20 30 40 50 60 70 80 90 100 110 Output Voltage of RTH [V] 50 0 -20 V-T Curve at VDD=5.0, 3.3V, RTH=6.8kohm 5 120 Temperature TTH[¡É][°C] Figure 31. R-T Curve of NTC Thermistor in 3 Package Normally, designers use two kinds of circuits for temperature protection (monitoring) by NTC thermistor. One is Analog-Digital Converter (ADC) and the other is circuit by comparator. Figure 32 and Figure 33 show two examples of application circuit with NTC thermistor. VOUT(typ) 4 VOUT(max) VDD=5.0V 3 VDD=3.3V 2 1 0 20 30 40 50 60 70 80 90 100 110 120 o Temperature TThermistor[ C] Figure 34. V-T Curve of Figure 32 © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 20 AN-9090 APPLICATION NOTE Table 13. R-T Table of NTC Thermistor (1-1) TNTC (°C) RMIN (kΩ) RTYP (kΩ) RMAX (kΩ) T (°C) RMIN (kΩ) RTYP (kΩ) RMAX (kΩ) 0 153.8063 158.2144 162.7327 30 37.1428 37.6431 38.1463 1 146.0956 150.1651 154.3326 31 35.5329 36.0351 36.5408 2 138.8168 142.5725 146.4152 32 34.0011 34.5041 35.0111 3 131.9431 135.4081 138.9502 33 32.5433 33.0462 33.5534 4 125.4497 128.6453 131.9091 34 31.1555 31.6573 32.1640 5 119.3135 122.2594 125.2655 35 29.8340 30.3339 30.8392 6 113.5129 116.2273 118.9947 36 28.5760 29.0734 29.5764 7 108.0276 110.5275 113.0739 37 27.3776 27.8717 28.3720 8 102.8388 105.1398 107.4814 38 26.2356 26.7260 27.2228 9 97.9288 100.0454 102.1974 39 25.1472 25.6332 26.1261 10 93.2812 95.2267 97.2031 40 24.1094 24.5907 25.0792 11 88.8803 90.6673 92.4810 41 23.1198 23.5960 24.0796 12 84.7119 86.3519 88.0148 42 22.1759 22.6466 23.1249 13 80.7624 82.2661 83.7894 43 21.2753 21.7401 22.2129 14 77.0190 78.3963 79.7903 44 20.4158 20.8746 21.3416 15 73.4700 74.7302 76.0043 45 19.5953 20.0478 20.5088 16 70.1042 71.2558 72.4189 46 18.8120 19.2580 19.7126 17 66.9112 67.9620 69.0224 47 18.0638 18.5032 18.9514 18 63.8812 64.8386 65.8039 48 17.3492 17.7818 18.2234 19 61.0050 61.8759 62.7530 49 16.6663 17.0921 17.5269 20 58.2739 59.0647 59.8601 50 16.0137 16.4325 16.8605 21 55.6798 56.3961 57.1160 51 15.3899 15.8016 16.2227 22 53.2152 53.8628 54.5127 52 14.7934 15.1981 15.6122 23 50.8732 51.4569 52.0422 53 14.2230 14.6205 15.0277 24 48.6469 49.1715 49.6969 54 13.6773 14.0677 14.4678 25 46.5300 47.0000 47.4700 55 13.1552 13.5385 13.9316 26 44.4567 44.9360 45.4159 56 12.6556 13.0318 13.4178 27 42.4868 42.9737 43.4618 57 12.1774 12.5465 12.9255 28 40.6147 41.1075 41.6021 58 11.7195 12.0815 12.4536 29 38.8351 39.3323 39.8319 59 11.2810 11.6361 12.0011 30 37.1428 37.6431 38.1463 60 10.8610 11.2091 11.5673 © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 21 AN-9090 APPLICATION NOTE Table 14. R-T Table of NTC Thermistor (1-2) TNTC(°C) RMIN (kΩ) RTYP (kΩ) RMAX (kΩ) T (°C) RMIN (kΩ) RTYP (kΩ) RMAX (kΩ) 61 10.4594 10.8007 11.1520 91 3.6675 3.8463 4.0334 62 10.0746 10.4091 10.7536 92 3.5505 3.7253 3.9084 63 9.7058 10.0336 10.3714 93 3.4377 3.6087 3.7879 64 9.3522 9.6734 10.0046 94 3.3290 3.4963 3.6716 65 9.0133 9.3279 9.6525 95 3.2242 3.3878 3.5593 66 8.6882 8.9963 9.3145 96 3.1235 3.2836 3.4515 67 8.3764 8.6782 8.9899 97 3.0264 3.1830 3.3473 68 8.0773 8.3727 8.6782 98 2.9328 3.0860 3.2468 69 7.7902 8.0795 8.3787 99 2.8425 2.9923 3.1497 70 7.5147 7.7979 8.0910 100 2.7553 2.9019 3.0559 71 7.2496 7.5268 7.8138 101 2.6712 2.8146 2.9654 72 6.9950 7.2663 7.5474 102 2.5901 2.7303 2.8779 73 6.7505 7.0160 7.2913 103 2.5117 2.6489 2.7933 74 6.5157 6.7755 7.0450 104 2.4360 2.5703 2.7117 75 6.2901 6.5443 6.8082 105 2.3630 2.4943 2.6327 76 6.0739 6.3227 6.5810 106 2.2921 2.4206 2.5560 77 5.8662 6.1096 6.3624 107 2.2236 2.3493 2.4819 78 5.6665 5.9046 6.1521 108 2.1575 2.2805 2.4102 79 5.4745 5.7075 5.9498 109 2.0936 2.2139 2.3409 80 5.2899 5.5178 5.7549 110 2.0319 2.1496 2.2739 81 5.1129 5.3358 5.5680 111 1.9725 2.0877 2.2094 82 4.9426 5.1607 5.3879 112 1.9151 2.0278 2.1470 83 4.7788 4.9921 5.2145 113 1.8596 1.9699 2.0866 84 4.6211 4.8299 5.0475 114 1.8060 1.9139 2.0282 85 4.4694 4.6736 4.8866 115 1.7541 1.8598 1.9716 86 4.3228 4.5226 4.7310 116 1.7042 1.8076 1.9171 87 4.1817 4.3771 4.5811 117 1.6559 1.7572 1.8644 88 4.0459 4.2369 4.4366 118 1.6092 1.7083 1.8134 89 3.9150 4.1019 4.2973 119 1.5640 1.6611 1.7639 90 3.7890 3.9717 4.1629 120 1.5203 1.6153 1.7161 © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 22 AN-9090 APPLICATION NOTE General Application Circuit Example & PCB Layout Guidance General Application Circuit Example Figure 35 shows a schematic of application circuit example. Control signals are connected directly to a MCU or UCC3818. VAO 15V line U4 KA224 3 OVP1 2 + 4 1 Note5 R29 20k R39 3.9K R38 12K R27(RX) 15K R26(RY) 1.8K R37 270K R25 330K R35 Note4 270K R23 R25+R24+R23(RZ) 270K 870K R36 270K R24 270K 11 C28 C27 101 104 OVP2 15V line N.C Boost PFC SPM® FPAB30BH60B (10) V(TH) R31 6.8K OVP1 (9) R(TH) P (21,22) DCP TP L (24) R2 TP PR (25) R1 TP J1 R19 C20 20K 101 C19 333 Vcc VAO VAC- R20 4.7k OVP2 VFO R21 100R PWM (8) CSC C(SC) (7) CFOD CFOD (6) VFO VFO (5) IN(WL) IN R (26) OUT AC1 TP S (27) AC2 TP Note8 15V line Csc NTC Vref C26 104 600V Snubber cap (11,12) Vg VAC 15V line C25 C21 102 102 (2,3,4) COM COM (1) VCC VCC C22 C24 220uF/35V 105 +15V GND MC7805 15V line C29 105 R40 2mΩ 5W shunt DCN TP N(13~16) H/W OC part 15V line Vcc U5 MC7805C NR (17~20)) Note1 R28 1.8K R22 1K Note7 R41 20mΩ (Shunt) OC level VAC- C23 102 Note2,3 D5 LED Power GND Signal GND 15V line VAC D2 TLP181 R32 18K R30 18K R34 18K R33 18K D1 DF08S + ~ - ~ Note6 Figure 35. Example of Application Circuit for Boost PFC SPM 3 Series Notes: 7. The ceramic capacitor placed between VCC-COM (C24, 105) needs to be over 100 nF and mounted as close to the pins as possible. 8. Over-current level is 50 A because the value of shunt resistor used is 10 mΩ. 9. If OCP of SPM is not used, R28 and C23 should not be used and R41 should be zero Ω. 10. Two-level OVP can be also implemented. The DC-link voltage changes slowly because of its large capacitance and, therefore, OVP does not need a fast response. It is optional to activate the OVP of the PFC controller. The selected component values of the evaluation board are: RX = 15 [KΩ], RY = 1.8 [KΩ], RZ = 870 [K] OVP Level 1 – PFC When an over-voltage situation occurs, the PFC stops operating and generates a fault-out signal during fault-out duration time (set by CFOD). R X RY V R RY RZ 886.8 REF VDC _ PK X VREF 7.5 395[V ] R X RY RZ VDC _ PK R X RY 16.8 The over-voltage level can be adjusted by the value of VREF and resistance. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 23 AN-9090 APPLICATION NOTE OVP Level 2 – External PFC Controller The voltage level of OVP level 2 is higher than that of OVP level 1. RX V R RY RZ 886.8 REF VDC _ PK X VREF 7.5 443[V ] R X RY RZ VDC _ PK RX 15 Notes: 11. The PFC evaluation board can protect the power module from over-voltage situations. When over-voltage event occurs, the PFC stops operating and generates fault-out signal during fault-out duration time(set by CFOD). A comparator solution is recommended. 12. Power input AC voltage sensing circuit. Normally, the PFC IC needs to have the magnitude and phase of the input AC voltage. 13. If FAN6982 (PFC IC) is not used, R40 must be zero Ω. 14. An external anti-parallel diode must be used to prevent negative VCE voltage at light load and zero switching conditions. Otherwise, the IGBT in boost PFC SPM® 3 Package can be damaged due to repetitive reverse avalanches. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 24 AN-9090 APPLICATION NOTE Print Circuit Board (PCB) Layout Guidance Figure 36. Print Circuit Board (PCB) Layout Guidance © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 25 AN-9090 APPLICATION NOTE Experiment Results Appendix Test An external anti-parallel diode must be used to prevent negative VCE voltage at light-load and zero-switching conditions; otherwise, the boost PFC SPM® 3 series can be damaged by repetitive reverse avalanches. Table 15. Test Conditions (FPAB30BH60B) Item Condition VCC VAC VPN Current (Simulation Results) Load TA Switching fSW Shunt Resistor Cooler Snubber Capacitor 15 V 172 V / 268 V Target Voltage 380 V 30 Apeak (TC < 108°C at TJ =150°C, VI=220 V, VPN=400 V) Electronic Load 25 °C 22 kHz 10 mΩ, OCP Level 50 A Not Used Film Capacitor 105 Boost PFC of PFC-SPM P Inductor 15V 220µF VDC = 300V VCC 0.1µF IN Switching Pulse LO COM N Figure 39. Circuit without Anti-Parallel Diodes Test Results Boost PFC of PFC-SPM P Inductor 15V 220µF VDC = 300V VCC 0.1µF IN Switching Pulse LO COM N Figure 40. Circuit with Anti-Parallel Diodes Figure 37. Input AC 171.8 V, Output DC 30 Apeak, DC Link 375 V (CH3: Input Voltage [200 V/div], CH4: Input Current [10 A/div]) Figure 41. No Anti-Parallel Diodes Figure 38. Input AC 268.7 V, Output DC 30 Apeak, DC Link 376.6 V (CH3: Input Voltage [200 V/div], CH4: Input Current [10 A/div]) Table 16. Test Result (FPAB30BH60B) Waveform VAC [VRMS] VPN [V] fSW [kHz] Figure 37 Figure 38 171.8 268.7 375.0 376.6 22.0 22.0 TA [°C] TC [°C] 25.0 25.0 76.8 64.8 Figure 42. With Anti-Parallel Diodes (FRD 600 V 1A) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 www.fairchildsemi.com 26 AN-9090 APPLICATION NOTE Related Resources FPAB30BH60B − PFC SPM® 3 Series Ver.2 for 1-Phase Boost PFC FPAB20BH60B − PFC SPM® 3 Series Ver.2 for 1-Phase Boost PFC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.0 • 5/13/13 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 27