ML4828 - Rochester Electronics

REI Datasheet
ML4828
BiCMOS Phase Modulation/Soft Switching Controller
The ML4828 is a complete BiCMOS phase modulation control IC suitable for full bridge soft switching
converters. Unlike conventional PWM circuits, the phase modulation technique allows for zero
voltage switching (ZVS) transitions and square wave drive across the transformer. The IC modulates
the phases of the two sides of the bridge to control output power.
The ML4828 can be operated in either voltage or current mode. Both cycle-by-cycle current limit,
integrating fault detection, and soft start reset are provided. The under-voltage lockout circuit features
a 1.5V hysteresis with a low starting current to allow off-line start up with a bleed resistor. A shutdown
function powers down the IC, putting it into a low quiescent state.
Rochester Electronics
Manufactured Components
Rochester branded components are
manufactured using either die/wafers
purchased from the original suppliers
or Rochester wafers recreated from the
original IP. All recreations are done with
the approval of the OCM.
Parts are tested using original factory
test programs or Rochester developed
test solutions to guarantee product
meets or exceeds the OCM data sheet.
Quality Overview
•
•
•
•
ISO-9001
AS9120 certification
Qualified Manufacturers List (QML) MIL-PRF-38535
• Class Q Military
• Class V Space Level
Qualified Suppliers List of Distributors (QSLD)
•
Rochester
is a critical supplier to DLA and
meets all industry and DLA standards.
Rochester Electronics, LLC is committed to supplying
products that satisfy customer expectations for
quality and are equal to those originally supplied by
industry manufacturers.
The original manufacturer’s datasheet accompanying this document reflects the performance
and specifications of the Rochester manufactured version of this device. Rochester Electronics
guarantees the performance of its semiconductor products to the original OEM specifications.
‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be
based on product characterization, design, simulation, or sample testing.
© 2014 Rochester Electronics, LLC. All Rights Reserved 01202014
To learn more, please visit www.rocelec.com
May 1997
ML4828*
BiCMOS Phase Modulation/Soft Switching Controller
GENERAL DESCRIPTION
FEATURES
The ML4828 is a complete BiCMOS phase modulation
control IC suitable for full bridge soft switching converters.
Unlike conventional PWM circuits, the phase modulation
technique allows for zero voltage switching (ZVS)
transitions and square wave drive across the transformer.
The IC modulates the phases of the two sides of the bridge
to control output power.
■
■
■
■
The ML4828 can be operated in either voltage or current
mode. Both cycle-by-cycle current limit, integrating fault
detection, and soft start reset are provided. The undervoltage lockout circuit features a 1.5V hysteresis with a
low starting current to allow off-line start up with a bleed
resistor. A shutdown function powers down the IC, putting
it into a low quiescent state.
■
■
■
The circuit can be operated at frequencies up to 1MHz.
The ML4828 contains four high current CMOS outputs
which feature high slew rate with low cross conduction.
5V BiCMOS for low power and high frequency
(1MHz) operation
Full bridge phase modulation zero voltage switching
circuit with independent programmable delay times
Current or voltage mode operation capability
Cycle-by-cycle current limiting with integrating fault
detection and restart delay
Can be externally synchronized
Four 3Ω CMOS output drivers
Under-voltage lockout circuit with 1.5V hysteresis
*Some Packages Are End Of Life
BLOCK DIAGRAM
VREF
VCC
14
SYNC RT
6
3
5
2.5V REF
SDN 19
OSC
UVLO
EA+ 10
+
9
–
EA–
ERROR
AMP
DRIVER
18 A1
DRIVER
16 A2
DRIVER
15 B1
DELAY A
ISS
Q
8
–
RAMP 11
+
EAO
CT
4
ΦMOD
T
Q
SS 7
2.5V
1.25V
Q
S
Q
R
+
–
R
Q
S
Q
DELAY B
FAULT
LOGIC
RST 12
+
ILIM 20
1V
ILIM
IRST
DRIVER
13 B2
–
17
1
2
GND
RA
RB
REV. 1.0 10/10/2000
ML4828
PIN CONNECTION
ML4828
20-Pin DIP (P20)
20-Pin SOIC (S20)
RA
1
20
ILIM
RB
2
19
SDN
RT
3
18
A1
CT
4
17
GND
REF
5
16
A2
SYNC
6
15
B1
SS
7
14
VCC
EA0
8
13
B2
EA–
9
12
RST
EA+
10
11
RAMP
TOP VIEW
PIN DESCRIPTION
PIN
NAME
DESCRIPTION
PIN
NAME
DESCRIPTION
1
RA
A1 and A2 delay programming
resistor.
11
RAMP
RC network for phase modulator
ramp input.
2
RB
B1 and B2 delay programming
resistor .
12
RST
RC network for reset and integrating
fault detect.
3
RT
Oscillator charge current
programming resistor.
13
B2
B2 driver output.
14
CT
Oscillator timing capacitor.
VCC
Power supply
4
15
B1
B1 driver output.
5
REF
2.5V reference voltage.
16
A2
A2 driver output.
6
SYNC
Synchronization input to oscillator.
17
GND
Ground.
7
SS
Soft start capacitor connection.
18
A1
A1 driver output.
8
EAO
Error amplifier output.
19
SHDN
Active low device shutdown.
9
EA-
Error amplifier inverting input.
20
EA+
Error amplifier non-inverting input.
ILIMIT
Current limit control input
10
2
REV. 1.0 10/10/2000
ML4828
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
VCC .................................................................................................. 7V
Output Current, Source or Sink (A1, A2, B1, B2)
Pulse (0.5 µs) ......................................................... 1.0A
Analog Inputs (EA+, EA–, EAO,
RST, RAMP, RST)............................ –0.3V to VCC + 0.3V
RT Source Current .................................................... –1mA
Error Amplifier Output Current ................................ ±2mA
Soft Start Discharge Current ...................................... 5mA
CT Charging Current ................................................. –1mA
Junction Temperature .............................................. 150°C
Storage Temperature Range ...................... –65°C to 150°C
Lead Temperature (Soldering 10 sec.) ...................... 260°C
Thermal Resistance (θJA)
Plastic DIP ........................................................ 67°C/W
Plastic SOIC ..................................................... 95°C/W
OPERATING CONDITIONS
Temperature Range
ML4828CX ................................................. 0°C to 70°C
ML4828IX ............................................... –40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RA = RB = 33.3kΩ, RT = 16kΩ, CT = 270PF, VCC = 5V, TA = Operation Temperature Range
(Notes 1,2)
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
340
360
380
kHz
4
5.3
%/V
OSCILLATOR
Initial Accuracy
TA = 25°C
Voltage Stability
4.5V < VCC < 5.5V
Temperature Stability
2
Total Variation
Line, temp.
325
CT Discharge Current
VCT = 2V
1.15
%
400
kHz
1.5
mA
Ramp Peak
2.6
V
Ramp Valley
1.12
V
REFERENCE
Initial Accuracy
TA = 25°C, IO = 250µA
Line Regulation
Load Regulation
2.475
2.5
2.525
V
4.5V < VCC < 6.5V
±0.2
±1
%/V
100µA to 1mA
±0.5
±6
mV
Temperature Stability
0.45
Total Variation
Line, Load, & Temp
Long Term Stability
TJ = 125°C, 1000 hrs
Short Circuit Current
VREF = 0V
2.44
%
2.54
V
5
25
mV
–23
–35
mA
–20
20
mV
0
1.75
V
–10
ERROR AMPLIFIER
Input Offset Voltage
Input Common-Mode Range
Open Loop Gain
1V < VO < 2.7V
60
80
dB
PSRR
4.5V < VCC < 6.5V
60
80
dB
Output Sink Current
VO = 0.5V
1.2
1.9
mA
Output Source Current
VO= 2.7V
–0.35
–1.1
mA
Output High Voltage
ISOURCE = –500µA
2.6
2.85
V
Output Low Voltage
ISINK = 500µA
0.1
0.2
V
Unity Gain Bandwidth
7
10
MHz
Slew Rate
5
10
V/µs
REV. 1.0 10/10/2000
3
ML4828
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNITS
0
0.5
0.9
V
50
80
ns
95
mA
–25
–50
µA
6
10
13.2
mA
0.9
1.0
1.1
V
PHASE MODULATOR
EAO Zero Duty Cycle Threshold
VRT = 0V
RAMP Delay to Output
RAMP Discharge Current
48
SOFT-START
Charge Current
VSS = 4V
Discharge Current
VSS = 1V
CURRENT LIMIT/SHUTDOWN
Current Limit Threshold
Pin 20 Delay to Output
(Note 1)
50
ns
Pin 12 Shutdown Threshold
1.0
1.1
1.5
V
Pin 12 Restart Threshold
2.2
2.4
2.6
V
Pin 12 Charging Current
–350
–460
–550
µA
SDN Shutdown Threshold
1.05
1.6
2.05
V
0.01
0.1
0.1
0.3
V
V
OUTPUT
Output Low Level
IOUT = 20 mA
IOUT = 100 mA
Output High Level
IOUT = –20 mA
IOUT = –100 mA
Rise/Fall Time
CL = 1000pF, (Note 1)
ZVS Programmable Delay
4.9
4.6
240
Delay Mismatch
4.95
4.7
V
V
5
7
ns
280
315
ns
0
RA/RB Reference Voltage
ns
2.45
2.5
2.55
V
Start Threshold
5.1
5.85
6.6
V
Stop Threshold
4.1
4.2
4.3
V
0.6
1
mA
100
500
µA
5
7
mA
UNDER VOLTAGE LOCKOUT
SUPPLY
Start Up Current
VCC < 6V
Shutdown Current
ICC
Note 1:
Note 2:
4
VCC = 5V, CL = 1000pF, TA = 25°C
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
VCC must be brought above the UVLO start voltage (6V) before dropping to VCC = 5V to ensure start-up.
REV. 1.0 10/10/2000
ML4828
FUNCTIONAL DESCRIPTION
charged to +VIN. At this time, Q3 turns on at zero
voltage. The transformer is now effectively shorted
through Q1 and Q3, with the primary magnetizing
current circulating in the loop formed by the
transformer primary, Q1, and Q3.
PHASE MODULATOR
The ML4828 controls the power of a full bridge power
section by modulating the phases of the switches of the A
and B sides (Figure 1). The power cycle starts with A2 and
B1 high, as shown in the timing diagram (Figure 2).
4. CLOCK then goes high and A2 goes low, while A1
remains low for time tDA, which is set by the resistor
connected from RA (pin 1) to GND. During this time,
both Q1 and Q4 are OFF. The primary magnetizing
current discharges the parasitic capacitances of Q1 and
Q4 to GND.
1. With A2 and B1 high, Q1 and Q2 are ON. Current
flows through the primary of the transformer, and
power is delivered to the output through the secondary
winding (not shown).
2. After either the ΦMOD or ILIM comparator trips, B1
goes low, turning off Q2. Energy in the primary winding
charges the parasitic capacitances of Q2 and Q3 to
+VIN during tDB.
3. B2 goes high after time tDB, which is set by the resistor
connected from RB (pin 2) to GND. tDB should be set
large enough such that the source of Q3 has been
5. A1 goes high after time tDA. At this point, the drain of
Q4 is discharged to GND, and Q4 turns on at zero
voltage. With both Q3 and Q4 ON, a new power cycle
starts, and power is delivered to the output.
The above sequence is then repeated with the roles of
side A and B interchanged.
The ML4828 can also be used in current mode by sensing
the load current on the RAMP input (pin 11).
+VIN
A2
Q3
TB
B2
Q1
TA
B1
LLEAKAGE
ML4828
B
A
TRANSFORMER
Q2
Q4
TB
A1
TA
ILIM
RSENSE
Figure 1. Simplified diagram of Phase Modulated power Outputs.
CT
CLOCK
A2
tDA
A1
tDA
tDA
B1
tPD1
tDB
tDB
tPD1
tPD1
B2
tDB
B
A
Figure 2. Phase Modulation control waveforms (Shaded areas indicate a power cycle).
REV. 1.0 10/10/2000
5
ML4828
SETTING THE OSCILLATOR FREQUENCY
ERROR AMPLIFIER
The ML4828 switching frequency is determined by the
charge and discharge times of the network connected to
the RT and CT pins. Figure 3 shows the relationships
between the internal clock and the charge and discharge
times.
The ML4828 error amplifier has a 10MHz bandwidth and
a 10V/µs slew rate. Figure 4 gives the Bode plot of the
error amplifier.
100
180
80
GAIN
RAMP VALLEY
1.25V
tCHARGE
135
GAIN
60
PHASE
90
40
20
tDISCHARGE
45
PHASE (Degrees)
RAMP PEAK
2.5V
0
INTERNAL
CLOCK
–20
100
1K
10K
100K
1M
FREQUENCY
10M
100M
0
Figure 3. Internal Oscillator Timing.
Figure 4. Error Amplifier Open-Loop Gain
and Phase vs. Frequency.
The frequency of the oscillator is:
fOSC =
1
t CHARGE + tDISCHARGE
(1)
The ramp peak is 2.5V and the ramp valley is 1.25V,
giving a ramp range of 1.25V. The charging current is set
externally through the resistor RT:
ICHARGE = 2.5V
RT
(2)
tDISCHARGE =
CT × 1.25V CT × R T
=
ICHARGE
2
CT × 1.25V CT × 1.25V
=
IDISCHARGE
1.4mA
(3)
(4)
The oscillator frequency can then be found by substituting
the results of equations 3 and 4 into equation 1. This
frequency activates a T flip-flop which generates the
output pulses. The T flip-flop acts as a frequency divider
(÷2), so the output frequency will be:
fOUT =
6
fOSC
2
The ML4828 has four high-current CMOS output drivers,
each capable of 1A peak output current. These outputs
have been designed to quickly switch the gates of power
MOSFET transistors via a gate drive transformer. For higher
power applications, the outputs can be connected to
external MOSFET drivers.
The output phase delay times are set by charging an
internal 6.7pF capacitor up to the REF voltage (2.5V) via a
current that is externally programmed through RA and R B,
for the side A and side B drivers, respectively. The
charging current and delay time for side A are given by:
while the discharging current is fixed at 1.4 mA. The
charge and discharge times can be determined by:
t CHARGE =
OUTPUT DRIVERS
IA = 2.5V
RA
(6)
tDA = 6.7pF × R A
(7)
The same equations can be applied to RB. For example,
with RA = 33kΩ:
tDA = 6.7pF × 33kΩ = 220ns
(8)
(5)
REV. 1.0 10/10/2000
ML4828
V+
ISWITCH
I1
7
SS
CSS
TERMINATE
PWM CYCLE
20
R1
ILIM
+
C1
1V
–
S
RSENSE
V+
Q
IRST
12
RRST
R
RST
CLOCK
CRST
+
2.5V
1.25V
INHIBIT
OUTPUT
–
UNDER-VOLTAGE
LOCKOUT
Figure 5. Over-Current, Soft-Start, and Integrating Fault Detect Circuits.
SOFT START TIME CONSTANT
During start up, the output voltage is much lower than the
steady state value. Without soft start circuitry, the error
amplifier output (EAO) would swing all the way to the
upper limit and the phase modulator would issue pulses
with full duty cycle, possibly causing output overshoot. To
ensure smooth start up, EAO (pin 8) is pulled low and
then gradually released through the charging of an
external soft start capacitor connected to SS (pin 7). The
soft start charging current is internally set at 25µA. Hence,
EAO will rise with a time constant of:
dv = 25µA
dt
CSS
(9)
For example, with CSS = 25µF, the soft start rate of change
will be:
dv = 25µA = 1V
dt 25µF
s
(10)
FAULT TIME CONSTANT AND RESTART DELAY
Figure 5 shows the internal circuitry and external
components involved in fault detection. During normal
operation, RST (pin 12) is discharged to ground through
the external resistor RRST. The ILIM comparator has a
threshold of 1V. RSENSE is selected so that the voltage
across it will be equal to the ILIM threshold at the
maximum desired ISWITCH current. When the voltage
across RSENSE exceeds 1V, the ILIM comparator trips,
terminating the present power cycle, and at the same time
activating the fault logic to turn on the 500µA current
REV. 1.0 10/10/2000
source IRST. This current charges the reset capacitor C RST.
For proper design, RRST should be very large (in the order
of 100kΩ). This will cause nearly all of the IRST current
(approximately 500µA) to go into charging CRST at a rate of:
dv = 500µA
dt
CRST
(11)
in volts per second. IRST will be turned off at the beginning
of the next clock cycle. If the current limit condition is
removed, RST will be gradually discharged to ground,
and normal operation resumes as shown in Figure 6.
1V
V(PIN 20)
2.5V
V(PIN 12)
Figure 6. ILIM and Resulting RCRST
Waveforms During Load Surge.
7
ML4828
If the current limit condition persists, then IRST will be
reactivated, thus charging CRST to a higher level as shown
in Figure 7. Eventually, the voltage at RST will exceed
2.5V, and the soft start comparator will trip, shutting down
all power drivers and inhibiting any further delivery of
power. At the same time, the soft start capacitor CSS is
discharged to prepare for the next start up cycle.
dv = 500µA = 20 V
dt
25µF
s
(14)
tD(RST ) = (240kΩ × 25µF) × 1.39 = 8.3s
(15)
and
Since the threshold for shutdown is 2.5V, the controller
will shut down after approximately 125ms. After the
converter recovers form the current limit condition, the
controller will reactivate after 8.3s.
1V
V(PIN 20)
UNDERVOLTAGE LOCKOUT
2.5V
During start-up, the ML4828 draws very little current
(typically 150µA) and VREF is disabled. When VCC rises
above 6.0V, the internal circuitry and VREF are enabled,
and will stay enabled until VCC falls below the 4.5V UV
lockout threshold.
V(PIN 12)
Figure 7. ILIM and Resulting RCRST
Waveforms During Short Circuit.
SHUTDOWN FUNCTION
During the ILIM shutdown, IRST is turned off, and CRST is
discharged through RRST with a time constant of:
tRST = RRST × CRST
(12)
When the condition causing the current limit is removed,
RRST will discharge CRST with a time constant of tRST.
When the voltage at RST (pin 12) drops to 1.25V, the soft
start comparator and the converter will undergo a start up
cycle. The restart delay (tD(RST)) is given by:
tD(RST ) = tRST × 1.39
8
For example, with CRST = 25µF and RRST = 240kΩ:
The ML4828 can be externally shut down by bringing
SDN (pin 19) low. The shutdown threshold (VSD) is given
by
VSD = 0.33 × VCC
(16)
For example, if VCC= 5V, then VSD = 1.67V. As long as
2.4V < VCC < 6.0V, the SDN pin will be TTL compatible.
(13)
REV. 1.0 10/10/2000
ML4828
PHYSICAL DIMENSIONS inches (millimeters)
Package: S20
20-Pin SOIC
0.498 - 0.512
(12.65 - 13.00)
20
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
PIN 1 ID
1
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
REV. 1.0 10/10/2000
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE
0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.007 - 0.015
(0.18 - 0.38)
9
ML4828
PHYSICAL DIMENSIONS inches (millimeters) (Continued)
Package: P20
20-Pin PDIP
1.010 - 1.035
(25.65 - 26.29)
20
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
0.060 MIN
(1.52 MIN)
(4 PLACES)
1
0.055 - 0.065
(1.40 - 1.65)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
10
0.100 BSC
(2.54 BSC)
0.016 - 0.022
(0.40 - 0.56)
SEATING PLANE
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
REV. 1.0 10/10/2000
ML4828
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
ML4828CP
ML4828CS
0°C to 70°C
0°C to 70°C
ML4828IP
ML4828IS
–40°C to 85°C
–40°C to 85°C
PACKAGE
20-Pin DIP (P20)
20-Pin DIP (S20) (EOL)
20- Pin DIP (P20) (EOL)
20- Pin SOIC (S20) (EOL)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
www.fairchildsemi.com
REV. 1.0 10/10/2000
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
© 2000 Fairchild Semiconductor Corporation
11