C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications ADVANTAGES • • • • • • • • Suitable for applications with or without cable such as USB chargers Can meet USB OMTP undershoot requirement < 30 mW no-load power consumption (5* rating) Low cost bipolar primary switch Tight tolerance CV/CC operation Low component count High efficiency (Energy Star 2.0 compliance with margin) Programmable maximum switching frequency C2161DX2 C2162DX2 SOT23-6 FEATURES • • • • • Advanced primary sensing controller achieves true CV/CC output characteristic without opto-coupler Full featured protection for over-temperature, input over-voltage, input under-voltage, output short-circuit Advanced PFM/PWM control and quasi-resonant switching for increased efficiency Switching timing jitter spreads RF spectral emissions, eases EMC compliance SOT23-6 package APPLICATIONS USB chargers; for mobile phones, digital camera and MP3 players. Universal standby and auxiliary power supplies up to 8 W using C2162DX2 (up to 4 W using C2161DX2). Figure 1: Typical Application Circuit Product data © Cambridge Semiconductor Ltd 2010 Page 1 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications BLOCK DIAGRAM Figure 2: C2161DX2 and C2162DX2 Block Diagram PIN DEFINITIONS SOT23-6 CS 1 6 FB GND 2 5 VDD ED 3 4 RC Figure 3: C2161DX2 and C2162DX2 Pin Assignment VDD Pin The VDD pin supplies power to the chip and dictates the operating mode (Run or Sleep). FB Pin The FB pin is used to sense the transformer winding voltage waveform, scaled and AC-coupled by an external RC network (Rfb1, Rfb2 and Cfb in Figure 4). CS Pin The CS pin senses the primary switch current via the current sensing resistor (Rcs in Figure 4). RC Pin The RC timing network connected to the RC pin (shown as Rosc, Cosc in Figure 4) defines both the required maximum switching frequency FMAX and the cable compensation. ED Pin The ED pin is connected to the emitter of the external bipolar junction transistor (Q1 in Figure 4). GND Pin The GND pin provides the ground reference. Product data © Cambridge Semiconductor Ltd 2010 Page 2 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications TYPICAL APPLICATION The C2161DX2 and C2162DX2 controllers are intended primarily for 5 V USB chargers meeting the 5-star energy saving requirements, but are equally applicable to other off-line applications up to 8 W requiring low standby power and high efficiency. A high degree of configurability allows a wide range of applications to be met at minimum cost. A typical application circuit is shown in Figure 4. NP NS NA NF Figure 4: Universal Input 4 W Charger Typical 4 W Charger Performance Input VIN 85 - 265 V ac Output VOUTNOM 5 V dc (± 5%) IOUTNOM 800 mA dc (-0/+10%) Cable compensation GCAB 1% Average Typical Efficiency (including cable) KEFF > 70% No-load input power consumption PINSTBY < 30 mW Over-temperature protection (OTP) TSH 115 ºC Start-up time tSTART <1s Product data © Cambridge Semiconductor Ltd 2010 Page 3 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications PRINCIPLE OF OPERATION Parameters used in equations are explained in the Electrical Characteristics section. Power-Up/Power-Down Sequences The C2161DX2 and C2162DX2 controllers are powered via the VDD pin. When the line input is first applied, a small amount of current (IDDSLEEP) is drawn from the rectified mains input via a high value start up resistor (Rht in Figure 4). When the voltage on the VDD pin (VDD) reaches a level VDDRUN the controller wakes up, demands more supply current (IDDREG) and enters the Initialise mode (see Figure 5). The controller stays in Initialise for a short time during which internal circuits are enabled and then changes to Run mode. In Run mode, the controller uses an internal shunt regulator to regulate VDD at VDDREG. If the VDD pin voltage drops ΔVDDSLEEP below VDDREG the controller goes back into Sleep mode, reducing the supply current demand. The system will restart when input power is restored and VDD reaches VDDRUN again. To achieve a smooth power up sequence the VDD reservoir capacitor (Cdd in Figure 4) needs to be large enough to sustain the supply over the Initialise period and the first few cycles of Run mode, until the auxiliary rail voltage supply is established. VDDRUN ΔVDDSLEEP VDDREG VDD tINIT Off Sleep Initialise Run Sleep Off Figure 5: VDD Pin Waveform (VDD) Mode Description Sleep From initial application of power or from Run mode if VDD falls below ΔVDDSLEEP below VDDREG, the controller changes to Sleep mode. Non-essential controller circuits are powered down and the external switching transistor (Q1) is held off. Exit from Sleep mode occurs when VDD rises above VDDRUN and the controller moves to the Initialise mode. Initialise When Initialise mode is entered, internal controller circuits are initialised and two clock cycles are issued, after which the controller changes from Initialise to Run mode. Run Converter operation continues. The shunt regulator controls VDD to VDDREG. If VDD falls ΔVDDSLEEP below VDDREG, the controller ceases power conversion and reverts to Sleep mode. Table 1: Summary of Controller Modes Product data © Cambridge Semiconductor Ltd 2010 Page 4 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications Constant Voltage and Constant Current (CV/CC) Operation The C2161DX2 and C2162DX2 controllers achieve constant voltage and constant current output within tight limits without the need for any secondary sensing components, by sensing the primary side waveforms of transformer voltage and primary switch current. Figure 6 shows the output characteristics of a typical phone charger implemented with the C2161DX2 and C2162DX2. VOUT (ICCMIN,VNOM) 100% 50% 30% 0 5% 50% 100% IOUT Figure 6: Achievable Charger Output Characteristic Using C2161DX2 and C2162DX2 Product data © Cambridge Semiconductor Ltd 2010 Page 5 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications Switching Waveforms Typical switching waveforms for the FB, CS and RC inputs are shown with the ED output in Figure 7. Figure 7: Typical Waveforms: ED, FB, CS, RC pins Constant Voltage (CV) Regulation Constant voltage regulation is achieved by sensing the FB input, which is AC coupled to the auxiliary winding of the transformer, as shown in Figure 4. The FB pin is internally biased to VFBBIAS. A typical voltage waveform seen on this pin is shown in Figure 7. The waveform is analysed and sampled at tSAMP to derive an estimate of the reflected output voltage. The tSAMP point is identified by the change in slope of the transformer auxiliary winding waveform (as sensed by the FB input) immediately prior to the zero crossing. The difference between the sampled voltage and the FB regulation voltage (ΔVFBREG) is used to derive the system power demand and close the voltage control loop. The regulated output voltage is determined by the selection of the potential divider resistors (Rfb1, Rfb2 in Figure 4) and the chosen transformer turns ratio. The total parallel combination of these resistors should be typically less than 120 Ω to prevent unwanted effects of stray capacitance. The tolerances of Rfb1 and Rfb2 affect output voltage regulation and would typically be chosen to be 1% or better. Values of Rfb1, Rfb2 and Cfb are given by the equations: Rfb2 = 120 Ω Cfb = 47nF ± 20% Product data © Cambridge Semiconductor Ltd 2010 ⎛ ⎞ N Rfb2⎜⎜ VOUTNOM F − ΔVFBREG ⎟⎟ NS ⎝ ⎠ Rfb1 = ΔVFBREG Page 6 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications Constant Current (CC) Regulation The current flowing through the transformer primary winding is sensed on the CS pin by the voltage generated across the current sensing resistor (Rcs in Figure 4). The voltage seen on the CS pin is a negative-going voltage waveform as shown in Figure 7. When the voltage on the CS pin exceeds a (negative) threshold VCSTHR, the primary switching transistor is rapidly turned off. The internal loop controller regulates the CS voltage threshold (VCSTHR in Figure 7) between VCSMIN and VCSMAX, based on the average CS input voltage and CC regulation set point (VCSCC) to achieve constant output current regulation. Blanking is provided for a period of tCSB1 to prevent false triggering due to leading edge spikes in the waveform. Constant Current regulation is determined by the transformer turns ratio and the value of Rcs. The value of Rcs is determined by the required output current (IOUT) and transformer primary-secondary turns ratio (NP/NS) according to the approximation: ⎛N Rcs ≈ ⎜⎜ P ⎝ NS ⎞⎛ VCSCC ⎟⎟⎜⎜ ⎠⎝ IOUT ⎞ ⎟⎟ ⎠ The tolerance of Rcs has a direct relationship to the accuracy of the output current limit and is typically chosen to be 1%. Cable Drop Compensation The C2161DX2 and C2162DX2 controllers adjust the output voltage of the power supply to compensate for the voltage drop seen in the output cable. However, the benefit of this IC is that it can minimize cable compensation to 1% suitable for USB applications. The amount of compensation applied (GCAB) is programmed by the value of the capacitor connected to the RC pin, (Cosc in Figure 4) according to the equation: Cosc = K CAB GCAB Drive Pulse and Frequency Modulation The C2161DX2 and C2162DX2 control both the primary switch peak current and the switching frequency in response to the power demanded by the application load. The controller ensures that power conversion is performed in discontinuous conduction mode (DCM) at all times. The switching frequency is varied depending on the actual power demand. The maximum switching frequency is set by FMAX. The C2161DX2 and C2162DX2 controllers do not have a minimum switching frequency. The full-load frequency FMAX (chosen in the range 40 to 66 kHz) is set by the equations: FMAX = 1 K OSC .τ RCOSC + t RCRST The oscillator time constant τRCOSC is controlled by external components Cosc, Rosc so that: τ RCOSC = R OSC .C OSC Duty Cycle Control The maximum duty cycle is set by the primary-secondary turns ratio (NP/NS) of the transformer (typically 16:1 for a 5 V output). For a typical universal input offline application, a maximum duty cycle of 50% is chosen for the minimum rectified supply voltage (typically 80 VDC). Product data © Cambridge Semiconductor Ltd 2010 Page 7 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications Soft Switching Zero current (quasi-resonant) switching is used to minimise the switching losses in the primary switch, thereby increasing efficiency and introducing frequency jitter, to spread the RF emissions spectrum. The primary switching BJT is turned on when the voltage across it is a minimum (as detected by the FB input), minimising the capacitive switching losses and reducing the RF emissions. Cascode Switching The primary switch is connected in cascode configuration to ensure fast and efficient switching using lowcost bipolar transistors, e.g. MJE13002, STX13003, STBV42, STBV45, TS13003MV. The slew rate of the ED drive pin is limited to minimise conducted and radiated EMI. Fast Load Step Response When a drop in output voltage is detected due to a large load step from no-load, the controller quickly ramps up output power. This prevents the output voltage from dropping further, as shown in Figure 8. The total voltage drop is determined by the application circuit and the no-load switching frequency (fNLP). fNLP Controller recovery 5V Output capacitor hold up Vout 4.1V 0.5A Iout 0A Figure 8: No-load to 0.5 A Load Step Recovery Protection Features Short-Circuit Protection If required, the application circuit can be forced to hiccup if the output is short-circuit. This is achieved by designing the auxiliary winding on the transformer (T1) so that the auxiliary rail voltage (at the cathode of Daux) is too low, allowing the VDD pin to fall by at least ΔVDDSLEEP below VDDREG. The controller will repeatedly switch between Sleep and Run modes, resulting in low power consumption. (When the shortcircuit condition is removed, the application returns to normal operation.) Mains Under Voltage Protection (UVP) and Over Voltage Protection (OVP) The regulated output voltage is reduced when the rectified input voltage falls outside the normal working voltage range, defined by VUVP and VOVP. The value is defined by the nominal output voltage (VOUTNOM), the primary-secondary turns ratio (NP/NS) and other IC parameters by the equation: VUVP ≈ VOUTNOM Product data © Cambridge Semiconductor Ltd 2010 NP ΔVFBUVP NS ΔVFBREG VOVP ≈ VOUTNOM Page 8 NP VFBBIAS NS ΔVFBREG DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications Over Temperature Protection (OTP) The on-chip OTP is triggered if the junction temperature exceeds the threshold TSH, shutting down the controller. To prevent possible damage to the PCB, the OTP prevents restarting until the temperature has dropped to (TSH – TSHHYST). Primary Switch Over Current Protection (OCP) The primary switch is turned off if the primary switch current exceeds a preset threshold VCSMAX, as sensed by the CS input, subject to the minimum on-time TONMIN. This gives pulse by pulse over current protection. Output Over Voltage Protection The switching operation is inhibited when the output voltage is above the nominal range, defined by VOUTOVP. The value is defined by the nominal output voltage (VOUTNOM) and the feedback OVP to regulation level ratio: VOUTOVP = VOUTNOM ⋅ GFBOVP Product data © Cambridge Semiconductor Ltd 2010 Page 9 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications ABSOLUTE MAXIMUM RATINGS CAUTION: Permanent damage may result if a device is subjected to operating conditions at or in excess of absolute maximum ratings. Parameter Symbol Condition Min Max Unit 4.5 V Supply voltage VDD -0.5 Supply current IDD -20 90 mA V FB input voltage VFB -0.5 VDD + 0.5 CS input voltage VCS -0.5 VDD + 0.5 V DC condition RC input voltage VRC -0.5 VDD + 0.5 V ED pin voltage VED -0.5 VDD + 0.5 V FB input current IFB -20 20 mA CS input current ICS -20 20 mA RC input current IRC -35 250 mA ED pin current IED C2161DX2 -20 400 mA C2162DX2 -20 650 mA Junction temperature TJ -25 125 °C Storage temperature TP -40 150 °C Lead temperature TL 260 °C 2 kV 500 V ESD withstand Soldering, 10 s Human body model, JESD22-A114 Charged device Model, ANSI-ESD-STM5.3.1 NORMAL OPERATING CONDITIONS Unless otherwise stated, electrical characteristics are defined over the range of normal operating conditions. Functionality and performance is not defined when a device is subjected to conditions outside this range and device reliability may be compromised. Parameter Symbol Supply voltage VDD Supply current IDD Condition Min Typ Max Unit 3.1 3.45 3.6 V 30 mA 66 kHz Full power switching frequency FNOM Transformer resonance frequency (in-circuit) FRES 300 TJ -25 Junction temperature Product data © Cambridge Semiconductor Ltd 2010 Full-load, application dependent Page 10 36 40 kHz 25 105 °C DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications ELECTRICAL CHARACTERISTICS Unless otherwise stated: 1. 2. 3. 4. Min and Max electrical characteristics apply over normal operating conditions. Typical electrical characteristics apply at TJ = TJ(TYP) and IDD = IDDREG(TYP). The chip is operating in Run mode. Voltages are specified relative to the GND pin. VDD Pin Parameter Supply voltage Symbol Condition Min Typ Max Unit VDDRUN To enter Initialise mode 3.6 4.0 4.45 V VDDREG In Run mode 3.3 3.45 3.6 V ΔVDDSLEEP Supply current Initialisation time IDDREG IDDSLEEP To enter Sleep mode (measured relative to VDDREG) -600 mV In Run mode 2.4 mA In Sleep mode 5.5 µA 3τRCOSC tINIT s FB Pin Parameter Symbol Condition Min FB bias voltage VFBBIAS Internal DC bias voltage 1.66 FB regulation level ΔVFBREG Measured relative to VFBBIAS T=25°C 394.5 FB slope detection threshold ΔVFB/Δt -280 FB input resistance RFBIN Effective input resistance 0 < VFB < VDD FB initialisation current IFBINIT VFB = 0 V FB OVP ratio GFBOVP FB UVP comparator threshold offset ΔVFBUVP Typ Max Unit 1.84 V 405 415.5 mV -200 -120 mV/μs 50 kΩ -1.8 mA 1.4 Measured relative to VFBBIAS 1.8 -135 mV RC Pin Parameter Symbol Condition Min Typ Maximum switching frequency FMAX Maximum frequency control factor KOSC Cable compensation GCAB Cable compensation factor KCAB 20 Oscillator reset time tRCRST 2.7 Product data © Cambridge Semiconductor Ltd 2010 30 Unit 66 kHz 10 % 0.31 220 pF < Cosc < 2.2 nF 1 Page 11 Max pF 3.8 µs DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications CS Pin Parameter Symbol CS input minimum threshold VCSMIN CS input maximum threshold VCSMAX CS turn-off response time tCSOFF CS Input Offset Condition Min Outside CS blanking time tCSB1 Typ Max Unit Minimum load -38 mV Over-current protection -182 mV Step ΔVCS: VCSMAX + 10 mV to VCSMAX - 10 mV 175 ns 0 µV ΔVCSOFF CS Input Leakage Current ICSLEAK -0.2 V < VCS < VDD CS input limit for CC operation (average) VCSCC F = 40 kHz, t1 = t2 = 12.5 μs, T=25°C Leading edge blanking time tCSB1 See Figure 7 -10 -32.5 -31.4 10 µA -30.3 mV 400 ns ED Pin Parameter Symbol Condition On-state resistance REDON IED < IED(MAX) Off-state current IEDOFF VED = VDD Minimum on-time tONMIN Product data © Cambridge Semiconductor Ltd 2010 Min Typ Max Unit 0.9 1.25 Ω 10 µA 575 Page 12 ns DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications THERMAL CIRCUIT PROTECTION Parameter Symbol Condition Min Typ Max Unit 105 115 125 °C Thermal shutdown temperature TSH At silicon junction Thermal shutdown hysteresis TSHHYST At silicon junction 30 °C PACKAGE THERMAL RESISTANCE CHARACTERISTICS Conditions: 1. Controller IC mounted on typical PCB (1.6 mm thick, 35 µm copper, CEM1); 2. θJB measured to pin terminal of device at the surface of the PCB. Package Junction-to-board θJB (Typical) Junction-to-ambient θJA (Typical) Units SOT23-6 60 170 °C / W PACKAGING AND ORDERING INFORMATION Package Marking The SOT23-6 package is marked with a short code indicating type and production lot as shown in Figure 9. Type code (PT or PU) Lot dependent code (varies) PXXX Figure 9: SOT23-6 Package Marking Ordering Type Package Marking Packing Form C2162DX2 SOT23-6 PUxx C2161DX2 SOT23-6 PTxx 7” Tape & Reel Shipping C2162DX2-TR7 13” Tape & Reel C2162DX2-TR13 7” Tape & Reel C2161DX2-TR7 13” Tape & Reel C2161DX2-TR13 For further package and ordering information, please contact CamSemi. Product data © Cambridge Semiconductor Ltd 2010 Page 13 DS-3785-1006 11-Jun-2010 C2161DX2 and C2162DX2 Datasheet Primary Sensing SMPS Controller For 5* USB Charging Applications DATASHEET STATUS The status of this Datasheet is shown in the footer. Always refer to the most current version. Datasheet Status Product Status Definition Product preview In development The Datasheet contains target specifications relating to design and development of the described IC product. Application circuits are illustrative only. Specifications are subject to change without notice. Preliminary In qualification The Datasheet contains preliminary specifications relating to functionality and performance of the described IC product. Application circuits are illustrative only. Specifications are subject to change without notice. Product data In production The Datasheet contains specifications relating to functionality and performance of the described IC product which are supported by testing during development and production. Application circuits are illustrative only. Specifications are subject to change without notice. CONTACT DETAILS Cambridge Semiconductor Ltd St Andrew’s House St Andrew’s Road Cambridge CB4 1DL United Kingdom Phone: Fax: Email: Web: +44 (0)1223 446450 +44 (0)1223 446451 [email protected] www.camsemi.com DISCLAIMER The product information provided herein is believed to be accurate and is provided on an “as is” basis. Cambridge Semiconductor Ltd (CamSemi) assumes no responsibility or liability for the direct or indirect consequences of use of the information in respect of any infringement of patents or other rights of third parties. Cambridge Semiconductor Ltd does not grant any licence under its patent or intellectual property rights or the rights of other parties. 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The products and circuits described herein are subject to the usage conditions and end application exclusions as outlined in Cambridge Semiconductor Ltd Terms and Conditions of Sale which can be found at www.camsemi.com/legal . Cambridge Semiconductor Ltd reserves the right to change specifications without notice. To obtain the most current product information available visit www.camsemi.com or contact us at the address shown above. Product data © Cambridge Semiconductor Ltd 2010 Page 14 DS-3785-1006 11-Jun-2010