RT8153C/D

RT8153C/D
Single Phase PWM Controller for CPU Core Power Supply
General Description
Features
The RT8153C/D is a single phase PWM controller with
integrated MOSFET drivers. Moreover, it is compliant with
Intel IMVP6.5 Voltage Regulator Specification to fulfill its
mobile CPU core and Render core voltage regulator
requirements. The RT8153C/D adopts G-NAVP (Green
Native AVP), which is a Richtek proprietary topology
derived from finite DC gain compensator constant on-time
mode, making it an easy setting PWM controller which
meets all Intel AVP (Active Voltage Positioning) mobile
CPU/Render requirements. The output voltage of the
RT8153C/D is set by a 7-bit VID code. The built in high
accuracy DAC converts the VID code into a voltage ranging
from 0V to 1.5V with 12.5mV per step. The system
accuracy of the controller can reach 1.5%.
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The part supports VID on the fly and mode change on the
fly functions that are fully compliant with IMVP6.5
specification. It operates in single phase and diode
emulation modes. It can reach up to 90% efficiency in
different modes according to different loading conditions.
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The RT8153C/D includes power good and thermal throttling
indicator and an additional clock enabling for CPU core
specification. The soft-start and output transition slew rate
is programmable by an external capacitor. It also features
complete fault protection functions including over voltage,
under voltage, negative voltage, over current and thermal
shutdown. The RT8153C/D is available in WQFN-32L 5x5
and WQFN-32L 4x4 small foot print packages.
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Single Phase PWM Controller with Integrated
MOSFET Driver
G-NAVPTM Control Topology
7-bit DAC with 0.8% DAC Accuracy
1.5% or 11.5mV System Accuracy
Fixed VBOOT 1.1V (Only for RT8153C CPU Core Only)
Fixed VBOOT 1.2V (Only for RT8153D CPU Core Only)
Current Monitor Output
Built-in Offset Programming for Platform
Differential Remote Voltage Sensing
Diode Emulation Mode at Light Load Condition
Programmable Output Transition Slew Rate Control
System Thermal Compensated AVP
Fast Transient Response
Load Line Enable/Disable
Power Good Indicator
Clock Enable Output (For CPU Core Only)
Thermal Throttling
Switching Frequency Up to 1MHz
OVP, UVP, OCP, OTP, UVLO, NVP
RoHS Compliant and Halogen Free
Ordering Information
RT8153C/D
Package Type
QW : WQFN-32L 5x5 (W-Type)
QW : WQFN-32L 4x4 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Applications
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IMVP 6.5 VCORE/Render
AVP Step-Down Converter
Notebook / Desktop Computer / Servers
Package Size
L : 5x5
S : 4x4
VBOOT
C : 1.1V
D : 1.2V
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
DS8153C/D-05 April 2011
Suitable for use in SnPb or Pb-free soldering processes.
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1
RT8153C/D
Marking Information
RT8153CLGQW
RT8153DLGQW
RT8153CLGQW : Product Number
RT8153CL
GQW
YMDNN
RT8153DLGQW : Product Number
RT8153DL
GQW
YMDNN
YMDNN : Date Code
RT8153CLZQW
RT8153DLZQW
RT8153CLZQW : Product Number
RT8153CL
ZQW
YMDNN
RT8153DLZQW : Product Number
RT8153DL
ZQW
YMDNN
YMDNN : Date Code
RT8153CSGQW
EJ= : Product Code
YMDNN : Date Code
EJ=YM
DNN
RT8153CSZQW
YMDNN : Date Code
RT8153DSZQW
EH : Product Code
EH YM
DNN
YMDNN : Date Code
RT8153DSGQW
EH= : Product Code
EH=YM
DNN
YMDNN : Date Code
EJ : Product Code
YMDNN : Date Code
EJ YM
DNN
YMDNN : Date Code
Pin Configurations
VRTT
VID0
VID1
VID2
VID3
VID4
VID5
VID6
(TOP VIEW)
32
31
30
29
28
27
26
25
NTC
1
24
BOOT
OCSET
2
23
UGATE
DPRSLPVR
3
22
VRON
PGOOD
CLKEN
VCC
4
21
PHASE
PGND
20
LGATE
19
18
PVDD
OFS
SOFT
8
17
TON
GND
5
6
7
9
10
11
12
13
14
15
16
RGND
CM
CMSET
VSEN
FB
COMP
ISEN_N
ISEN
33
WQFN-32L 5x5 / WQFN-32L 4x4
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DS8153C/D-05 April 2011
RT8153C/D
Typical Application Circuit
VIN
5V to 25V
RT8153C/D
R1
7
5V
TON
VCC
17
R2
R3
19
C2
VID0
VID1
31
PVDD
30 VID1
VID4
VID5
26
VID3
VID6
DPRSLPVR
VRON
PWRGD
6
CLKEN
32
R9
R10
PHASE 22
LGATE 20
PGND
ISEN
VID5
25 VID6
3 DPRSLPVR
4 VRON
5
VRTT
BOOT 24
UGATE 23
VID0
29 VID2
28
VID3
27 VID4
VID2
C5
C3
C1
PGOOD
R4
C4
Q1
L1
R5
R8
VOUT
Q2
R6*
21
D1*
COUT
C6*
R14
16
ISEN_N 15
CMSET
C7
R7
R20
NTC1
R13
11
VSEN 12
C9
R21
R22
FB 13
CLKEN
C12
C13
R18
R19
VRTT
R11
COMP
14
CPU VCC_SENSE
VCCP
RGND 9
3.3V
VCC
R15
NTC2
1
NTC
CM 10
R24
R23
VCC
R16
2
R17
* = Optional
SOFT 8
CPU VSS_SENSE
C10
R12
C11
CM
OFS 18
OCSET
GND
33 (Exposed Pad)
Figure 1. IMVP 6.5 CPU Core Application Circuit
DS8153C/D-05 April 2011
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3
RT8153C/D
VIN
5V to 25V
RT8153C/D
R1
7
5V
TON
VCC
17
R2
R3
19
C2
VID0
VID1
31
PVDD
30 VID1
VID4
VID5
26
VID3
VID6
DPRSLPVR
VRON
PWRGD
6
CLKEN
32
R9
R10
PHASE 22
LGATE 20
PGND
ISEN
VID5
25 VID6
3 DPRSLPVR
4 VRON
5
VRTT
BOOT 24
UGATE 23
VID0
29 VID2
28
VID3
27 VID4
VID2
C5
C3
C1
PGOOD
R4
C4
Q1
L1
R5
R8
VOUT
Q2
R6*
21
D1*
C7
R7
C6*
R14
16
ISEN_N 15
CMSET
COUT
R20
NTC1
R13
11
VSEN 12
C9
R21
R22
FB 13
CLKEN
C12
C13
R18
R19
VRTT
R11
COMP
14
CPU VCC_SENSE
VCCP
RGND 9
3.3V
VCC
R15
NTC2
1
NTC
VCC
R16
2
R17
* = Optional
CPU VSS_SENSE
C10
R12
CM 10
R24
R23
SOFT 8
OFS 18
C11
CM
1V to 1.6V
OCSET
GND
33 (Exposed Pad)
Figure 2. IMVP 6.5 CPU Core with Offset Application Circuit
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DS8153C/D-05 April 2011
RT8153C/D
VIN
5V to 25V
RT8153C/D
R1
5V
7
TON
VCC
17
R2
R3
19
C2
31
VID0
BOOT 24
UGATE 23
VID0
VID4
29 VID2
28
VID3
27 VID4
VID5
26
VID2
VID3
PHASE 22
LGATE 20
PGND
ISEN
VID5
25 VID6
3 DPRSLPVR
4 VRON
VID6
DPRSLPVR
VRON
5
PWRGD
32
VRTT
PGOOD
CMSET
3.3V
C4
Q1
L1
R5
R8
VOUT
Q2
R6*
21
D1*
NTC2
1
R14
VCC
NTC1
C9
2
R17
* = Optional
R21
R22
FB 13
14
C12
C13
R18
R19
GPU VCC_SENSE
CLKEN
SOFT 8
NTC
CM 10
R16
R20
R13
11
VRTT
R24
R23
COUT
C6*
16
RGND 9
R15
C7
R7
VSEN 12
COMP
6
R4
ISEN_N 15
R11
VCCP
VCC
PVDD
30 VID1
VID1
R9
C5
C3
C1
GPU VSS_SENSE
C10
R12
C11
CM
OFS 18
OCSET
GND
33 (Exposed Pad)
Figure 3. IMVP 6.5 Render Application Circuit
DS8153C/D-05 April 2011
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5
RT8153C/D
VIN
5V to 25V
RT8153C/D
R1
7
5V
TON
VCC
17
R2
R3
19
C2
31
VID0
BOOT 24
UGATE 23
VID0
VID4
29 VID2
28
VID3
27 VID4
VID5
26
VID2
VID3
PHASE 22
LGATE 20
PGND
ISEN
VID5
25 VID6
3 DPRSLPVR
4 VRON
VID6
DPRSLPVR
VRON
5
PWRGD
32
VRTT
PGOOD
CMSET
3.3V
C4
Q1
L1
R5
R8
VOUT
Q2
R6*
21
D1*
C7
R7
R14
NTC2
1
NTC1
C9
VCC
14
C12
C13
R18
R19
2
R17
* = Optional
R22
GPU VCC_SENSE
CLKEN
NTC
SOFT 8
GPU VSS_SENSE
C10
R12
CM 10
R16
R21
FB 13
VRTT
R24
R23
R20
R13
11
RGND 9
R15
COUT
C6*
16
VSEN 12
COMP
6
R4
ISEN_N 15
R11
VCCP
VCC
PVDD
30 VID1
VID1
R9
C5
C3
C1
OFS 18
C11
CM
1V to 1.6V
OCSET
GND
33 (Exposed Pad)
Figure 4. IMVP 6.5 Render with Offset Application Circuit
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DS8153C/D-05 April 2011
RT8153C/D
Functional Pin Description
Pin No.
Pin Name
Pin Function
Thermal Detection Input for VRTT Circuit. Connect this pin with a resistor divider
from VCC using NTC on the top to set the thermal management threshold level.
Furthermore, this pin provides load line enable/disable function.
Over Current Protection Setting. Connect a resistor voltage divider from VCC to
ground, the joint of the resistive voltage divider is connected to the OCSET pin,
with a voltage VOCSET, to set the over current threshold ILIM.
1
NTC
2
OCSET
3
DPRSLPVR
Deeper Sleep Mode Signal.
4
VRON
Voltage Regulator Enabler.
5
PGOOD
Power Good Indicator.
6
CLKEN
Inverted Clock Enable. Pull high by a resistor for CPU core application. This
open-drain pin is an output indicating the start of the PLL locking of the clock
chip. Connect to GND for Render application.
7
VCC
Chip Power.
Soft-Start. This pin provides soft-start function and slew rate controller. The
capacitance of the slew rate control capacitor is restricted to be larger than 10nF.
The feedback voltage of the converter follows the ramping voltage on the SOFT
pin during soft-start and other voltage transitions according to different mode of
operation and VID change.
Return Ground. This pin is the negative node of the differential remote voltage
sensing.
8
SOFT
9
RGND
10
CM
11
CMSET
12
VSEN
Positive Voltage Sensing Pin. This pin is the positive node of the differential
voltage sensing.
13
FB
Feedback. This is the negative input node of the error amplifier.
14
COMP
Compensation Pin. This pin is the output node of the error amplifier.
15
ISEN_N
Negative Input of the Current Sense.
16
ISEN
Positive Input of the Current Sense.
17
TON
Connect this Pin to VIN with One Resistor.
18
OFS
Output Voltage Offset Setting.
19
PVDD
Driver Power.
20
LGATE
Lower Gate Drive. This pin drives the gate of the low side MOSFETs.
21
PGND
22
PHASE
23
UGATE
24
BOOT
Driver Ground.
This pin is the return node of the high side MOSFET driver. Connect this pin to
the high side MOSFET sources together with the low side MOSFET drains and
the inductor.
Upper Gate Drive. This pin drives the gate of the high side MOSFETs.
Bootstrap Power Pin. This pin powers the high side MOSFET drivers. Connect
this pin to bootstrap capacitor.
Current Monitor Output. This pin outputs a voltage proportional to the output
current.
Current Monitor Output Gain Externally Setting. Connect this pin with one resistor
to VSEN the while CM pin is connected to ground with another resistor. In such a
way, the current monitor output gain can be set by the ratio of these two resistors.
To be continued
DS8153C/D-05 April 2011
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RT8153C/D
Pin No.
Pin Name
25 to 31
VID6 to VID0
32
VRTT
33
(Exposed Pad)
GND
Pin Function
Voltage ID. DAC voltage identification inputs for IMVP6.5.
The logic threshold is 30% of VCC as the maximum value for low state and
70% of the VCC as the minimum value for the high state.
Voltage Regulator Thermal Throttling. This open drain output pin will be
pulled low when the preset temperature level is exceeded.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
Function Block Diagram
NTC
VRTT
CLKEN
PGOOD
VRON
VCC
DPRSLPVR
OCSET
TON
SOFT
VCC
Power On Reset
&
Central Logic
+
-
Mode
Selection
OCP
Setting
Power
Saving
mode
GND
BOOT
+
2V
NVP Trip
Point
0LL
-
+
PHASE
PVDD
-
1.1V for RT8153C
1.2V for RT8153D
OTP
LGATE
PWMCP
PGND
DAC
MUX
OVP Trip
Point
UVP Trip
Point
RGND
OFS
Driver
Logic
Control
+
-
VID0
VID1
VID2
VID3
VID4
VID5
VID6
UGATE
+
Soft Start/Slew
Rate
Control/Offset
Control
DPRSLPVR
SOFT
FB
ERROR
AMP
+
-
+
+
0LL
-
10
+
ISEN_N
ISEN
Offset Cancellation
CM
CM
CMSET
COMP
VSEN
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DS8153C/D-05 April 2011
RT8153C/D
Table 1. IMVP6.5 VID Code Table
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Output
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Output
0
0
0
0
0
0
0
1.5000V
0
1
0
0
0
0
1
1.0875V
0
0
0
0
0
0
1
1.4875V
0
1
0
0
0
1
0
1.0750V
0
0
0
0
0
1
0
1.4750V
0
1
0
0
0
1
1
1.0625V
0
0
0
0
0
1
1
1.4625V
0
1
0
0
1
0
0
1.0500V
0
0
0
0
1
0
0
1.4500V
0
1
0
0
1
0
1
1.0375V
0
0
0
0
1
0
1
1.4375V
0
1
0
0
1
1
0
1.0250V
0
0
0
0
1
1
0
1.4250V
0
1
0
0
1
1
1
1.0125V
0
0
0
0
1
1
1
1.4125V
0
1
0
1
0
0
0
1.0000V
0
0
0
1
0
0
0
1.4000V
0
1
0
1
0
0
1
0.9875V
0
0
0
1
0
0
1
1.3875V
0
1
0
1
0
1
0
0.9750V
0
0
0
1
0
1
0
1.3750V
0
1
0
1
0
1
1
0.9625V
0
0
0
1
0
1
1
1.3625V
0
1
0
1
1
0
0
0.9500V
0
0
0
1
1
0
0
1.3500V
0
1
0
1
1
0
1
0.9375V
0
0
0
1
1
0
1
1.3375V
0
1
0
1
1
1
0
0.9250V
0
0
0
1
1
1
0
1.3250V
0
1
0
1
1
1
1
0.9125V
0
0
0
1
1
1
1
1.3125V
0
1
1
0
0
0
0
0.9000V
0
0
1
0
0
0
0
1.3000V
0
1
1
0
0
0
1
0.8875V
0
0
1
0
0
0
1
1.2875V
0
1
1
0
0
1
0
0.8750V
0
0
1
0
0
1
0
1.2750V
0
1
1
0
0
1
1
0.8625V
0
0
1
0
0
1
1
1.2625V
0
1
1
0
1
0
0
0.8500V
0
0
1
0
1
0
0
1.2500V
0
1
1
0
1
0
1
0.8375V
0
0
1
0
1
0
1
1.2375V
0
1
1
0
1
1
0
0.8250V
0
0
1
0
1
1
0
1.2250V
0
1
1
0
1
1
1
0.8125V
0
0
1
0
1
1
1
1.2125V
0
1
1
1
0
0
0
0.8000V
0
0
1
1
0
0
0
1.2000V
0
1
1
1
0
0
1
0.7875V
0
0
1
1
0
0
1
1.1875V
0
1
1
1
0
1
0
0.7750V
0
0
1
1
0
1
0
1.1750V
0
1
1
1
0
1
1
0.7625V
0
0
1
1
0
1
1
1.1625V
0
1
1
1
1
0
0
0.7500V
0
0
1
1
1
0
0
1.1500V
0
1
1
1
1
0
1
0.7375V
0
0
1
1
1
0
1
1.1375V
0
1
1
1
1
1
0
0.7250V
0
0
1
1
1
1
0
1.1250V
0
1
1
1
1
1
1
0.7125V
0
0
1
1
1
1
1
1.1125V
1
0
0
0
0
0
0
0.7000V
0
1
0
0
0
0
0
1.1000V
1
0
0
0
0
0
1
0.6875V
To be continued
DS8153C/D-05 April 2011
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9
RT8153C/D
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Output
VID6 VID5 VID4 VID3 VID2 VID1 VID0
Output
1
0
0
0
0
1
0
0.6750V
1
1
0
0
0
0
1
0.2875V
1
0
0
0
0
1
1
0.6625V
1
1
0
0
0
1
0
0.2750V
1
0
0
0
1
0
0
0.6500V
1
1
0
0
0
1
1
0.2625V
1
0
0
0
1
0
1
0.6375V
1
1
0
0
1
0
0
0.2500V
1
0
0
0
1
1
0
0.6250V
1
1
0
0
1
0
1
0.2375V
1
0
0
0
1
1
1
0.6125V
1
1
0
0
1
1
0
0.2250V
1
0
0
1
0
0
0
0.6000V
1
1
0
0
1
1
1
0.2125V
1
0
0
1
0
0
1
0.5875V
1
1
0
1
0
0
0
0.2000V
1
0
0
1
0
1
0
0.5750V
1
1
0
1
0
0
1
0.1875V
1
0
0
1
0
1
1
0.5625V
1
1
0
1
0
1
0
0.1750V
1
0
0
1
1
0
0
0.5500V
1
1
0
1
0
1
1
0.1625V
1
0
0
1
1
0
1
0.5375V
1
1
0
1
1
0
0
0.1500V
1
0
0
1
1
1
0
0.5250V
1
1
0
1
1
0
1
0.1375V
1
0
0
1
1
1
1
0.5125V
1
1
0
1
1
1
0
0.1250V
1
0
1
0
0
0
0
0.5000V
1
1
0
1
1
1
1
0.1125V
1
0
1
0
0
0
1
0.4875V
1
1
1
0
0
0
0
0.1000V
1
0
1
0
0
1
0
0.4750V
1
1
1
0
0
0
1
0.0875V
1
0
1
0
0
1
1
0.4625V
1
1
1
0
0
1
0
0.0750V
1
0
1
0
1
0
0
0.4500V
1
1
1
0
0
1
1
0.0625V
1
0
1
0
1
0
1
0.4375V
1
1
1
0
1
0
0
0.0500V
1
0
1
0
1
1
0
0.4250V
1
1
1
0
1
0
1
0.0375V
1
0
1
0
1
1
1
0.4125V
1
1
1
0
1
1
0
0.0250V
1
0
1
1
0
0
0
0.4000V
1
1
1
0
1
1
1
0.0125V
1
0
1
1
0
0
1
0.3875V
1
1
1
1
0
0
0
0.0000V
1
0
1
1
0
1
0
0.3750V
1
1
1
1
0
0
1
0.0000V
1
0
1
1
0
1
1
0.3625V
1
1
1
1
0
1
0
0.0000V
1
0
1
1
1
0
0
0.3500V
1
1
1
1
0
1
1
0.0000V
1
0
1
1
1
0
1
0.3375V
1
1
1
1
1
0
0
0.0000V
1
0
1
1
1
1
0
0.3250V
1
1
1
1
1
0
1
0.0000V
1
0
1
1
1
1
1
0.3125V
1
1
1
1
1
1
0
0.0000V
1
1
0
0
0
0
0
0.3000V
1
1
1
1
1
1
1
0.0000V
www.richtek.com
10
DS8153C/D-05 April 2011
RT8153C/D
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
(Note 1)
VCC to GND -------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
RGND, PGND to GND ------------------------------------------------------------------------------------------- −0.3V to 0.3V
VIDx to GND ------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
DPRSLPVR, VRON to GND ----------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
PGOOD, CLKEN, VRTT to GND ------------------------------------------------------------------------------ −0.3V to (VCC + 0.3V)
VSEN, FB, COMP, SOFT, OCSET, CM, CMSET, NTC to GND --------------------------------------- −0.3V to (VCC + 0.3V)
ISEN, ISEN_N to GND ------------------------------------------------------------------------------------------ −0.3V to (VCC + 0.3V)
PVDD to PGND --------------------------------------------------------------------------------------------------- −0.3V to 6.5V
LGATE to PGND
DC -------------------------------------------------------------------------------------------------------------------- −0.3V to (PVDD + 0.3V)
<20ns --------------------------------------------------------------------------------------------------------------- −2.5V to 7.5V
PHASE to PGND
DC -------------------------------------------------------------------------------------------------------------------- −0.3V to 30V
<20ns --------------------------------------------------------------------------------------------------------------- −8V to 38V
BOOT to PHASE ------------------------------------------------------------------------------------------------- −0.3V to 6.5V
UGATE to PHASE
DC -------------------------------------------------------------------------------------------------------------------- −0.3V to (PVDD + 0.3V)
<20ns --------------------------------------------------------------------------------------------------------------- −5V to 7.5V
TON to GND ------------------------------------------------------------------------------------------------------- −0.3V to 30V
Power Dissipation, PD @ TA = 25°C
WQFN−32L 5x5 --------------------------------------------------------------------------------------------------- 2.778W
WQFN−32L 4x4 --------------------------------------------------------------------------------------------------- 1.923W
Package Thermal Resistance (Note 2)
WQFN−32L 5x5, θJA --------------------------------------------------------------------------------------------- 36°C/W
WQFN−32L 5x5, θJC --------------------------------------------------------------------------------------------- 6°C/W
WQFN−32L 4x4, θJA --------------------------------------------------------------------------------------------- 52°C/W
WQFN−32L 4x4, θJC --------------------------------------------------------------------------------------------- 7°C/W
Junction Temperature -------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range ----------------------------------------------------------------------------------- −65°C to 150°C
Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------- 260°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
z
z
z
z
(Note 4)
Supply Voltage, VCC --------------------------------------------------------------------------------------------- 4.5V to 5.5V
Battery Voltage, VIN --------------------------------------------------------------------------------------------- 5V to 25V
Junction Temperature Range ----------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ----------------------------------------------------------------------------------- −40°C to 85°C
DS8153C/D-05 April 2011
www.richtek.com
11
RT8153C/D
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.92
1.2
--
V
----
1.2
1.6
1
----
V
1
--
--
MΩ
--
80
--
μA
2
--
--
V
4.5
5
5.5
V
--
--
10
mA
--
--
5
μA
V SOFT = 1.5V
--
20
--
μA
ISS2
V SOFT = 1.5V
40
50
60
μA
ISS3
V SOFT = 1.5V
80
100
120
μA
VFB
VVID = 0.7500 − 1.5000
(No Load, Active Mode )
VVID = 0.5000 − 0.7500
−0.5
0
0.5
%VID
−7.5
0
7.5
mV
For RT8153C VCORE
1.089
1.1
1.111
For RT8153D VCORE
1.188
1.2
1.212
−2
--
2
mV
RL = 47kΩ
70
80
--
dB
CLOAD = 5pF
--
10
--
MHz
--
5
--
V/μs
0.5
--
3.6
V
OFS Function (Only for RT8153C/D)
Enable
V OFS > 0.92V before VRON rising
OFS Threshold Offset
Voltage
Disable
V OFS connected to GND before VRON
Offset
rising
No Offset Voltage
Set OFS voltage
V OFS
Offset 400mV
Offset −200mV
Impedance
R OFS
OLL Function
I0LL
NTC
V0LL
Supply Input
Supply Voltage
Pulse sinking current source NTC
resistor at VRON rising edge.
Detect and Latch voltage at NTC pin at
VRON rising edge.
V NTC < V0LL, enable 0 Load Line
Function.
VCC
IVCC +
Supply Current
V RON = 3.3V, Not Switching
IPVCC
ICC +
V RON = 0V
Shutdown Current
IPVCC
Soft-Start/Slew Rate Control (based on 10nF CSS )
Soft-Start / Soft-Shutdown ISS1
Normal VID change slew
current
Deeper Sleep Exit/VID
Change Slew Current
(only at IMVP6.5 Render
application)
Reference and DAC
DC Accuracy
Boot Voltage
VBOOT
V
Error Amplifier
Input Offset Voltage
VOSEA
DC Gain
Gain Bandwidth Product
GBW
Slew Rate
SRCOMP
Output Voltage Range
VCOMP
CLOAD = 10pF (Gain = −4,
RF = 47kΩ, V OUT = 0.5V − 3V)
RL = 47kΩ
To be continued
www.richtek.com
12
DS8153C/D-05 April 2011
RT8153C/D
Parameter
Maximum Source
Current
Maximum Sink Current
Symbol
Min
Typ
Max
Unit
V COMP = 2V
200
250
--
μA
V COMP = 2V
20
--
--
mA
−1
--
1
mV
Impedance at Neg. Input RISEN_N
1
--
--
MΩ
Impedance at Pos Input
1
--
--
MΩ
--
10
--
V/V
1
%
IOUTEA_COMP
Test Conditions
Current Sense Amplifier
Input Offset Voltage
VOSCS
RISEN
DC Gain
1 Phase Operating
VISEN_ACC
−30mV < ISEN_IN < 50mV
−1
TON Pin Output Voltage
VTON
ITON = 80μA, VTON = VVID = 0.75
−5
0
5
%
DEM ON-Time Setting
tON
IRTON = 80μA
--
350
--
ns
RTON Current Range
IRTON
25
--
280
μA
4.1
4.3
4.5
V
--
200
--
mV
VISEN Linearity
DEM TON Setting
Protection
Under Voltage Lock out
Threshold
UVLO Hysteresis
Absolute Over Voltage
Protection Threshold
Absolute Over Voltage
Offset
Relative Over Voltage
Protection Threshold
VUVLO
VOVABS
(Respect to 1.7V, ±50mV)
1.65
1.7
1.75
V
VOVABS_OFS
(Respect to 2V, ±50mV)
1.95
2
2.05
V
VOV
(Respect to VDAC, ±50mV)
250
300
350
mV
−450
−400
−350
mV
−100
--
--
mV
45
50
55
mV
TSD
--
160
--
°C
ΔTSD
--
10
--
°C
Under Voltage Protection
VUV
Threshold
Negative Voltage
Protection Threshold
Current Limit Threshold
Voltage
Thermal Shut Down
Threshold
Thermal Shut Down
Hysteresis
Logic Inputs
VRON Threshold
Falling Edge.
VNV
VILIMIT
Measured at VSEN with respect to
Unloaded Output Voltage (UOV)
(for 0.8 < UOV < 1.5)
Measured at VSEN with Respect to
GND
V ISEN − VISEN_N = V ILIM ,
V OCSET = 2.4V, 48 x V ILIMT = VOCSET
VIH
Respect to 1.05V, 70%
0.735
--
--
VIL
Respect to 1.05V, 30%
--
--
0.315
−1
--
1
V
Leakage Current of
VRON
DAC (VID0 to VID6) and
DPRSLPVR
Leakage Current of DAC
(VID0 to VID6), PSI and
DPRSLPVR
VIH
Respect to 1.05V, 70%
0.735
--
--
VIL
Respect to 1.05V, 30%
--
--
0.315
−1
--
1
μA
V
μA
To be continued
DS8153C/D-05 April 2011
www.richtek.com
13
RT8153C/D
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Power Good
PGOOD Low Voltage
VPGOOD
IPGOOD = 4mA
--
--
0.4
V
PGOOD Delay
t PGD
CLK_EN Low to PGOOD High
3
--
20
ms
VCLKEN
ICLKEN = 4mA (only for VCORE)
--
--
0.4
V
VOT
Measure at NTC Respect to VCC
--
80
--
%VDD
VOT_HY
At VCC = 5V
--
230
--
mV
IVRTT = −40mA
--
--
0.4
V
450
480
510
mV
--
--
1.15
V
--
1
--
Ω
Clock Enable
CLKEN Low Voltage
Thermal Throttling
Thermal Throttling
Threshold
Thermal Throttling
Threshold Hysteresis
VVRTT
VRTT Output Voltage
Current Monitor
Current Monitor Output
Voltage in Operating
Range
Current Monitor Maximum
Output Voltage
Gate Driver
VISEN − VISEN_N= 20mV,
RCM = 18kΩ, RCMSET = 12kΩ
Upper Driver Source
RUGATEsr
VBOOT − VPHASE = 5V
VBOOT − VLGATE = 1V
Upper Driver Sink
RUGATEsk
VUGATE = 1V
Lower Driver Source
RLGATEsr
VPVDD = 5V, VPVDD − VLGATE = 1V
--
1
--
Ω
Lower Driver Sink
RLGATEsk
VLGATE = 1V
--
0.5
--
Ω
Upper Driver Source/Sink
IUGATE
Current
Lower Driver Source
ILGATEsr
Current
VBOOT − VPHASE = 5V
VUGATE = 2.5V
--
2
--
A
VLGATE = 2.5V
--
2
--
A
Lower Driver Sink Current ILGATEsk
Internal Boot Charging
RBOOT
Switch On Resistance
VLGATE = 2.5V
--
4
--
A
PVDD to BOOT
--
30
--
Ω
Ω
1
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layers test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
www.richtek.com
14
DS8153C/D-05 April 2011
RT8153C/D
Typical Operating Characteristics
CCM VCC_SENSE vs. Load Current
CCM Efficiency vs. Load Current
1.16
100
90
1.14
VIN = 8V
VIN = 12V
VIN = 19V
70
60
VCC_SENSE (V)
Efficiency (%)
80
50
40
30
20
1.12
1.10
VIN = 8V
VIN = 12V
VIN = 19V
1.08
1.06
10
VID = 1.15V, RTON = 120kΩ, DPRSLPVR = GND
VID = 1.15V, RTON = 120kΩ, DPRSLPVR = GND
1.04
0
0
5
10
15
20
25
0
30
5
10
15
20
25
Load Current (A)
Load Current (A)
CCM Efficiency vs. Load Current
CCM VCC_SENSE vs. Load Current
100
30
0.94
90
0.92
VIN = 8V
VIN = 12V
VIN = 19V
70
60
VCC_SENSE (V)
Efficiency (%)
80
50
40
30
20
0.90
0.88
VIN = 8V
VIN = 12V
VIN = 19V
0.86
0.84
10
VID = 0.9375V, RTON = 120kΩ, DPRSLPVR = GND
VID = 0.9375V, RTON = 120kΩ, DPRSLPVR = GND
0.82
0
0
5
10
15
20
25
0
30
5
Load Current (A)
10
15
20
25
30
Load Current (A)
VCM vs. Load Current
DEM Efficiency vs. Load Current
90
1200
85
1000
800
VIN = 8V
VIN = 12V
VIN = 19V
75
70
VCM (mV)
Efficiency (%)
80
65
600
VIN = 8V
VIN = 12V
VIN = 19V
400
60
200
55
VID = 0.85V, RTON = 120kΩ, DPRSLPVR = High
VID = 0.9375V, RTON = 120kΩ, DPRSLPVR = GND
0
50
0
0.5
1
1.5
2
Load Current (A)
DS8153C/D-05 April 2011
2.5
3
0
5
10
15
20
25
30
Load Current (A)
www.richtek.com
15
RT8153C/D
Render Mode Power On
CPU Mode Power On
V CC_SENSE
(1V/Div)
VCC_SENSE
(1V/Div)
PGOOD
(5V/Div)
PGOOD
(5V/Div)
VRON
(5V/Div)
CLKEN
(5V/Div)
VID = 0.9375V, CLKEN Pull High to 3.3V
VRON
(5V/Div)
CLKEN
(5V/Div)
VID = 0.9375V, CLKEN Pull low to GND
Time (1ms/Div)
Time (1ms/Div)
CPU Mode Power Down
CCM VID Change Down
V CC_SENSE
(100mV/Div)
VCC_SENSE
(1V/Div)
PGOOD
(5V/Div)
UGATE
(20V/Div)
VRON
(5V/Div)
LGATE
(5V/Div)
VIN = 12V, DPRSLPVR = GND, No Load
CLKEN
(5V/Div)
VID = 0.9375V, CLKEN Pull High to 3.3V
VID0
(2V/Div)
Time (100μs/Div)
Time (20μs/Div)
CCM VID Change Up
CPU-DEM VID Change Down
V CC_SENSE
(100mV/Div)
V CC_SENSE
(100mV/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
VIN = 12V, DPRSLPVR = GND, No Load
VID0
(2V/Div)
VID change from 0.85V to 0.9375V
Time (20μs/Div)
www.richtek.com
16
VID change from 0.9375V to 0.85V
VIN = 12V, DPRSLPVR = High, No Load
VID0
(2V/Div)
VID change from 0.9375V to 0.85V
Time (20μs/Div)
DS8153C/D-05 April 2011
RT8153C/D
CCM Load Transient Response
CCM Load Transient Response
VIN = 12V, VID = 0.9375V, ILOAD = 5A to 28A
DPRSLPVR = GND
VIN = 12V, VID = 0.9375V, ILOAD = 28A to 5A
DPSLPVR = High
V CC_SENSE
(100mV/Div)
V CC_SENSE
(100mV/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
Time (10μs/Div)
Time (10μs/Div)
Over Current Protection
Over Voltage Protection
VIN = 12V, VID = 0.9375V, DPRSLPVR = GND
V CC_SENSE
(1V/Div)
VCC_SENSE
(1V/Div)
I LOAD
(20A/Div)
PHASE
(10V/Div)
UGATE
(20V/Div)
PGOOD
(2V/Div)
PGOOD
(2V/Div)
LGATE
(10V/Div)
Time (10μs/Div)
VIN = 12V, VID = 0.9375V, DPRSLPVR = GND
Time (10μs/Div)
Under Voltage Protection
V CC_SENSE
(1V/Div)
UGATE
(20V/Div)
LGATE
(5V/Div)
PGOOD
(2V/Div)
VIN = 12V, VID = 0.9375, VDPRSLPVR = GND
Time (10μs/Div)
DS8153C/D-05 April 2011
www.richtek.com
17
RT8153C/D
Application Information
The RT8153C/D is a single-phase PWM controller with
embedded gate driver. It is compliant with Intel IMVP6.5
Voltage Regulator Specification to fulfill its mobile CPU
and Render voltage regulator power supply requirement.
Inductor current are continuously sensed for loop control,
droop tuning, and over current protection. The 7-bit VID
DAC and low offset differential amplifier allow the controller
to maintain high regulating accuracy to meet Intel’s
IMVP6.5 specification.
Design Tool
To help users to reduce the efforts and errors caused by
manual calculations using the design concept below, a
user-friendly design tool is now available on request.
This design tool calculates all necessary design
parameters by entering user's requirements. Please
contact Richtek's representatives for details.
Operation Modes
Table 2 shows the RT8153C/D operation modes. When
VRON is enabled (=1), the RT8153C/D will detect CLKEN
within 10μs to determine which operation mode is applied.
If CLKEN is low, the RT8153C/D will operate in Render
core voltage regulator mode. If CLKEN is high, the IC will
operate in CPU core voltage regulator mode.
DPRSLPVR determines whether the operation mode of
the controller operation is in CCM or DEM. The controller
enters DEM (Diode Emulation Mode) when DPRSLPVR
= 1 and enters CCM when DPRSLPVR = 0.
Differential Remote Sense Connection
The RT8153C/D includes differential, remote-sense inputs
to eliminate the effects of voltage drops along the PC
board traces, CPU internal power routes, and socket
contacts. CPU contains on-die sense pins VCC_SENSE and
VSS_SENSE. Connect RGND to VSS_SENSE. Connect FB to
VCC_SENSE with a resistor to build the negative input path
of the error amplifier. Connect VSEN to VCC_SENSE for
CLKEN, PGOOD, OVP, and UVP detection. The 7 bit VID
DAC and the precision voltage reference are referred to
RGND for accurate remote sensing.
Current Sense Setting
The RT8153C/D is continuously sensing the inductor
current. Therefore, the controller can be less noise
sensitive. Low offset amplifiers are used for loop control
and over current detection. The internal current sense
amplifier gain (AI) is fixed to be 10. ISEN and ISEN_N
denote the positive and negative inputs of the current sense
amplifier.
Users can either use a current-sense resistor or the
inductor's DCR for current sensing. Using inductor's DCR
allows higher efficiency as shown in Figure 5. If
L = R ×C
(1)
X
X
DCR
then the transient performance will be optimum. For
example, choose L = 0.36μH with 1mΩ DCR and
CX = 100nF, to yield for RX :
RX =
0.36μH
= 3.6k Ω
1m Ω × 100nF
(2)
Table 2. Control Signal Truth Table for Operation
Modes of the RT8153C/D
CLKEN
DPRSLPVR
0
0
Render CCM
(GND)
1
Render DEM
1
0
CPU CCM
(Pull High)
1
CPU DEM
www.richtek.com
18
Operation Mode
V OUT
L
DCR
PHASE
RX
ISEN
CX
+ VX -
ISEN_N
Figure 5. Lossless Inductor Current Sensing
DS8153C/D-05 April 2011
RT8153C/D
Considering the inductance tolerance, the resistor, RX, has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice-versa, with a resistance too
large, the output voltage transient has only a small initial
dip and the recovery become too fast, causing a ring-back.
Since the DCR of inductor is highly temperature dependent,
it affects the output accuracy, current monitor and over
current protection accuracy at hot conditions. Temperature
compensation is recommended for the lossless inductor
DCR current sense method. Figure 6 shows a simple but
effective way of compensating the temperature variations
of the sense resistor using an NTC thermistor at DCR
sensing network.
VOUT
L
R
R R − (mRNTC + mRP )R X − mRNTCRP
RS = NTC P X
(7)
( −RNTC − RP )R X + m(RNTC + RP )
RX can be expressed by :
2
R X = −b ± b − 4ac
2a
a = ATHCTL − ATLCTH
b = ATHDTL − BTLCTH − ATLDTH
c = BTLDTH − BTHDTL
where
ATH = RNTC_THRP − mTHRNTC_TH − mTHRP
ATL = RNTC_TLRP − mTLRNTC_TL − mTLRP
BTH = RNTC_THRP
CX
BTL = RNTC_TLRP
RX
RS
(8)
where
DCR
PHASE
ISEN
so
CTH = − RNTC_TH − RP
RP
CTL = − RNTC_TL − RP
RNTC
DTH = mTH (RNTC_TH + RP)
ISEN_N
Figure 6. Lossless Inductor Current Sensing with NTC
Compensation
Usually, RP is set to equal RNTC(25°C). RS is selected to
linearize the NTC's temperature characteristic. For a given
NTC, design is to get RS and RX to compensate the
temperature variations of the sense resistor.
Let
R equ = RS + (RP / /RNTC )
(3)
DTL = mTL (RNTC_TL + RP)
where XTH denotes the value of this variable at high
temperature, and XTL denotes the value of this variable at
low temperature.
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, a RC filter is recommended. The RC filter
calculation method is similar to the above-mentioned
inductor DCR sensing method.
Then, according to above circuit,
Re qu
L =C x
X
DCR
R X + Re qu
Loop Control
(4)
Next, let
m=
L
DCR x C X
(5)
Then
R
× RP
⎛
m × ⎜ R X + RS + NTC
RNTC + RP
⎝
RNTC + RP ⎞
⎞
⎛
⎟ = R X × ⎜ RS + R
⎟
NTC + RP ⎠
⎠
⎝
The RT8153C/D adopts Richtek's proprietary G-NAVPTM
topology. G-NAVPTM is based on the finite-gain current
mode with CCRCOT (Constant Current Ripple Constant
On Time) topology. The output voltage, VOUT, will decrease
with increasing output load current. The control loop
consists of PWM modulator with power stage, current
sense amplifier and error amplifier as shown in Figure 7.
(6)
DS8153C/D-05 April 2011
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19
RT8153C/D
VIN
where AI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the DCR of the inductor. RDROOP is the
resistive slope value of the converter output and is the
desired static output impedance.
RT8153C/D
UGATE
CCRCOT
PWM
Logic
RX
LGATE
VOUT
L
CX
C
LS_FET
-
CMP
+
COMP2
HS_FET
VCS
AI
+
-
ISEN
ISEN_N
COMP
EA
+
R2
C1
R1
AV2 > AV1
VCC_SENSE
FB
+
-
Offset
Cancellation
VOUT
C2
VDAC
SOFT
RGND
CSOFT
10nF
AV2
VSS_SENSE
AV1
Figure 7. Simplified Schematic for Droop and Remote
Sense in CCM
0
Load Current
Figure 8. Error Amplifier Gain (AV) Influence on VOUT
The HS_FET on-time is determined by CCRCOT On-Time
generator. When load current increases, VCS increases,
the steady-state COMP voltage also increases and makes
V OUT decrease, achieving AVP. A near-DC offset
cancellation is added to the output of EA to cancel the
inherent output offset of finite-gain current mode controller.
In RFM, HS_FET is turned on with constant tON when VCS
is lower than VCOMP2. Once HS_FET is turned off, LS_FET
is turned on automatically. With Ringing-Free Technique,
LS_FET allows only partial negative current when the
inductor free-wheeling current reaches negative. The
switching frequency will be proportionately reduced, thus
the conduction and switching losses will be greatly
reduced.
Output Voltage Droop Setting (with Temperature
As shown in Figure 9, when DCR sensing network is used
for NTC thermistor temperature compensation, the error
amplifier gain can be calculated as :
A × RSENSE
A V = Z2 = I
×K
Z1
RDROOP
(11)
where K is the dividing ratio of DCR sensing as shown
below :
K=
Z2
Z1 + Z2
(12)
VOUT
L
DCR
PHASE
CX
Z1
ISEN
Z2
Compensation)
It's very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
VOUT = VDAC − ILOAD x RDROOP
(9)
, then solving the switching condition VCOMP = VCS in Figure
7 yields the desired error amplifier gain as
A × RSENSE
A V = R2 = I
R1
RDROOP
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20
(10)
ISEN_N
Figure 9. Using an NTC Thermistor at DCR Sensing
Network
Loop Compensation
Optimized compensation of the RT8153C/D allows for best
possible load step response of the regulator's output. A
compensator with one pole and one zero is adequate for
a proper compensation. Figure 7 shows the compensation
circuit. Prior design procedure shows how to determine
DS8153C/D-05 April 2011
RT8153C/D
the resistive feedback components of error amplifier gain.
The C1 and C2 must be calculated for the compensation.
The target is to achieve constant resistive output impedance
over the widest possible frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
fP =
1
2 × π × C × RC
C × RC
R2
VDAC(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS-FET + DCRL − RDROOP ⎤⎦
VIN(MAX) + ILOAD(MAX) × ⎡⎣RON _ LS-FET − RON _ HS-FET ⎤⎦
where
`
fsMAX is the maximum switching frequency
`
tHS- Delay is the turn on delay of HS-FET
`
VDAC(MAX) is the maximum VDAC of application
`
VINMAX is the maximum application Input voltage
`
ILOAD(MAX) is the maximum load of application
`
RON_LS-FET is the Low side FET RDS(ON)
`
RON_HS-FET is the High side FET RDS(ON)
`
DCRL is the inductor DCR
`
RDROOP is the load line setting
(14)
The zero of compensator has to be placed at half of the
switching frequency to filter the switching-related noise,
such that,
1
C1 =
(15)
R1b
+
R1a
//
R
(
NTC, 25 ) × π × fSW
TON Setting
High frequency operation optimizes the application for the
smaller component size, trading off efficiency due to higher
switching losses. This may be acceptable in ultra-portable
devices where the load currents are lower and the
controller is powered from a lower voltage supply. Low
frequency operation offers the best overall efficiency at
the expense of component size and board space. Figure
10 shows the On-Time setting circuit. Connect a resistor
(RTON) between VIN and TON to set the on-time of UGATE:
−12
tON =
For better efficiency of the given load range, the maximum
switching frequency is suggested to be :
1
fS(MAX) =
×
(17)
tON − tHS-Delay
(13)
where C is the capacitance of output capacitor and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C2 =
time by a period equal to the HS-FET rising dead time.
14.5 × 10 × RTON × 2
(VIN − VDAC )
(16)
where tON is UGATE turn on period, VIN is input voltage of
converter, VDAC is DAC voltage.
On-time translates only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in external HS-FET.
Also, the dead-time effect increases the effective on-time,
reducing the switching frequency. It occurs only in CCM
(DPRSLPVR = 0) and during dynamic output voltage
transitions when the inductor current reverses at light or
negative load currents. With reversed inductor current,
PHASE goes high earlier than normal, extending the onDS8153C/D-05 April 2011
CCRCOT
On-Time
Generator
TON
VDAC
RTON
R1
VIN
C1
On-Time
Figure 10. On-Time setting with RC Filter
Soft-Start and Mode Transition Slew Rates
The RT8153C/D uses 3 slew rates for various modes of
operation. The three slew rates are internally determined
by commanding one of three bi-directional current sources
(ISS) into the SOFT pin. The 7 bit VID DAC and the precision
voltage reference are referred to RGND for accurate remote
sensing. Hence, connect a capacitor (CSOFT) from SOFT
pin to RGND for controlling the slew rate as shown in
Figure 7. The capacitance of capacitor is restricted to be
larger than 10nF. The voltage (VSOFT) on the SOFT pin is
the reference voltage of the error amplifier and is, therefore,
the commanded system voltage.
The first current is typically 20μA used to charge or
discharge the CSOFT during soft-start, and soft-shutdown.
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21
RT8153C/D
The second current is typically 50μA used during other
voltage transitions, including VID change and transitions
between operation modes. The third current is typically
100μA used during Render DEM with VID change up
transitions.
The IMVP−6.5 specification specifies the critical timing
associated with regulating the output voltage. The symbol,
SLEWRATE, as given in the IMVP−6.5 specification will
determine the choice of the SOFT capacitor, CSOFT, by the
following equation :
CSOFT =
ISS
SLEWRATE
(18)
Power Up Sequence
When the controller's VCC voltage rises above the UVLO
threshold (typ. 4.3V), the power up sequence begins when
VRON goes high. If CLKEN = 1 (Pull High), the
RT8153C/D will enter CPU mode power-up sequence. If
CLKEN = 0 (Connect to GND), the controller will enter
Render mode power up sequence.
After the RT8153C/D enters CPU mode, VSEN starts
ramping up to VBOOT within 1ms. The slew rate during
power-up is 20μA/CSOFT. The RT8153C/D pulls CLKEN low
after VSEN gets across VBOOT − 0.1V for 73μs. Right after
CLKEN goes low, VSEN starts ramping to first VDAC value.
After CLKEN goes low for approximately 4.7ms, PGOOD
is asserted HIGH. DPRSLPVR is valid right after PGOOD
is asserted. UVP is masked as long as VSEN is less than
VBOOT − 0.1V.
VCC 4.3V
4.1V
UVLO
VRON
VID
XX
Valid
VBOOT - 0.1V
xx
VBOOT
VSEN
PWM
DPRSLPVR
0.2V
Hi-Z
CCM
DPRSLPVR Defined
CCM
Pull Down
Valid
XX
XX
CLKEN
PGOOD
73µs typ.
4.7ms typ.
Figure 11. CPU Mode Timing Diagram for Power Up and Power Down
After the RT8153C/D enters Render mode, VSEN starts ramping up to VDAC within 1ms. The slew rate during power-up
is 20μA/CSOFT. PGOOD is asserted HIGH after VSEN exceeds VDAC − 100mV for 4.77ms (typ.). DPRSLPVR is valid
right after PGOOD is asserted. UVP is masked as long as VSEN is less than VDAC − 100mV.
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22
DS8153C/D-05 April 2011
RT8153C/D
VCC
4.3V
4.1V
POR
VRON
VID
XX
xx
Valid
VDAC-100mV
VDAC
VSEN
PWM
0.2V
Hi-Z
DPRSLPVR
DPRSLPVR Defined
CCM
XX
CCM
Pull Down
Valid
XX
PGOOD
4.77ms typ.
Figure 12. Render Mode Timing Diagram for Power Up and Power Down
Power Down
When VRON goes low, the RT8153C/D enters low power
shutdown mode. PGOOD is pulled low immediately and
the VSOFT ramps down with slew rate of 20μA/CSOFT. VSEN
also ramps down following VSOFT. After VVSEN is lower than
200mV, the RT8153C/D turns off high side FETs and low
side FETs. An internal discharge resistor at VSEN will be
enabled and the analog part will be turned off.
After DPRSLPVR goes high, the RT8153C/D enters deeper
sleep mode operation. If the VIDs are set to a lower voltage
setting, the output drops at a rate determined by the load
and the output capacitance. The internal target VSOFT still
ramps as before, and UVP, OCP and OVP are masked for
73μs.
Over Current Protection Setting
The RT8153C/D compares a programmable current limit
set point to the voltage from the current sense amplifier
output for over current protection (OCP). The voltage applied
to OCSET pin defines the desired current limit threshold
ILIM :
(19)
Connect a resistive voltage divider from VCC to GND, with
DS8153C/D-05 April 2011
⎛ VCC
⎞
ROC1 = ROC2 × ⎜
− 1⎟
V
⎝ OCSET
⎠
(20)
VCC
ROC1
OCSET
ROC2
Deeper Sleep Mode Transitions
VOCSET = 48 x ILIM x RSENSE
the joint of the voltage divider connected to OCSET pin as
shown in Figure 13. For a given ROC2, then
Figure 13. OCP Setting Without Temperature
Compensation
The RT8153C/D provides current limit function and over
current protection. The current limit function is triggered
when inductor current exceeds the current limit threshold,
ILIM, defined by VOCSET. When current limit function is
tripped, high side MOSFET will be forced off until the over
current condition is cleared.
If the current limit function is triggered for 15 switching
cycles, OCP will be tripped. Once OCP is tripped, both
high side and low side MOSFET will be turned off, and the
internal discharge resistor at the VSEN pin will be enabled
to discharge output capacitors. OCP is a latched
protection, it can only be reset by cycling VRON or VCC.
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23
RT8153C/D
Over Voltage Protection (OVP)
The OVP circuit is triggered under two conditions (without
offset mode):
state and the discharging resistor at VSEN pin will be
enabled. A reset can be executed by cycling VCC or
VRON.
`
Condition 1 : When VVSEN exceeds 1.7V.
Thermal Throttling Control
`
Condition 2 : When VVSEN exceeds VDAC by 300mV
(typ.).
Intel IMVP-6.5 technology supports thermal throttling of
the processor to prevent catastrophic thermal damage.
The RT8153C/D includes a thermal monitoring circuit to
detect an exceeded user-defined temperature on a VR
point. The thermal monitoring circuit senses the voltage
change across NTC pin. Figure 14 shows the principle of
setting the temperature threshold. Connect an external
resistive voltage divider between Vcc and GND. This divider
uses a Negative Temperature Coefficient (NTC) thermistor
and a resistor. The joint of the voltage divider is connected
to the NTC pin in order to generate a voltage that is
When offset mode, the relative over voltage protection is
disable and the over circuit is triggered until VVSEN exceeds
2V.
If either condition is valid, the RT8153C/D latches the
LGATE = 1 and UGATE = 0 as crowbar to the output
voltage of VR. Turning on all LS_FETs can lead to very
large reverse inductor current and potentially result in
negative output voltage of VR. To prevent the CPU from
damage by negative voltage. The RT8153C/D turns off all
LS_FETs when VVSEN falls below −100mV.
Under Voltage Protection (UVP)
If VVSEN is lower than VDAC by 400mV (typ.) a UVP fault
will be tripped. Once UVP is tripped, both high side and
low side MOSFET will be turned off and the internal
discharge resistor at VSEN pin will be enabled. UVP is a
latched protection; it can only be reset by cycling VRON
or VCC.
Negative Voltage Protection (NVP)
During the state when VVSEN is lower than −100mV, the
controller will force LGATE = 0 and UGATE = 0 to prevent
negative voltage. Once VVSEN recovers to be higher than
0V, NVP will be suspended and LGATE = 1 will be enabled
again.
Over Temperature Protection (OTP)
Over Temperature Protection prevents the VR from
damage. OTP is considered to be the final protection stage
against overheating of the VR. The thermal throttling VRTT
is set to be asserted prior to OTP to manage the VR power.
When this measure becomes insufficient to keep the die
temperature of the controller below the OTP threshold,
OTP will be asserted and latched. The die temperature of
the controller is monitored internally by a temperature
sensor. As a result of OTP triggering, a soft shutdown will
be launched and VVSEN will be monitored. When VVSEN is
less than 200mV, the driver remains in high impedance
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24
inversely proportional to temperature. The RT8153C/D
pulls VRTT low if the voltage on the NTC pin is greater
than 0.8 x VCC. The internal VRTT comparator has a
hysteresis of 200mV (typ.) to prevent high frequency VRTT
oscillation when the temperature is near the setting point.
The minimum assertion/de-assertion time for VRTT toggling
is 1.6ms (typ.).
VCC
VRTT
CMP
NTC
NTC
+
-
RTT
+
0.8 x VCC
Figure 14. Thermal Throttling Setting Principle
Furthermore, this pin also provides load line enable/disable
function in which the zero load line regulation can be
implemented through NTC pin. The NTC pin will sink a
80μA current pulse inward the IC at VRON rising edge
and the IC will detect the voltage of NTC pin at the same
time to determine whether the zero load line function is
enabled or not. Figure 15 is the recommended setting
network of zero load line. The 100kΩ NTC resistor is
recommended in this setting network for zero load line
application and the resistance of R1 is set to be the same
value as the resistor at 25°C. In addition, the resistance
of both R2 and R3 can be obtained by solving the equations
21 and 22.
DS8153C/D-05 April 2011
RT8153C/D
for 120°C
VNTC =
I(MAX) = 30A, DCR = 1mΩ,
R3
x VCC = 4V
(R1/ /RNTCHT ) + R2 + R3
VCM = 1V, RCMSET = 10kΩ
(21)
⇒ RCM = 20.8kΩ
for − 20°C
VNTC =
R3
x VCC = 1.5V
(R1/ /RNTCLT ) + R2 + R3
(22)
VRTT
Current
Monitor
Generator
VSEN
VCC_SENSE
RCMSET
CMSET
CM
VCC
VCM
RCM
R1
NTC
Figure 16. Current Monitor Setting Principle
R2
CMP +
C1
RGND
NTC
-
When DCR sensing network is used for NTC thermistor
temperature compensation, the current monitor indication
voltage, VCM, can be calculated as below :
R3
0.8 x VCC
Figure15. For Zero Load Line Network
VCM =
16 × ILOAD × DCR × RCM × K
RCMSET
(25)
Current Monitor
Figure 16 shows the current monitor setting principle.
Current monitor needs to meet IMVP6.5 specification. The
RT8153C/D is based on the relation between RDROOP and
load current to provide an easy setting and high accuracy
current monitor indicator.
The current monitor indication voltage, VCM, is calculated
as :
16 × ILOAD × DCR × RCM
VCM =
RCMSET
(23)
where ILOAD is the output load current, DCR is the load
line setting of applications, and RCM and RCMSET are the
current monitor current setting resistors.
To find RCM and RCMSET, follow below equation :
RCM
RCMSET
=
VCM
16 × I(MAX) × DCR
(24)
VCM must be kept equal to 1V and I(MAX) needs to follow
the setting current of the IMVP6.5 definition with various
CPU. VCM is clamped not higher than 1.15V.
For an example of current monitor setting, the following
design parameters are given :
DS8153C/D-05 April 2011
To find RCM and RCMSET follow below equation :
VCM
RCMSET
=
VCM(MAX)
16 × I(MAX) × DCR × RCM × K
(26)
where, K is dividing ration of DCR sensing.
No Load Offset
The RT8153C/D feature no-load offset function which
provides the possibility of wide range positive/negative
offset. The no-load offset function can be implemented
through OFS pin. To enable no-load offset function, the
voltage of the OFS pin should be higher than 0.9V at the
VRON raising edge. It is recommended to set the OFS
pin at 1.2V before VRON rising edge. The no-load offset
range can be from 400mV to −200mV while OFS pin
voltage varying from 1.6V to 1V. The output offset voltage
magnitude is equaled to the voltage difference between
OFS pin and the 1.2V. For example, the OFS pin should
be set to 1.4V if the target offset voltage is 200mV and
OFS pin should be set to 1.1V to have −100mV output
offset voltage. The accuracy of this offset voltage is ±10mV
at no-offset point which OFS pin is 12V and the linearity
of no-load offset function is higher than 95% in the 400mV
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25
RT8153C/D
Inductor Selection
The switching frequency and ripple current determine the
inductor value as follows :
L(MIN) =
VIN − VOUT
×t
IRipple −MAX ON
(27)
where tON is the UGATE turn on period.
Higher inductance yields in less ripple current and hence
in higher efficiency. The flaw is the slower transient
response of the power stage to load transients. This might
increase the need for more output capacitors driving the
cost up. Find a low-loss inductor having the lowest possible
DC resistance that fits in the allotted dimensions. The
core must be large enough not to be saturated at the
peak inductor current.
Output Capacitor Selection
Output capacitors are used to obtain high bandwidth for
the output voltage beyond the bandwidth of the converter
itself. Usually, the CPU manufacturer recommends a
capacitor configuration. Two different kinds of output
capacitors can be found including, bulk capacitors closely
located to the inductors and ceramic output capacitors in
close proximity to the load. Latter ones are for midfrequency decoupling with especially small ESR and ESL
values while the bulk capacitors have to provide enough
stored energy to overcome the low frequency bandwidth
gap between the regulator and the CPU.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
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26
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8153C/D, the maximum junction temperature is
125°C and TA is the ambient temperature. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-32L 4x4 packages, the thermal resistance, θJA, is
52°C/W on a standard JEDEC 51-7 four-layer thermal test
board. For WQFN-32L 5x5 packages, the thermal
resistance, θJA, is 36°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formulas :
PD(MAX) = (125°C − 25°C) / (36°C/W) = 2.778W for
WQFN-32L 5x5 package
PD(MAX) = (125°C − 25°C) / (52°C/W) = 1.923W for
WQFN-32L 4x4 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. For the RT8153C/D packages, the derating
curves in Figure 17 allow the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Maximum Power Dissipation (W)1
to −200mV range. Furthermore, the offset function has
clamp mechanism to prevent the output voltage run-away.
The lower limit of the offset function is −300mV which
means the output offset voltage magnitude will keep exactly
−300mV even if the OFS pin voltage is lower than 0.9V. In
another hand, the upper limit of the offset function is about
600mV which means the output offset voltage magnitude
will keep about 600mV even if the OFS pin voltage is
higher than 1.8V.
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
Four Layers PCB
WQFN-32L 5x5
WQFN-32L 4x4
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 17. Derating Curve for RT8153C/D Package
DS8153C/D-05 April 2011
RT8153C/D
Layout Considerations
Careful PC board layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount all
of the power components on the top side of the board
with their ground terminals flush against one another.
Follow these guidelines for optimum PC board layout :
`
Keep the high current paths short, especially at the
ground terminals.
`
Keep the power traces and load connections short. This
is essential for high efficiency.
`
The slew rate control capacitor should be connected
from SOFT to RGND.
`
When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be made
longer than the discharging path.
`
Place the current sense component close to the
controller. ISEN and ISEN_N connections for current limit
and voltage positioning must be made using Kelvin sense
connections to guarantee the current sense accuracy.
The PCB trace from the sense nodes to controller should
be parallel to each other.
`
Route high-speed switching nodes away from sensitive
analog areas (SOFT, COMP, FB, VSEN, ISEN, ISEN_N,
CM, etc...)
DS8153C/D-05 April 2011
www.richtek.com
27
RT8153C/D
Outline Dimension
D2
D
SEE DETAIL A
L
1
E
E2
e
b
1
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A1
1
2
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
4.950
5.050
0.195
0.199
D2
3.400
3.750
0.134
0.148
E
4.950
5.050
0.195
0.199
E2
3.400
3.750
0.134
0.148
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 32L QFN 5x5 Package
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28
DS8153C/D-05 April 2011
RT8153C/D
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
3.900
4.100
0.154
0.161
D2
2.650
2.750
0.104
0.108
E
3.900
4.100
0.154
0.161
E2
2.650
2.750
0.104
0.108
e
L
0.400
0.300
0.016
0.400
0.012
0.016
W-Type 32L QFN 4x4 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8153C/D-05 April 2011
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29