RT8800A General Purpose 3-Phase PWM Controller for High-Density Power Supply General Description Features The RT8800A is a general-purposed multi-phase synchronous buck controller dedicating for high power density applications. The RT8800A operates with 2 or 3 synchronous buck switching stages in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. z The output voltage is precisely regulated to the external reference voltage at PI pin. The RT8800A can provide Intel® VRD10.x or AMD® K8 compliant output voltage when companioned with DAC generator RT9401A/B. The RT8800A adopts innovative time-sharing DCR current sensing technique for channel current balance, droop tuning, and over current protection. Using one common GM amplifier for current sensing eliminates offset errors and linearity variation between GMs. As sub-milli-ohmgrade inductors are widely used in modern mother boards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The timesharing DCR current sensing technique is extremely important to guarantee phase current balance at mass production. Other features include overvoltage protection, undervoltage protection and internal softstart. The RT8800A comes to a VQFN-16L 3x3 package. z z z z z z z z z z z z 5V Power Supply Voltage 2/3-Phase Power Conversion with Automatic Phase Selection Output Voltage Controlled by External Reference Voltage Precise Core Voltage Regulation Power Stage Thermal Balance by DCR Current Sensing Extreme Low-Cost, Lossless Time Sharing Current Sensing Internal Soft-Start Hiccup Mode Over-Current Protection Over Voltage Protection Adjustable Operating Frequency and Typical at 300kHz Per Phase Power Good Indication Small 16-Lead VQFN Package RoHS Compliant and 100% Lead (Pb)-Free Applications z z z Desktop CPU Core Power Low Output Voltage, High Power Density DC/DC Converters Voltage Regulator Modules Marking Information Ordering Information RT8800A Package Type QV : VQFN-16L 3x3 (V-Type) Note : For marking information, contact our sales representative directly or through a Richtek distributor located in your area. Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. DS8800A-06 April 2011 www.richtek.com 1 RT8800A Pin Configurations PWM1 PWM2 PWM3 VDD (TOP VIEW) 16 15 14 13 FB 3 DVD 4 12 ISP1 11 ISP2 GND 10 ISP3 17 9 5 6 7 8 ICOMMON 2 RT VID125 PI 1 COMP IMAX PGOOD VQFN-16L 3x3 Functional Pin Description IMAX (Pin 1) ICOMMON (Pin 8) Over current protection setting. Common negative input of current sense amplifiers for all three channels. VID125 (Pin 2) Connect a resistor from this pin to GND can raise VOUT. PGOOD (Pin 9) FB (Pin 3) Output power-good indication. The signal is implemented as an output signal with open-drain type. The pin is defined as the inverting input of internal error amplifier. ISP1 , ISP2 , ISP3 (Pin 12, Pin 11, Pin 10) DVD (Pin 4) Current sense positive inputs for individual converter channel current sense. The pin is defined as a programmable power UVLO detection input. Trip threshold = 0.8V at VDVD rising. PWM1 , PWM2 , PWM3 (Pin 13, Pin 14, Pin 15) PWM outputs for each phase switching drive. COMP (Pin 5) The pin is defined as the output of the error amplifier and the input of all PWM comparators. VDD (Pin 16) PI (Pin 6) GND [Exposed Pad (17)] The pin is defined as the positive input of the error amplifier. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Chip power supply. Connect this pin to a 5V supply. RT (Pin 7) Switching frequency setting. Connect this pin to GND with a resistor to set the frequency. www.richtek.com 2 DS8800A-06 April 2011 5V 4 3 VDD VDA VID1 VID0 GND VID4 5 6 7 8 DVD 4 R9 16k Optional RCSN R8 3k RT 7 VID3 R7 27k GND RT8800A C5 4.7uF RCS 11 10 14 15 DSKY C8 1uF R12 R11 R R R PHASE1 PHASE2 PHASE3 C11 to C14 1500uF x 4 C6 1uF R10 Optional C10 1uF VCORE Optional 430 C7 1uF Optional ISP2 ISP3 PWM2 PWM3 RCOMM 8 VID2 12V 5V ICOMMON 12 2 1 3.3V PGOOD COMP R6 10k 9 VID125 2 R5 16k PI 1 IMAX 6 FB R4 10k R3 3k 5 ISP1 RT9401A/B C4 10nF C2 10nF RADJ R1 15k Optional C3 R2 1uH 17 BOOT2 C18 1uF 12V VIN Q4 1 24 R16 0 BOOT1 PWM1 PWM2 19 R13 0 PWM3 D2 2 4 5 7 16 C15 1uF D1 Q1 UGATE2 VIN 21 12V GND 1uF C19 R17 2.2 12V 22 Q3 BOOT3 C21 3.3nF 9 Q6 C20 1uF 8 R19 10 R20 0 5VSB C23 1uF 11 12V 15 14 UGATE3 10 PHASE3 PVCC3 LGATE3 R18 0 Q5 23 RT9605 3 R15 0 C16 3.3uF Q2 20 1uF C17 R14 2.2 PVCC2 C9 1000uF 12V LGATE2 C1 33pF VDD UGATE1 PHASE2 PHASE1 3 PVCC1 16 LGATE1 TS DS8800A-06 April 2011 13 PWM1 VDD Q9 Q8 L3 0.5uH R22 2.2 L2 0.5uH Q7 PHASE3 C24 3.3nF L1 0.5uH VIN PHASE1 12V R21 0 C22 1uF PHASE2 VCORE C37 to C40 10uF x 4 C25 to C36 1000uF x 12 RT8800A Typical Application Circuit 3-phase with RT9401A/B DAC generator www.richtek.com 3 VID125 FB PI COMP 500mV - + 0.8V VREF OVP IMAX SUM/N & OCP Detection OCP Oscillator & Ramp Generator EA MAJ Soft Start + - Power On Reset GND + + + + + + PWMCP PWMCP Sample & Hold Sample & Hold Sample & Hold PWMCP + + RT Mux INH INH INH PWM Logic & Driver PWM Logic & Driver PWM Logic & Driver GM ISP2 ISP3 ISP1 PWM3 PWM2 PWM1 ICOMMON Mux + + + www.richtek.com 4 - + + PGOOD VDD DVD RT8800A Function Block Diagram DS8800A-06 April 2011 RT8800A Absolute Maximum Ratings z z z z z z z z (Note 1) Supply Voltage, VDD ------------------------------------------------------------------------------------------- 7V Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to VDD + 0.3V Power Dissipation, PD @ TA = 25°C VQFN-16L 3x3 -------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) VQFN-16L 3x3, θJA --------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z 1.47W 68°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage, VDD ------------------------------------------------------------------------------------------- 5V ± 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range --------------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VDD = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit -- 5 -- mA Rising 4.0 4.2 4.5 Hysteresis 0.2 0.5 -- 0.75 0.8 0.85 V -- 65 -- mV 170 200 230 kHz 50 -- 400 kHz -- 1.7 -- V -- 1.0 -- V 62 66 75 % VDD Supply Current Nominal Supply Current IDD PWM 1,2,3 Open Power-On Reset V DD Threshold DVD Rising Threshold DVD Hysteresis V Oscillator Free Running Frequency fOSC Frequency Adjustable Range fOSC_ADJ Ramp Amplitude ΔVOSC Ramp Valley VRV RRT = 16kΩ RRT = 16kΩ Maximum On-Time of Each Channel RT Pin Voltage VRT RRT = 16kΩ 0.77 0.82 0.87 V IMAX Reference Voltage VIMAX RIMAX = 16kΩ 0.75 0.8 0.85 V VID125 Reference Voltage VVID125 RVID125 = 16kΩ 0.75 0.8 0.85 V Reference Voltage To be continued DS8800A-06 April 2011 www.richtek.com 5 RT8800A Parameter Symbol Test Conditions Min Typ Max Unit -- 65 -- dB Error Amplifier DC Gain Gain-Bandwidth Product GBW CL = 10pF -- 10 -- MHz Slew Rate SR CL = 10pF -- 8 -- V/μs 100 -- -- μA 360 460 560 mV -- -- 0.2 V 4 -- 8 ms Current Sense GM Amplifier Recommended Full Scale Source Current Protection Over-Voltage Trip (V FB – VPI) Power Good PGOOD Output Low Voltage VPGOOD IPGOOD = 4mA PGOOD Delay T PGOOD_Delay 90% * V OUT to PGOOD_H Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 6 DS8800A-06 April 2011 RT8800A Typical Operating Characteristics Efficiency vs. Output Current Load Line 1.4 RLL = 1.5mΩ, RCSN = 10kΩ, RADJ = 100Ω VIN = 12V 1.38 VIN = 12V, VOUT = 1.4V 90 80 1.36 70 Efficiency (%) Output Voltage (V) 100 1.34 1.32 1.3 60 50 40 30 1.28 20 1.26 10 1.24 0 0 10 20 30 40 50 60 70 80 90 Driver RT9605 0 100 10 20 30 Output Current (A) 40 1000 90 900 80 800 70 700 70 80 90 100 GM RCOMM = 430Ω 60 600 I ADJ (uA) Frequency (kHz) 60 Output Current (A) Frequency vs. RRT 500 400 GM3 GM2 GM1 50 40 30 300 200 20 100 10 0 0 0 5 10 15 20 25 30 35 40 45 50 55 60 0 10 20 30 40 50 60 70 80 90 100 110 VC (mV) RRT (k (kΩ) ٛ) VVID125 vs. Temperature Frequency vs. Temperature 0.815 350 0.81 300 0.805 250 Frequency (kHz) V VID125 (V) 50 0.8 0.795 0.79 200 150 100 0.785 50 0.78 0 RRT = 16kΩ -25 -10 5 20 35 50 65 80 Temperature (°C) DS8800A-06 April 2011 95 110 125 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) www.richtek.com 7 RT8800A Load Transient Response Load Transient Response V CORE (200mV/Div) V CORE (200mV/Div) UGATE1 (20V/Div) UGATE1 (20V/Div) UGATE2 (20V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div) UGATE3 (20V/Div) phase 1, IOUT = 5A to 85A @SR = 93A/us) phase2, IOUT = 5A to 85A @SR = 93A/us) Time (2.5μs/Div) Time (2.5μs/Div) Load Transient Response Over Current Protection V CORE (200mV/Div) Short While Turn_On UGATE1 (20V/Div) IL1+IL2 (50A/Div) V CORE (1V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div) phase 3, IOUT = 5A to 85A @SR = 93A/us) PWM1 (10V/Div) VCOMP (2V/Div) Time (2.5μs/Div) Time (10ms/Div) Over Current Protection VID On the Fly Falling IOUT = 5A Short After Turn_On PWM (5V/Div) IL1+IL2 (50A/Div) V CORE (100mV/Div) V CORE (1V/Div) VFB (200mV/Div) PWM1 (10V/Div) VID0 (2V/Div) VCOMP (2V/Div) Time (10ms/Div) www.richtek.com 8 Time (25μs/Div) DS8800A-06 April 2011 RT8800A VID On the Fly Falling VID On the Fly Rising IOUT = 90A V CORE (50mV/Div) IOUT = 5A PWM (5V/Div) PWM (5V/Div) V CORE (200mV/Div) VFB (200mV/Div) VFB (200mV/Div) VID0 (2V/Div) VID0 (2V/Div) Time (25μs/Div) Time (10μs/Div) VID On the Fly Rising IOUT = 90A PWM (5V/Div) V CORE (200mV/Div) VFB (200mV/Div) VID0 (2V/Div) Time (10μs/Div) DS8800A-06 April 2011 www.richtek.com 9 RT8800A Applications Information The RT8800A is a general-purposed multi-phase synchronous buck controller dedicating for high power density applications. The RT8800A operates with 2 or 3 synchronous buck switching stages in interleaved phase set automatically. The multiphase architecture provides high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. Initialization The RT8800A initiates after 2 pins are ready : VDD pin power on reset (POR) and DVD pin is higher than 1V. VDD POR is to make sure RT8800A is powered by a voltage high enough for normal work. The rising threshold voltage of VDD POR is 4.2V typically. At VDD POR, RT8800A checks PWM3 status to determine phase number of operation. Pull high PWM3 for two-phase operation. The unused current sense pins should be connected to GND or left floating. DVD is to make sure that ATX12V is ready for the companion MOSFET drivers to work normally. Connect a voltage divider from ATX12V to DVD pin as shown in the Typical Application Circuit. Make sure that DVD pin voltage is below its threshold voltage before drivers are ready and above its threshold voltage for minimum ATX12V during normal operation. If one of VDD and DVD is not ready, RT8800A keeps its PWM outputs high impedance and the companion drivers turn off both upper and lower MOSFETs. Soft-Start After VDD and DVD are ready, RT8800A initiates its soft start cycle as shown in Figure 1. The error amplifier and PWM comparator are triple-input devices. The non-inverting input whichever is smaller dominates the behavior of the device. The soft start function generates SS and SSE for the non-inverting input of PWM comparator and error amplifier respectively where SSE = SS - VGS. VGS is threshold voltage of internal MOSFET. The typical softstart duration is 3ms. The soft start can be sliced to several time frames with specific operation respectively. 1) Mode 1 (SS < VRAMP_Valley) Initially the COMP stays in the positive saturation due to offset of the error amplifier. Since SS < VRAMP_Valley, the PWM comparator keeps its output low and VOUT is zero. 2) Mode 2 (VRAMP_Valley < SS < Cross-over) Since VRAMP_Valley < SS < Cross-over, SS dominates the non-inverting inputs of the PWM comparators. The PWM duty cycles increase according to the ramping up SS signal. The output voltage ramps up accordingly. However as VOUT increases, the difference between VOUT and SSE (SS - VGS) is reduced and COMP leaves the saturation and declines. The takeover of SS lasts until it meets the COMP. During this interval, since the feedback path is broken, the converter is operated in the open loop. 3) Mode3 (Cross-over < SS < VGS + VPI) When the VCOMP takes over the non-inverting input for PWM Amplifier and when SSE (SS - VGS) < VPI, the output of the converter follows the ramp input, SSE (SS - VGS). Before the crossover, the output follows SS signal. And when VCOMP takes over SS, the output is expected to follow SSE (SS - VGS). Therefore the deviation of VGS is represented as the falling of VOUT for a short while. The COMP is observed to keep its decline when it passes the cross-over, which shortens the duty width and hence the falling of VOUT happens. Since there is a feedback loop for the error amplifier, the output's response to the ramp input, SSE (SS - VGS) is lower than that in Mode 2. 4) Mode 4 (SS > VGS + VPI) When SS > VGS + VPI, the output of the converter follows the desired VPI signal and the soft start completes. However, the SS keeps ramping up to 3.3V and stays there. The PGOOD pin trips to high impedance as SS reaches 3.3V. Soft Start SSE FB PI + -EA + SS + + - PWM Figure 1. Soft Start Block Diagram. www.richtek.com 10 DS8800A-06 April 2011 RT8800A LX RX COMP VRAMP_Valley CX + VX - T1 + S/H CKT Cross-over ILX RLX VOUT - SS_Internal + IX V CORE T3 SSE_Internal Figure 2 T2 RCOMM Time-Sharing DCR Current Sensing RT8800A adopts an innovative time-sharing DCR current sensing technique to sense the phase currents for phase current balance (phase thermal balance), over current protection and load line regulation as shown in Figure 3. The current sensing amplifier GM samples and holds voltages VX across the current sensing capacitor CX by turns in a switching cycle. According to the Basic Circuit Theory, if Figure 3 Figure 4 and 5 show the linearity of GM amplifier and its test circuit respectively. A voltage source is applied to ISPx while other ISPx pins are short to VOUT. The voltage VADJ across resistor RADJ is measured. It is observed from Figure 5 shows that all ISPx share the same transconductance linearity and voltage offset. LX = R X × C X then VX = ILX × RLX RLX Consequently, the sensing current IX is proportional to inductor current ILX and is expressed as The sensed current IX is used for current balance, over current protection, and droop tuning as described as followed. Since all phases share one common GM, GM offset and linearity variation effect are eliminated in practical applications. As sub-milli-ohmgrade inductors are widely used in modern motherboards, slight mismatch of GM amplifiers offset and linearity results in considerable current shift between phases. The time sharing DCR current sensing technical is extremely important to guarantee phase current balance at mass production. DS8800A-06 April 2011 GM3 60 50 I ADJ (uA) ILX × RLX IX = R COMM GM 70 GM2 40 30 GM1 20 10 0 0 20 40 60 80 100 VXC (mV) Figure 4. The Linearity of GMx www.richtek.com 11 RT8800A IADJ PI + VADJ - Over Current Protection EA + ISP1 SUM/N ISP2 ISP3 MUX DAC_OUT S/H RT9401 + GM IX MUX VX + - RADJ PWM (5V/Div) ICOMMON VCORE Figure 5. Test Circuit of GM. IL (5V/Div) Phase Current Balance Time (25ms/Div) The sampled and held phase current IX are injected to the corresponding saw tooth waveforms of PWM comparators. If phase current IX is larger than other phase currents, its saw tooth waveform will be lift higher than the others. The RT8800A reduces the duty cycle of corresponding phase to decrease the phase current accordingly, vice versa. Figure 7. The Over Current Protection in the interval Over Current Protection Over Current Protection RT8800A uses an external resistor RIMAX connected to IMAX pin to generate a reference current IIMAX for over current protection: IIMAX = VIMAX RIMAX where VIMAX is 0.8V typical. OCP comparator compares each sensed phase current IX with this reference current as shown in Figure 6. Equivalently, the maximum phase current is calculated as : ILX(MAX) 3 VIMAX R COMM = 2 RIMAX RLX - 1/3 IX 1/2 IIMAX Figure 6. Over Current Comparator. The RT8800A uses hiccup mode to eliminate nuisance detection of OCP or reduce output current when output is shorted to ground as shown in Figure 7 and 8. The RT8800A shuts down and latches off after 3 time OCP hiccups. It can only restart by resetting one of VDD or DVD pin. www.richtek.com 12 VSS (5V/Div) (5V/Div) Time (25ms/Div) Figure 8. Over Current Protection at steady state Voltage Reference for Converter Output & Load Droop OCP Comparator + PWM The output voltage is sensed at FB pin. The RT8800A receives an external reference voltage at PI pin as the non-inverting of the error amplifier and precisely regulates the FB voltage to this reference voltage. The RT8800A can provide Intel® VRD10.x or AMD® K8 compliant output voltage when companioned with DAC generator RT9401A/B as shown in Figure 9. The RT9401A/B receives VID[0:4] and produces DAC_OUT that complies with VRD10.x or K8 VID table. The DAC_OUT is fed to PI pin through a resistor RADJ as the reference voltage of the error amplifiers. The VID125 provides a 12.5mV offset for full compliance of VRD10.x table. DS8800A-06 April 2011 RT8800A A negative IX is required to correctly sense the negative voltage. However, the RT8800A CANNOT provide a negative IX and consequently cannot sense negative inductor current. This results in dead zone of load line performance as shown in Figure 10. Therefore a technique as shown in Figure 11 is required to eliminate the dead zone of load line at light load condition. COMP VCORE FB RFB - PI + 1/2 IOFS RADJ DAC_OUT VID [0 : 4] Current Mirror OVP 0.8V VREF IOFS RT9401 RVID125 500mV 1 sum(I X ) 3 + VCORE IX SUM/N Load Line - VID125 DAC_OUT VOFFSET Figure 9 Spec_High RCSN > RCSN = RCSN < Spec_Low Droop and Load Lind Setting The sampled and held phase current IX are summed to get sum(IX). RT8800A then sinks a current that is 1/3 sum(IX) and produces a droop voltage that is proportional to the average phase voltage. Figure 10 IL VADJ = 1/3 sum(IX) x RADJ VADJ is then subtracted form DAC generator output as the real reference voltage at non-inverting input of the error amplifier. Consequently, load line slope is calculated as: RX ΔVCORE R x RLX Load Line = = − ADJ ΔICORE 3 x R COMM + VID125 pin is internally regulated to be around 0.8V. An external resistor R VID125 between VID125 and GND generates the offset current IOFS = 0.8V . R VID125 FB pin will sink a current which is half of IOFS because of a current mirror FB and VID125. The output offset voltage is calculated to be 0.8V × 1 × R VOFS = FB R VID125 2 Thus, the output voltage becomes = VFB + 0.8V × RFB 2 × R VID125 Note : To maintain VID125 voltage around 0.8V, RVID125 must not be less than 16kΩ. Dead Zone Elimination and Output Voltage Offset Function RT8800A samples and holds inductor valley current by time-sharing sourcing a current IX to RCOMM. At light load condition the inductor valley current and consequently the voltage VX across the sensing capacitor may be negative. DS8800A-06 April 2011 + VX - CX LX RL_X RCOMM VCORE DSKY RCSN Output Voltage Offset Function VCORE = VFB + VOFS ICORE VCORE - VF IX RCS Figure 11 Referring to Figure 11, the Schottky diode provides a constant voltage drop VF with enough bias current. IX is expressed as: IX = VF + ILX_Valley × RLX ILX_Valley × RLX + R CSN R COMM (1) To make sure RT8800A could sense the inductor current, right hand side of Equation (1) should always be positive: VF + ILX_Valley × RLX ILX_Valley × RLX + ≥0 R CSN R COMM (2) Since VF >> (ILX_Valley x RLX) in practical application, Equation (2) could be simplified as: ILX_Valley × RLX VF ≥ R CSN R COMM (3) www.richtek.com 13 RT8800A Rewriting Equation (3), we get Current Ratio Setting VF × R COMM ≥ R CSN ILX_Valley × RLX (4) The technique mentioned above also provides output voltage offset function specified by Intel ® VRD10.x. The offset voltage level is calculated as: R ADJ VOFFSET = VF R CSN Enough bias current is required for a Schottky to act like a voltage source. Users should choose the appropriate R CS based on the IV characteristic of the diode (Figure 12) I IV Characteristic Zone 1 Current ratio adjustment is possible as described below. It is important for achieving thermal balance in practical application where thermal conditions between phases are not identical. Figure 13 shows the application circuit of GM for current ratio requirement. According to Basic Circuit Theory, if LX = (R SX //RPX ) × C X then RLX RPX × ILX × RLX R SX + RPX With other phase kept unchanged, this phase would share (RPX+RSX)/RPX times current than other phases. Figure 14 and 15 show different current ratio setting for the power stage when Phase 3 is programmed 2 times current than other phases. Figure 16 and 17 compare the above current ratio setting results. VX = Zone 2 V Figure 12 Over Voltage Protection (OVP) The RT8800A continuously monitors voltage at FB pin. OVP is triggered if FB voltage is 500mV higher than the voltage at PI pin. RT8800A latches off and turns on lower MOSFET to protect the load from damage upon on OVP trip. It can only be reset by DVD and VDD pins. www.richtek.com 14 RLX RSX CX ILX + VX - T RPX VOUT + According to Figure 12, the forward voltage of diode will be different results from the different conduction current. So when the characteristic of diode in the circuit you design is in zone 1, this will result in Spec. mis-met. It is because when the VCORE is changed during DVID, the node VCORE - VF is also changed to produce the differential conduction current of diode ΔI and the ΔI will result in producing the differential forward voltage of diode ΔVF Referring to Equation (1). The ΔVF would get ΔIX. Then the VCORE must be subtracted the extra voltage V(EXT)(ΔIX x RADJ ) during DVID. So you will get the ΔVCORE = V(MAX) - V(MIN) - V(EXT) during DVID tests. In order to reduce the effect results from diode. The better choice is to decrease the Rcs to increase the conduction current of diode I to get better V characteristic of diode in Zone 2. LX T Figure 13 IL3 1.5uH 3k 1m 1uF 3k Figure 13. GM4 Setting for current ratio function. IL1 to L2 1.5uH 1m 1.5k 1uF Figure 14. GM1 to GM3 Setting for current ratio function. DS8800A-06 April 2011 RT8800A Current Balance Function 40 Power Sequence & SS DVD pin external resistor and SS pin capacitor. IL3 35 PCB Layout 30 I LX (A) a.Sense for current sense GM amplifier input. IL2 25 b.Refer to layout guide for other items. IL1 20 Voltage Loop Setting 15 10 Design Example 5 Given: 0 0 20 40 60 80 100 VIN = 12V I CORE (A) VCORE = 1.5V Figure 15 ILOAD(MAX) = 100A Current Ratio Function 45 VDROOP = 100mV at full load (1mΩ Load Line) IL3 40 OCP trip point set at 35A for each channel (S/H) 35 DCR = 1mΩ of inductor at 25°C 30 I LX (A) Apply for four phase converter L = 1.5μH 25 IL2 IL1 20 COUT = 8000μF with 5mΩ equivalent ESR. 15 1. Compensation Setting 10 a. Modulator Gain, Pole and Zero: 5 From the following formula: 0 0 15 30 45 60 75 90 I CORE (A) Figure 16 Design Procedure Suggestion a.Output filter pole and zero (Inductor, output capacitor value & ESR). b.Error amplifier compensation & sawtooth wave amplitude (compensation network). Current Loop Setting Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB) where VRAMP : ramp amplitude of saw-tooth wave LC Filter Pole = 1.45kHz and ESR Zero =3.98kHz b. EA Compensation Network: Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and use the Type 2 compensation scheme shown in Figure 21. By calculation, the F Z = 0.88kHz, FP = 322kHz and Middle Band Gain is 3.19 (i.e 10.07dB). a.GM amplifier S/H current (current sense component DCR, ICOMMON pin external resistor value). C2 68pF RB2 b.Over-current protection trip point (RICOMMON1 resistor). RB1 VRM Load Line Setting a.Droop amplitude (PI pin resistor). b.No load offset (RICOMMON2) DS8800A-06 April 2011 4.7k C1 15k 12nF EA + Figure 17. Type 2 compensation network of EA www.richtek.com 15 RT8800A 2. Over-Current Protection Setting Consider the temperature coefficient of copper 3900ppm/°C, IL × DCR = 150 μA RICOMMON1 be parallel and as short as possible. R&C filter of choke should place close to PWM and the R & C connect directly to the pin of each output choke, use 10 mil differencial pair, and 20 mil gap to other phase pair. Less via as possible. 2. Switching ripple current path: IL × 1.39m Ω = 150 μA 330Ω a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. IL = 35.6A c. The return path of input and output capacitor. Layout Considerations Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: The current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3 and ICOMMON should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should SW1 d. Separate the power and signal GND. e. The switching nodes (the connection node of high/ low side MOSFET and inductor) is the most noisy points. Keep them away from sensitive small-signal node. f . Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET. L1 VOUT VIN RIN COUT CIN RL V SW2 L2 Figure 18. Power Stage Ripple Current Path www.richtek.com 16 DS8800A-06 April 2011 RT8800A Next to IC +12V or +5V +12V 0.1uF VCC BST CBP Next to IC LO1 SW RT9603 +5VIN VCC RT CBOOT DRVH VIN PWM CIN GND VCORE COUT COMP CC RT8800A RICOM RC ICOMMON DRVL Locate next to FB Pin FB GND RFB CSPx Locate near MOSFETs PI GND RDRD Figure 19. Layout Consideration Figure 20 DS8800A-06 April 2011 www.richtek.com 17 RT8800A Figure 21 Figure 22 www.richtek.com 18 DS8800A-06 April 2011 RT8800A Figure 23 DS8800A-06 April 2011 www.richtek.com 19 RT8800A Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 V-Type 16L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 20 DS8800A-06 April 2011