RT8152E/F Single-Phase PWM Controller for CPU / GPU Core Power Supply General Description Features The RT8152E/F is a single phase PWM controller with integrated MOSFET drivers. Moreover, it is compliant with Intel IMVP6.5 Voltage Regulator Specification to fulfill its mobile CPU core and Render core voltage regulator requirements. The RT8152E/F adopts G-NAVP (GreenNative AVP), which is a Richtek's proprietary topology derived from finite DC gain compensator constant on-time mode, making it an easy setting PWM controller meeting all Intel AVP (Active Voltage Positioning) mobile CPU/ Render requirements. The output voltage of the RT8152E/ F is set by 7-bit VID code. The built-in high accuracy DAC converts the VID code ranging from 0V to 1.5V with 12.5mV per step. The system accuracy of the controller can reach 1.5%. The part supports VID on-the-fly and mode change on-the-fly functions that are fully compliant with IMVP6.5 specification. It operates in single phase and diode emulation modes. It can reach up to 90% efficiency in different modes according to different loading conditions. The droop load line can be easily programmed by setting the DC gain of the error amplifier. W ith proper compensation, the load transient can achieve optimized AVP performance. This chip controls soft-start and output transition slew rate via a capacitor. It supports both DCR and sense resistor current sensing. The RT8152E/F provides power good and thermal throttling output signals for IMVP6.5 Render core specification, and additional clock enabling for CPU core specification. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and thermal shutdown. The RT8152E/F is available in WQFN-32L 5x5 small foot print package. l Applications l l l IMVP6.5 CPU / Render Core Voltage Regulator AVP Step-Down Converter Notebook / Desktop Computer / Servers l l l l l l l l l l l l l l l l l l l l Single Phase PWM Controller with Integrated MOSFET Driver Low-Gain Compensator with CCRCOT Topology (Constant Current Ripple Constant On Time) 7-bit DAC 0.8% DAC Accuracy 1.5% or 11.5mV System Accuracy Fixed VBOOT (For CPU Core Only) Differential Remote Voltage Sensing G-NAVP Topology (Green-Native AVP) Programmable Output Transition Slew Rate Control System Thermal Compensated AVP Ringing Free Mode at Light Load Condition Fast Transient Response IMVP6.5 Compatible Power Management States Power Good Clock Enable Output (For CPU Core Only) Thermal Throttling Current Monitor Output Switching Frequency Up to 1MHz OVP, UVP, OCP, OTP, UVLO, NVP 32-Lead WQFN Package RoHS Compliant and Halogen Free Ordering Information RT8152 Package Type QW : WQFN-32L 5x5 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) VRON Power E : 1.05V F : 3.3V Note : Richtek products are : } ments of IPC/JEDEC J-STD-020. } DS8152E/F-04 April 2011 RoHS compliant and compatible with the current requireSuitable for use in SnPb or Pb-free soldering processes. www.richtek.com 1 RT8152E/F Marking Information Pin Configurations (TOP VIEW) VRTT VID0 VID1 VID2 VID3 VID4 VID5 VID6 RT8152EGQW RT8152EGQW : Product Number RT8152E GQW YMDNN YMDNN : Date Code 32 31 30 29 28 27 26 25 RT8152FGQW NTC OCSET DPRSLPVR VRON PGOOD 1 24 2 23 3 22 CLKEN VCC SOFT 6 RT8152FGQW : Product Number YMDNN : Date Code 21 GND 5 20 19 7 18 33 8 17 9 10 11 12 13 14 15 16 RGND CM CMSET VSEN FB COMP ISEN_N ISEN RT8152F GQW YMDNN 4 BOOT UGATE PHASE PGND LGATE PVDD GND TON WQFN-32L 5x5 Typical Application Circuit VIN 5V to 25V RT8152E/F R1 5V 7 VCC TON 17 R2 R3 19 C2 C5 C3 C1 31 VID0 PVDD VID0 VID2 30 VID1 29 VID2 VID3 28 VID4 27 VID4 26 VID5 25 VID6 3 DPRSLPVR VID1 VID5 VID6 DPRSLPVR VID3 4 VRON VRON BOOT 24 UGATE 23 PHASE 22 LGATE 20 PGND R4 C4 Q1 L1 R5 R8 VOUT Q2 R6 21 D1 R7 C7 COUT C6 16 ISEN ISEN_N 15 CMSET R13 11 C9 VSEN 12 FB 13 5 PWRGD 6 CLKEN 32 VRTT CLKEN VRTT R9 R10 R14 NTC2 C13 CPU VCC_SNS COMP 14 R18 R19 R21 R20 VOUT NTC1 R11 RGND 9 VCCP 3.3V VCC C12 PGOOD 1 R15 R16 2 NTC OCSET SOFT 8 CPU VSS_SNS C10 R22 CM 10 CM R12 R17 GND 18, 33 (Exposed Pad) C11 CPU VSS_SNS Figure 1. CPU Core Voltage Regulator www.richtek.com 2 DS8152E/F-04 April 2011 RT8152E/F VIN 5V to 25V RT8152E/F R1 5V 7 VCC TON 17 R2 R3 19 PVDD C2 31 VID0 VID0 PHASE 22 21 VID4 28 VID3 27 VID4 VID5 26 VID2 VID3 VID5 25 VID6 3 DPRSLPVR 4 VRON VID6 DPRSLPVR VRON 6 CLKEN 5 PWRGD 32 VRTT PGND ISEN C4 Q1 L1 R5 R8 VOUT Q2 R6 D1 CMSET R13 11 C9 VSEN 12 FB 13 C13 GPU VCC_SNS COMP 14 R18 R19 R21 R20 VOUT NTC1 1 R16 2 NTC OCSET SOFT 8 GPU VSS_SNS C10 R22 CM 10 CM R12 R17 NTC2 COUT ISEN_N 15 RGND 9 R15 C7 16 C12 VRTT R7 C6 R11 3.3V R14 LGATE 20 R4 PGOOD VCCP VCC BOOT 24 UGATE 23 30 VID1 29 VID2 VID1 R9 C5 C3 C1 GND 18, 33 (Exposed Pad) C11 GPU VSS_SNS Figure 2. Render Core Voltage Regulator Functional Pin Description Pin No. Pin Name Pin Function 1 NTC Thermal Detection Input for VRTT Circuit. Connect this pin with a resistor divider from VCC using NTC on the top to set the thermal management threshold level. 2 OCSET Over Current Protection Setting. Connect a resistor voltage divider from VCC to ground, the joint of the resistor divider is connected to OCSET pin, with a voltage VOCSET, to set the over current threshold I LIM. 3 4 DPRSLPVR VRON Deeper Sleep Mode Signal. Voltage Regulator Enabler. 5 PGOOD Power Good Indicator. 6 CLKEN 7 VCC 8 SOFT DS8152E/F-04 April 2011 Inverted Clock Enable. Pull high by a resistor for CPU core application. This open-drain pin is an output indicating the start of the PLL locking of the clock chip. Connect to GND for Render application. Chip Power. Soft-Start. This pin provides soft-start function and slew rate controller. The capacitance of the slew rate control C is restricted to be larger than 10nF. The feedback voltage of the converter follows the ramping voltage on the SOFT pin during soft-start and other voltage transitions according to different mode of operation and VID change. To be continued www.richtek.com 3 RT8152E/F Pin No. Pin Name Pin Function Return Ground. This pin is the negative node of the differential remote voltage sensing. 9 RGND 10 CM 11 CMSET 12 VSEN 13 FB Feedback. This is the negative input node of the error amplifier. 14 COMP Compensation. This pin is the output node of the error amplifier. 15 ISEN_N Negative input of the current sense. ISEN TON Positive input of the current sense. Connect this pin to VIN with one resistor. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Driver Power. 16 17 18, 33 (Exposed Pad) 19 GND PVDD 20 21 LGATE PGND 22 PHASE 23 UGATE 24 BOOT 25 to 31 VID6 to VID0 32 www.richtek.com 4 VRTT Current Monitor Output. This pin outputs a voltage proportional to the output current. Current Monitor Output Gain Externally Setting. Connect this pin with one resistor to VSEN while CM pin is connected to ground with one another resistor. In such wa y, current monitor output gain can be set by the ratio of these two resistors. Positive Voltage Sensing Pin. This pin is the positive node of the differential voltage sensing. Lower Gate Drive. This pin drives the gate of the low side MOSFETs. Driver Ground. This pin is return node of the high side MOSFET driver. Connect this pin to the high side MOSFET sources together with the low side MOSFET drains and the inductor. Upper Gate Drive. This pin drives the gate of the high side MOSFETs. Bootstrap Power Input. This pin powers the high side MOSFET drivers. Connect this pin to bootstrap capacitor. Voltage ID. DAC voltage identification inputs for IMVP6.5. The logic threshold is 30% of the VCCP as the maximum value for low state and 70% of the VCCP as the minimum value for the high state. Voltage Regulator Thermal Throttling. This open-drain output pin will be pulled low when the preset temperature level is exceeded. DS8152E/F-04 April 2011 RT8152E/F Table 1. IMVP6.5 VID Code Table VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 0 0 0 0 0 0 0 1.5000V 0 1 0 0 0 0 1 1.0875V 0 0 0 0 0 0 1 1.4875V 0 1 0 0 0 1 0 1.0750V 0 0 0 0 0 1 0 1.4750V 0 1 0 0 0 1 1 1.0625V 0 0 0 0 0 1 1 1.4625V 0 1 0 0 1 0 0 1.0500V 0 0 0 0 1 0 0 1.4500V 0 1 0 0 1 0 1 1.0375V 0 0 0 0 1 0 1 1.4375V 0 1 0 0 1 1 0 1.0250V 0 0 0 0 1 1 0 1.4250V 0 1 0 0 1 1 1 1.0125V 0 0 0 0 1 1 1 1.4125V 0 1 0 1 0 0 0 1.0000V 0 0 0 1 0 0 0 1.4000V 0 1 0 1 0 0 1 0.9875V 0 0 0 1 0 0 1 1.3875V 0 1 0 1 0 1 0 0.9750V 0 0 0 1 0 1 0 1.3750V 0 1 0 1 0 1 1 0.9625V 0 0 0 1 0 1 1 1.3625V 0 1 0 1 1 0 0 0.9500V 0 0 0 1 1 0 0 1.3500V 0 1 0 1 1 0 1 0.9375V 0 0 0 1 1 0 1 1.3375V 0 1 0 1 1 1 0 0.9250V 0 0 0 1 1 1 0 1.3250V 0 1 0 1 1 1 1 0.9125V 0 0 0 1 1 1 1 1.3125V 0 1 1 0 0 0 0 0.9000V 0 0 1 0 0 0 0 1.3000V 0 1 1 0 0 0 1 0.8875V 0 0 1 0 0 0 1 1.2875V 0 1 1 0 0 1 0 0.8750V 0 0 1 0 0 1 0 1.2750V 0 1 1 0 0 1 1 0.8625V 0 0 1 0 0 1 1 1.2625V 0 1 1 0 1 0 0 0.8500V 0 0 1 0 1 0 0 1.2500V 0 1 1 0 1 0 1 0.8375V 0 0 1 0 1 0 1 1.2375V 0 1 1 0 1 1 0 0.8250V 0 0 1 0 1 1 0 1.2250V 0 1 1 0 1 1 1 0.8125V 0 0 1 0 1 1 1 1.2125V 0 1 1 1 0 0 0 0.8000V 0 0 1 1 0 0 0 1.2000V 0 1 1 1 0 0 1 0.7875V 0 0 1 1 0 0 1 1.1875V 0 1 1 1 0 1 0 0.7750V 0 0 1 1 0 1 0 1.1750V 0 1 1 1 0 1 1 0.7625V 0 0 1 1 0 1 1 1.1625V 0 1 1 1 1 0 0 0.7500V 0 0 1 1 1 0 0 1.1500V 0 1 1 1 1 0 1 0.7375V 0 0 1 1 1 0 1 1.1375V 0 1 1 1 1 1 0 0.7250V 0 0 1 1 1 1 0 1.1250V 0 1 1 1 1 1 1 0.7125V 0 0 1 1 1 1 1 1.1125V 1 0 0 0 0 0 0 0.7000V 0 1 0 0 0 0 0 1.1000V 1 0 0 0 0 0 1 0.6875V To be continued DS8152E/F-04 April 2011 www.richtek.com 5 RT8152E/F VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output VID6 VID5 VID4 VID3 VID2 VID1 VID0 Output 1 0 0 0 0 1 0 0.6750V 1 1 0 0 0 0 1 0.2875V 1 0 0 0 0 1 1 0.6625V 1 1 0 0 0 1 0 0.2750V 1 0 0 0 1 0 0 0.6500V 1 1 0 0 0 1 1 0.2625V 1 0 0 0 1 0 1 0.6375V 1 1 0 0 1 0 0 0.2500V 1 0 0 0 1 1 0 0.6250V 1 1 0 0 1 0 1 0.2375V 1 0 0 0 1 1 1 0.6125V 1 1 0 0 1 1 0 0.2250V 1 0 0 1 0 0 0 0.6000V 1 1 0 0 1 1 1 0.2125V 1 0 0 1 0 0 1 0.5875V 1 1 0 1 0 0 0 0.2000V 1 0 0 1 0 1 0 0.5750V 1 1 0 1 0 0 1 0.1875V 1 0 0 1 0 1 1 0.5625V 1 1 0 1 0 1 0 0.1750V 1 0 0 1 1 0 0 0.5500V 1 1 0 1 0 1 1 0.1625V 1 0 0 1 1 0 1 0.5375V 1 1 0 1 1 0 0 0.1500V 1 0 0 1 1 1 0 0.5250V 1 1 0 1 1 0 1 0.1375V 1 0 0 1 1 1 1 0.5125V 1 1 0 1 1 1 0 0.1250V 1 0 1 0 0 0 0 0.5000V 1 1 0 1 1 1 1 0.1125V 1 0 1 0 0 0 1 0.4875V 1 1 1 0 0 0 0 0.1000V 1 0 1 0 0 1 0 0.4750V 1 1 1 0 0 0 1 0.0875V 1 0 1 0 0 1 1 0.4625V 1 1 1 0 0 1 0 0.0750V 1 0 1 0 1 0 0 0.4500V 1 1 1 0 0 1 1 0.0625V 1 0 1 0 1 0 1 0.4375V 1 1 1 0 1 0 0 0.0500V 1 0 1 0 1 1 0 0.4250V 1 1 1 0 1 0 1 0.0375V 1 0 1 0 1 1 1 0.4125V 1 1 1 0 1 1 0 0.0250V 1 0 1 1 0 0 0 0.4000V 1 1 1 0 1 1 1 0.0125V 1 0 1 1 0 0 1 0.3875V 1 1 1 1 0 0 0 0.0000V 1 0 1 1 0 1 0 0.3750V 1 1 1 1 0 0 1 0.0000V 1 0 1 1 0 1 1 0.3625V 1 1 1 1 0 1 0 0.0000V 1 0 1 1 1 0 0 0.3500V 1 1 1 1 0 1 1 0.0000V 1 0 1 1 1 0 1 0.3375V 1 1 1 1 1 0 0 0.0000V 1 0 1 1 1 1 0 0.3250V 1 1 1 1 1 0 1 0.0000V 1 0 1 1 1 1 1 0.3125V 1 1 1 1 1 1 0 0.0000V 1 1 0 0 0 0 0 0.3000V 1 1 1 1 1 1 1 0.0000V www.richtek.com 6 DS8152E/F-04 April 2011 DS8152E/F-04 April 2011 VSEN COMP FB SOFT RGND VID0 VID1 VID2 VID3 VID4 VID5 VID6 GND DAC VBOOT VCC + - Soft Start MUX VDAC NTC - + ERROR AMP UVP Trip Point OVP Trip Point NVP Trip Point Mode Selection VRTT CLKEN - + + - + - PGOOD VCC Offset Cancellation OTP Power On Reset & Central Logic VRON - + Mode Selection DPRSLPVR + TON CM Driver Logic Control CCRCOT On-Time Generator FB PWMCP OCP Setting OCSET 10 + CM CMSET ISEN ISEN_N PGND LGATE PVDD PHASE UGATE BOOT RT8152E/F Function Block Diagram www.richtek.com 7 RT8152E/F Absolute Maximum Ratings l l l l l l l l l l l l l l l l l l l (Note 1) VCC to GND ------------------------------------------------------------------------------------------------RGND, PGND to GND -------------------------------------------------------------------------------------VIDx to GND ------------------------------------------------------------------------------------------------DPRSLPVR, VRON to GND -----------------------------------------------------------------------------PGOOD, CLKEN, VRTT to GND -----------------------------------------------------------------------VSEN, FB, COMP, SOFT, OCSET, CM, CMSET, NTC to GND ----------------------------------ISEN, ISEN_N to GND ------------------------------------------------------------------------------------PVDD to PGND ---------------------------------------------------------------------------------------------LGATE to PGND DC -------------------------------------------------------------------------------------------------------------<20ns ---------------------------------------------------------------------------------------------------------PHASE to PGND DC -------------------------------------------------------------------------------------------------------------<20ns ---------------------------------------------------------------------------------------------------------BOOT to PHASE ------------------------------------------------------------------------------------------UGATE to PHASE DC -------------------------------------------------------------------------------------------------------------<20ns ---------------------------------------------------------------------------------------------------------TON to GND -------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN−32L 5x5 --------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN−32L 5x5, θJA ---------------------------------------------------------------------------------------WQFN−32L 5x5, θJC --------------------------------------------------------------------------------------Junction Temperature -------------------------------------------------------------------------------------Storage Temperature Range -----------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) -------------------------------------------------------------------------------MM (Machine Mode) --------------------------------------------------------------------------------------- Recommended Operating Conditions l l l l −0.3V to (PVDD + 0.3V) −2.5V to 7.5V −0.3V to 28V −8V to 38V −0.3V to 6.5V −0.3V to (BOOT − PHASE) −5V to 7.5V −0.3V to 28V 2.778W 36°C/W 7°C/W 150°C −65°C to 150°C 260°C 2kV 200V (Note 4) Supply Voltage, VCC --------------------------------------------------------------------------------------Battery Voltage, VIN ---------------------------------------------------------------------------------------Junction Temperature Range ----------------------------------------------------------------------------Ambient Temperature Range ----------------------------------------------------------------------------- www.richtek.com 8 −0.3V to 6.5V −0.3V to 0.3V −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to (VCC + 0.3V) −0.3V to 6.5V 4.5V to 5.5V 5V to 25V −40°C to 125°C −40°C to 85°C DS8152E/F-04 April 2011 RT8152E/F Electrical Characteristics (VCC = 5V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Input Supply Current IVCC + IPVDD RTON = 130kΩ, VRON = 3.3V, No Loading Current -- -- 10 mA Shutdown Current IVCC + IPVDD VRON = 0V -- -- 5 µA 20 -- µA Soft-Start/Slew Rate Control (based on 10nF CSS) Soft-Start / Soft-Shutdown Normal VID Change Slew Current Deeper Sleep Exit/VID Change Slew Current Reference and DAC DC Accuracy Boot Voltage ISS1 SOFT = 1.5V -- ISS2 SOFT = 1.5V 40 50 60 µA ISS3 For Render Mode Only, SOFT = 1.5V 80 100 120 µA VFB VDAC = 0.7500 − 1.5000 (No Load, Active Mode) −0.8 0 0.8 %VID VDAC = 0.5000 − 0.7500 −7.5 0 7.5 mV RT8152E 1.089 1.1 1.111 RT8152F 1.188 1.2 1.212 70 80 -- dB -- 10 -- MHz -- 5 -- V/µs VBOOT V Error Amplifier DC Gain RL = 47kΩ (Note 5) Gain-Bandwidth Product GBW CLOAD = 5pF Slew Rate SRCOMP CLOAD = 10pF (Gain = −4, Rf = 47kΩ, VOUT = 0.5V − 3V) Output Voltage Range VCOMP RL = 47kΩ 0.5 -- 3.6 V VCOMP = 2V 200 250 -- µA VCOMP = 2V -- 20 -- mA Maximum Source Current Maximum Sink Current IOUTEA_COMP (Note 5) Current Sense Amplifier Input Offset Voltage VOSCS ISEN = ISEN_N = 1.5V −1 -- 1 mV Impedance at Neg. Input RISEN_N ISEN_N = 1.5V 1 -- -- MΩ Impedance at Pos. Input RISEN ISEN = 1.5V 1 -- -- MΩ -- 10 -- V/V DC Gain VISEN_IN VDAC = 1.1V, VISEN_IN = ISEN − ISEN_N −50 -- 80 mV TON Pin Output Voltage VTON RTON = 80kΩ, VTON = VDAC = VBOOT −5 0 5 % ON-Time Setting TON IRTON = 80µA, VTON = VDAC = VBOOT -- 350 -- ns R TON Current Range IRTON VTON = VDAC = VBOOT 25 -- 280 µA Minimum Off Time TOFF IRTON = 80µA, VDAC = VBOOT 250 -- 500 ns VUVLO Falling edge, 80mV Hysteresis 3.9 4.1 4.3 V Input Range TON Setting Protection Under Voltage Lock-out Threshold To be continued DS8152E/F-04 April 2011 www.richtek.com 9 RT8152E/F Parameter Symbol Test Conditions Min Typ Max Unit VOVABS (Respect to 1.5V, ±50mV) 1.45 1.5 1.55 V VOV (Respect to VDAC, ±50mV) 250 300 350 mV −450 −400 −350 mV −100 -- -- mV 46.5 50 53.5 mV -- 160 -- °C RT8152E Respect to 1.05V, 70% 0.735 -- -- RT8152F Respect to 3.3V, 70% 2.31 -- -- RT8152E Respect to 1.05V, 30% -- -- 0.315 RT8152F Respect to 3.3V, 30% -- -- 0.99 −1 -- 1 Protection Absolute Over Voltage Protection Threshold Relative Over Voltage Protection Threshold Under Voltage Protection Threshold Negative Voltage Protection Threshold Current Limit Threshold Voltage Thermal Shutdown Threshold VUV VNV VILIM TSD Measured at VSEN respect to unloaded output voltage (UOV) (for 0.8 < UOV < 1.5) Measured at VSEN respect to GND VISEN − VISEN_N = VILIM, VOCSET = 2V, 40 x VILIM = VOCSET Typical hysteresis is 10°C Logic Inputs VIH VRON Threshold VIL Leakage Current of VRON DAC (VID0 − VID6) and DPRSLPVR V µA VIH Respect to 1.05V, 70% 0.77 -- -- VIL Respect to 1.05V, 30% -- -- 0.33 −1 -- 1 CPU Core : VSEN − VBOOT -- −100 -- Render : VSEN − VDAC -- −100 -- IPGOOD = 4mA -- -- 0.4 CPU Core, CLKEN Low to PGOOD High 3 -- 20 Render Mode VRON High to PGOOD High 3 -- 20 -- -- 0.4 V Leakage Current of DAC (VID0 − VID6) and DPRSLPVR V µA Power Good PGOOD Threshold VTH_PGOOD PGOOD Low Voltage VPGOOD PGOOD Delay TPGOOD mV V ms Clock Enable CLKEN Low Voltage VCLKEN For CPU Core Only, ICLKEN = 4mA Thermal Throttling Thermal Throttling Threshold VOT Thermal Throttling Threshold VOT_HY Hysteresis Measure at NTC respect to VCC -- 80 -- %VDD At VCC = 5V -- 230 -- mV VRTT Output Voltage IVRTT = 40mA -- -- 0.4 V 770 800 830 mV Current Monitor Current Monitor Output Voltage in Operating Range VVRTT VDAC = 0.9V, VRCMSET = 0.82V, R CM = 7.5kΩ, R CMSET = 1.5kΩ To be continued www.richtek.com 10 DS8152E/F-04 April 2011 RT8152E/F Parameter Symbol Test Conditions Current Monitor Maximum Output Voltage Min Typ Max Unit -- -- 1.15 V Gate Driver Upper Driver Source R UGATEsr VBOOT − VPHASE = 5V VBOOT − V UGATE = 1V -- 0.7 -- Ω Upper Driver Sink R UGATEsk VUGATE = 1V -- 0.6 -- Ω Lower Driver Source R LGATEsr VPVDD = 5V, VPVDD − VL GATE = 1V -- 0.75 -- Ω Lower Driver Sink R LGATEsk VLGATE = 1V -- 0.5 -- Ω Upper Driver Source/Sink IUGATE Current Lower Driver Source IL GATEsr Current VBOOT − V PHASE = 5V VUGATE = 2.5V -- 3 -- A VLGATE = 2.5V -- 3 -- A Lower Driver Sink Current IL GATEsk VLGATE = 2.5V -- 5 -- A Internal Boot Charging Switch On-Resistance PVDD to BOOT -- 30 -- Ω R BOOT Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design. DS8152E/F-04 April 2011 www.richtek.com 11 RT8152E/F Typical Operating Characteristics VIN = 12.6V, RTON = 150Ω, L = 0.36µH, COUT = 330µF, No Load, TA = 25°C, unless otherwise specified. CCM Efficiency vs. Load Current CCM VCC_SENSE vs. Load Current 100 1.16 90 70 VCC_SENSE (V) Efficiency (%) 1.14 VIN = 8V VIN = 12V VIN = 19V 80 60 50 40 30 20 1.12 VIN = 8V VIN = 12V VIN = 19V 1.10 1.08 1.06 10 VID = 1.15V, DPRSLPVR = Low VID = 1.15V, DPRSLPVR = Low 1.04 0 0 3 6 9 12 15 18 21 24 27 0 30 3 6 9 CCM Efficiency vs. Load Current 0.95 90 0.94 VCC_SENSE (V) Efficiency (%) 60 50 40 30 20 21 24 27 30 VID = 0.9375V, DPRSLPVR = Low 0.92 0.91 0.90 VIN = 8V VIN = 12V VIN = 19V 0.89 0.88 0.87 0.86 10 0.85 VID = 0.9375V, DPRSLPVR = Low 0 0.84 0 3 6 9 12 15 18 21 24 27 0 30 3 6 9 12 15 18 21 24 27 30 Load Current (A) Load Current (A) VCM vs. Load Current RFM Efficiency vs. Load Current 100 1.1 95 1.0 90 0.9 0.8 85 0.7 VIN = 8V VIN = 12V VIN = 19V 80 75 V CM (V) Efficiency (%) 18 0.93 VIN = 8V VIN = 12V VIN = 19V 70 15 CCM VCC_SENSE vs. Load Current 100 80 12 Load Current (A) Load Current (A) 70 VIN = 8V VIN = 12V VIN = 19V 0.6 0.5 0.4 65 0.3 60 0.2 55 0.1 VID = 0.85V, DPRSLPVR = High VID = 0.9375V, DPRSLPVR = Low 0.0 50 0.3 0.6 0.9 1.2 1.5 1.8 2.1 Load Current (A) www.richtek.com 12 2.4 2.7 3 0 5 10 15 20 25 30 Load Current (A) DS8152E/F-04 April 2011 RT8152E/F CPU Mode Power On Render Mode Power On VCC_SENSE (1V/Div) VCC_SENSE (1V/Div) PGOOD (5V/Div) PGOOD (5V/Div) VRON (5V/Div) CLKEN (5V/Div) VRON (5V/Div) VID = 0.9375V, CLKEN Pull High to 3.3V CLKEN (5V/Div) VID = 0.9375V, CLKEN Pull low to GND Time (1ms/Div) Time (1ms/Div) CPU Mode Power Down CCM VID Change Down VCC_SENSE (100mV/Div) CLKEN Pull High to 3.3V VCC_SENSE (1V/Div) PGOOD (5V/Div) UGATE (20V/Div) VRON (5V/Div) LGATE (5V/Div) CLKEN (5V/Div) VID0 (5V/Div) VID = 0.9375V, CLKEN Pull High to 3.3V VID change from 0.9375V to 0.85V Time (100μs/Div) Time (20μs/Div) CCM VID Change Up CPU-RFM VID Change Down VCC_SENSE (100mV/Div) VCC_SENSE (100mV/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (5V/Div) LGATE (5V/Div) VID0 (5V/Div) CLKEN Pull High to 3.3V VID change from 0.85V to 0.9375V Time (20μs/Div) DS8152E/F-04 April 2011 CLKEN Pull High to 3.3V VID0 (5V/Div) VID change from 0.9375V to 0.85V Time (20μs/Div) www.richtek.com 13 RT8152E/F CCM Load Transient Response VID = 0.9375V, ILOAD = 5A to 28A CLKEN Pull High to 3.3V (CPU) DPSLPVR = Low VCC_SENSE (50mV/Div) CCM Load Transient Response VID = 0.9375V, ILOAD = 28A to 5A DPSLPVR = High VCC_SENSE (50mV/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (5V/Div) LGATE (5V/Div) CLKEN Pull High to 3.3V (CPU) Time (10μs/Div) Time (10μs/Div) C4 ENTRY / EXIT with VID Change Over Current Protection VID = 0.9375V and 0.85V, CLKEN Pull High to 3.3V DPSLPVR = High VCC_SENSE (100mV/Div) I LOAD (40A/Div) VCC_SENSE (1V/Div) I LOAD (20A/Div) VID0 (5V/Div) DPRSLPVR (5V/Div) CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low PHASE (10V/Div) ILOAD-DPRSLPVR = 1A, ILOAD-CCM = 21A PWRGD (2V/Div) Time (40μs/Div) Time (10μs/Div) Over Voltage Protection Under Voltage Protection VCC_SENSE (1V/Div) VCC_SENSE (1V/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (10V/Div) LGATE (10V/Div) PWRGD (2V/Div) PWRGD (2V/Div) CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low Time (10μs/Div) www.richtek.com 14 CLKEN Pull High to 3.3V (CPU), DPSLPVR = Low Time (10μs/Div) DS8152E/F-04 April 2011 RT8152E/F Application Information The RT8152E/F is a single-phase PWM controller with embedded gate driver. It is compliant with Intel IMVP6.5 Voltage Regulator Specification to fulfill its mobile CPU and Render voltage regulator power supply requirement. Inductor current are continuously sensed for loop control, droop tuning, and over current protection. The 7-bit VID DAC and a low offset differential amplifier allow the controller to maintain high regulating accuracy to meet Intel IMVP6.5 specification. Design Tool To help users to reduce the efforts and errors caused by manual calculations using the design concept below, a user friendly design tool is now available on request. This design tool calculates all necessary design parameters by entering user's requirements. Please contact Richtek's representatives for details. Operation Modes Table 2 shows the RT8152E/F operation modes. When VRON is enable (=1), and within 10µs the RT8152E/F will detect the CLKEN to determine which operation mode is applied. If the CLKEN is low, the RT8152E/F will operate in Render core voltage regulator mode. If the CLKEN is high, the IC will operate in CPU core voltage regulator mode. DPRSLPVR determines the operation mode of the controller operation in CCM or RFM. The controller enters RFM (Ring Free Mode) when DPRSLPVR = 1 and enters CCM when DPRSLPVR = 0. Differential Remote Sense Connection The RT8152E/F includes differential, remote sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. CPU contains on-die sense pins VCC_SENSE and VSS_SENSE. Connect RGND to VSS_SENSE. Connect FB to VCC_SENSE with a resistor to build the negative input path of the error amplifier. Connect VSEN to VCC_SENSE for CLKEN, PGOOD, OVP, and UVP detection. The 7 bit VID DAC and the precision voltage reference are referred to RGND for accurate remote sensing. Current Sense Setting The RT8152E/F is continuously sensing the inductor current. Therefore, the controller can be less noise sensitive. Low offset amplifiers are used for loop control and over current detection. The internal current sense amplifier gain (AI) is fixed to be 10. The ISEN and ISEN_N denote the positive and negative input of the current sense amplifier. Users can either use a current sense resistor or the inductor's DCR for current sensing. Using inductor's DCR allows higher efficiency as shown in Figure 3. To let : L = R ×C (1) X X DCR then the transient performance will be optimum. For example, chose L = 0.36µH with 1mΩ DCR and CX = 100nF, yields for RX : RX = 0.36µH = 3.6kΩ 1mΩ × 100nF Table 2. Control signal truth table for operation modes of the RT8152E/F (2) V OUT L PHASE CLKEN DPRSLPVR 0 0 Render CCM (GND) 1 Render RFM 1 0 CPU CCM (Pull High) 1 CPU RFM DS8152E/F-04 April 2011 Operation Mode RX ISEN DCR CX + VX - ISEN_N Figure 3. Lossless Inductor Current Sensing www.richtek.com 15 RT8152E/F Considering the inductance tolerance, the resistor RX has to be tuned on board by examining the transient voltage. If the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, RX is chosen too small. Vice versa, with a resistance too large, the output voltage transient has only a small initial dip and the recovery is too fast causing a ring back. Using current sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade off. Considering the equivalent inductance (LESL) of the current sense resistor, a RC filter is recommended. The RC filter calculation method is similar to the above mentioned inductor DCR sensing method. The HS_FET on-time is determined by CCRCOT ON-Time generator. When load current increases, VCS increases, the steady state COMP voltage also increases and makes the VOUT decrease, achieving AVP. A near-DC offset cancellation is added to the output of EA to cancel the inherent output offset of finite-gain current mode controller. In RFM, HS_FET is turned on with constant TON when VCS is lower than VCOMP2. Once the HS_FET is turned off, LS_FET is turned on automatically. By Ringing-Free Technique, the LS_FET allows only partial of negative current when the inductor free-wheeling current reaches negative. The switching frequency will be proportionately reduced, thus the conduction and switching losses will be greatly reduced. Loop Control The RT8152E/F adopts Richtek's proprietary G-NAVPTM topology. G-NAVPTM is based on the finite-gain current mode with CCRCOT (Constant Current Ripple Constant On Time) topology. The output voltage, VOUT, will decrease with increasing output load current. The control loop consists of PWM modulator with power stage, current sense amplifier and error amplifier as shown in Figure 4. VIN RT8152E/F UGATE CCRCOT PWM Logic HS_FET RX LGATE VOUT L CX C LS_FET + COMP2 - CMP VCS Ai + - ISEN ISEN_N C2 COMP R1 VDAC It's very easy to achieve the Active Voltage Positioning (AVP) by properly setting the error amplifier gain due to the native droop characteristics. The target is to have : VOUT = VDAC − ILOAD x RDROOP , then solving the switching condition VCOMP2 = VCS in Figure 4 yields the desired error amplifier gain as : A × RSENSE A V = R2 = I R1 RDROOP (4) where AI is the internal current sense amplifier gain. RSENSE is the current sense resistor. If no external sense resistor present, it is the DCR of the inductor. RDROOP is the resistive slope value of the converter output and is the desired static output impedance. V OUT A V2 > A V1 SOFT RGND (3) VCC_SENSE FB + - Offset Cancellation EA + R2 C1 Output Voltage Droop Setting (with Temperature Compensation) CSOFT VSS_SENSE A V2 Figure 4. Simplified Schematic for Droop and Remote Sense in CCM A V1 0 Load Current Figure 5. Error Amplifier Gain (AV) Influence on VOUT www.richtek.com 16 DS8152E/F-04 April 2011 RT8152E/F Since the DCR of inductor is highly temperature dependent, it affects the output accuracy at hot conditions. Temperature compensation is recommended for the lossless inductor DCR current sense method. Figure 6 shows a simple but effective way of compensating the temperature variations of the sense resistor using an NTC thermistor placed in the feedback path. C2 RT8152E/F COMP + - EA + VDAC R2 C1 FB SOFT RGND R1a R1b VCC_SENSE NTC CSOFT 10nF VSS_SENSE Figure 6. Loop Setting with Temperature Compensation Usually, R1a is set to equal RNTC (25°C). R1b is selected to linearize the NTC's temperature characteristic. For a given NTC, design is to get R1b and R2 and then C1 and C2. According to (4), to compensate the temperature variations of the sense resistor, the error amplifier gain (Av) should have the same temperature coefficient with RSENSE. Hence : A V, HOT R SENSE, HOT = A V, COLD RSENSE, COLD (5) From (4), we can have Av at any temperature (T) as A V, T = R2 R1a // RNTC, T + R1b (6) The standard formula for the resistance of NTC thermistor as a function of temperature is given by : {( RNTC, T = RNTC, 25 e ) ( )} 1 β − 1 298 T+273 (7) Where RNTC, 25 is the thermistor's nominal resistance at room temperature, β (beta) is the thermistor's material constant in Kelvins, and T is the thermistor's actual temperature in Celsius. To calculate DCR value at different temperature can use equation as below : DCRT = DCR25 x [1 + 0.00393 x (T − 25)] (8) Where the 0.00393 is the temperature coefficient of the copper. For a given NTC thermistor, solving (6) at room temperature (25°C) yields : DS8152E/F-04 April 2011 R2 = AV, 25 x (R1b + R1a // RNTC, 25) (9) Where AV, 25 is the error amplifier gain at room temperature and can be obtained from (4). R1b can be obtained by substituting (9) to (5), R1b = RSENSE, HOT × (R1a // RNTC, HOT ) − (R1a // RNTC, COLD ) RSENSE, COLD RSENSE, HOT 1 − R (10) SENSE, COLD Loop Compensation Optimized compensation of the RT8152E/F allows for best possible load step response of the regulator's output. A compensator with one pole and one zero is adequate for a proper compensation. Figure 4 shows the compensation circuit. Prior design procedure shows how to decide the resistive feedback components of error amplifier gain, the C1 and C2 must be calculated for the compensation. The target is to achieve the constant resistive output impedance over the widest possible frequency range. The pole frequency of the compensator must be set to compensate the output capacitor ESR zero : fP = 1 2 × π × C × RC (11) Where C is the capacitance of output capacitor, and RC is the ESR of output capacitor. C2 can be calculated as follows : C2 = C × RC R2 (12) The zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. Such that : 1 C1 = (13) (R1b + R1a // RNTC, 25 ) × π × fSW TON Setting High frequency operation optimizes the application for the smaller component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low frequency operation offers the best overall efficiency at the expense of component size and board space.Figure 5 www.richtek.com 17 RT8152E/F shows the On-Time setting circuit. Connect a resistor (RTON) between VIN and TON to set the on-time of UGATE : −12 14.5 × 10 × RTON × 2 TON = (VIN − VDAC) (14) Where TON is UGATE turn on period, VIN is Input voltage of converter, VDAC is DAC voltage. On-time translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in external HS-FET. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only in CCM (DPRSLPVR = 0), and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the PHASE goes high earlier than normal, extending the on-time by a period equal to the HS-FET rising dead time. For better efficiency of the given load range, the maximum switching frequency is suggested to be : 1 (15) FS(MAX) = × TON − THS-Delay VDAC(MAX) + ILOAD(MAX) × RON_ LS-FET + DCRL − RDROOP VIN(MAX) + ILOAD(MAX) × RON_ LS-FET − RON_ HS-FET Where } FsMAX is the maximum switching frequency } THS- Delay is the turn on delay of HS-FET } VDAC(MAX) is the maximum VDAC of application } VINMAX is the maximum application Input voltage } ILOAD(MAX) is the maximum load of application } RON_LS-FET is the Low side FET RDS(ON) } RON_HS-FET is the High side FET RDS(ON) } DCRL is the inductor DCR } RDROOP is the load line setting CCRCOT On-Time Generator TON VDAC R TON The RT8152E/F uses 3 slew rates for various modes of operation. The three slew rates are internally determined by commanding one of three bi-directional current sources (ISS) on to the SOFT pin. The 7 bit VID DAC and the precision voltage reference are referred to RGND for accurate remote sensing. Hence, connect a capacitor (CSOFT ) from SOFT pin to RGND for controlling the slew rate as shown in Figure 6. The capacitance of capacitor is restricted to be larger than 10nF. The voltage (VSOFT ) on the SOFT pin is the reference voltage of the error amplifier and is, therefore, the commanded system voltage. The first current is typically 20µA used to charge or discharge the CSOFT during soft-start, and soft-shutdown. The second current is typically 50µA used during other voltage transitions, including VID change and transitions between operation modes. The third current is typically 100µA used during Render RFM with VID change up transitions. The IMVP-6.5 specification specifies the critical timing associated with regulating the output voltage. The symbol, SLEWRATE, as given in the IMVP-6.5 specification will determine the choice of the SOFT capacitor, CSOFT, by the following equation : ISS CSOFT = (16) SLEWRATE Power up Sequence With the controller's VCC voltage rises above the POR threshold (typ. 4.3V), the power up sequence begins when VRON goes high. If CLKEN = 1 (Pull High), the RT8152E/F will enter CPU mode power up sequence. If the CLKEN = 0 (Connect to GND), the controller will enter Render mode power up sequence. After the RT8152E/F enters CPU mode, VSEN starts ramping up to VBOOT within 1ms. The slew rate during R1 power up is 20µA/CSOFT . The RT8152E/F pulls CLKEN low after VSEN gets across VBOOT − 0.1V for 73µs. Right V IN C1 On-Time Figure 7. On-Time setting with RC Filter www.richtek.com 18 Soft-Start and Mode Transition Slew Rates after CLKEN goes low, VSEN starts ramping to first VDAC value. After CLKEN goes low for approximately 4.7ms, PGOOD is asserted HIGH. DPRSLPVR are valid right after PGOOD is asserted. UVP is masked as long as VSEN is less than VBOOT − 0.1V. DS8152E/F-04 April 2011 RT8152E/F VCC 4.3V 4.1V POR VRON VID XX Valid VBOOT - 0.1V xx VBOOT VSEN PWM 0.2V Hi-Z CCM DPRSLPVR DPRSLPVR Defined CCM Pull Down Valid XX XX CLKEN PGOOD 73µs typ. 4.7ms typ. Figure 8. CPU Mode Timing Diagram for Power Up and Power Down After the RT8152E/F enters Render mode, VSEN starts ramping up to VDAC within 1ms. The slew rate during power up is 20µA/CSOFT . PGOOD is asserted HIGH after VSEN exceeds VDAC − 100mV for 4.77ms (typ.). DPRSLPVR are valid right after PGOOD is asserted. UVP is masked as long as VSEN is less than VDAC − 100mV. VCC 4.3V 4.1V POR VRON VID XX xx Valid VDAC-100mV VDAC VSEN PWM 0.2V Hi-Z DPRSLPVR CCM XX DPRSLPVR Defined CCM Pull Down Valid XX PGOOD 4.77ms typ. Figure 9. Render Mode Timing Diagram for Power Up and Power Down DS8152E/F-04 April 2011 www.richtek.com 19 RT8152E/F Power Down When VRON goes low, the RT8152E/F enters low power shutdown mode. PGOOD is pulled low immediately and the VSOFT ramps down with slew rate of 20µA/CSOFT. VSEN also ramps down following VSOFT . After VVSEN is lower than 200mV, the RT8152E/F turns off high side FETs and low side FETs. An internal discharge resistor at VSEN will be enabled and the analog part will be turned off. Deeper Sleep Mode Transitions If the current limit function is triggered for 15 switching cycles, OCP will be tripped. Once OCP is tripped, both high side and low side MOSFET will be turn off, and the internal discharge resistor at the VSEN pin will be enabled to discharge output capacitors. OCP is a latched protection, it can only be reset by cycling VRON or VCC. If inductor DCR is used as current sense component, then temperature compensation is recommended for proper protection under all conditions. Figure 11 shows a typical OCP setting with temperature compensation. After DPRSLPVR goes high, the RT8152E/F enters deeper sleep mode operation. If the VIDs are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. The internal target VSOFT still ramps as before, and UVP, OCP and OVP are masked for 73µs. VCC R OC1a NTC R OC1b OCSET ROC2 Over Current Protection Setting The RT8152E/F compares a programmable current limit set point to the voltage from the current sense amplifier output for Over Current Protection (OCP). The voltage applied to OCSET pin defines the desired current limit threshold ILIM : VOCSET = 40 x ILIM x RSENSE (17) Connect a resistor voltage divider from VCC to GND, the joint of the resistor divider is connected to OCSET pin as shown in Figure 10. For a given ROC2, then VCC ROC1 = ROC2 × − 1 VOCSET (18) V CC Figure 11. OCP Setting with Temperature Compensation Generally, the ROC1a must be selected to be equal to thermistor's nominal resistance at room temperature. Ideally, VOCSET has same temperature coefficient with RSENSE (Inductor DCR) : VOCSET, HOT RSENSE, HOT = VOCSET, COLD RSENSE, COLD ROC2 = α × REQU, HOT − REQU, COLD + (1 − α ) × REQU, 25 VCC × (1 − α ) VOCSET, 25 R OC1 ROC1b = R OC2 (α − 1) × ROC2 + α × REQU, HOT − REQU, COLD (1 − α ) OCSET (19) (20) (21) Where Figure 10. OCP Setting Without Temperature Compensation RT8152E/F provides current limit function and over current protection. The current limit function is triggered when inductor current exceeds the current limit threshold ILIM defined by VOCSET . When current limit function is tripped, high side MOSFET will be forced off until the over current condition is cleared. www.richtek.com 20 α= RSENSE, HOT DCR 25 × [1 + 0.00393 × (THOT − 25)] = R SENSE, COLD DCR 25 × [1 + 0.00393 × (TCOLD − 25)] (22) REQU, T = R1a // RNTC, T (23) DS8152E/F-04 April 2011 RT8152E/F For example, the following design parameters are given : Over Temperature Protection (OTP) DCR = 1mΩ, VCC = 5V, IL,ripple = 9A Over Temperature Protection prevents the VR from damaging. OTP is considered to be the final protection stage against overheating of the VR. The thermal throttling VRTT shall be set to be asserted prior to OTP to manage the VR power. When this measure was insufficient to keep the die temperature of the controller below the OTP threshold, OTP will be asserted and latches. The die temperature of the controller is monitored internally by a temperature sensor. As a result of OTP triggering, a soft shutdown will be launched and VVSEN will be monitored. When VVSEN is less than 200mV, the driver remains in high impedance state and the discharging resistor at VSEN pin will be enabled. A reset can be executed by cycling VCC or VRON. ROC1a = RNTC, 25 = 10kΩ, βNTC = 3450 For −20°C to 100°C operation range, to set OCP trip current ITRIP = 28A ILIM = 28A + 9A = 32.5A 2 VOCSET, 25 = 40 × 33A × 1mΩ = 1.297V RNTC, −20°C = 78.4kΩ, RNTC,100°C = 0.98kΩ RSENSE, −20°C = 0.82mΩ, RSENSE,100°C = 1.29mΩ ⇒ ROC2 = 4.7kΩ, ROC1b = 8.46kΩ Over Voltage Protection (OVP) The OVP circuit is triggered under two conditions: } Condition 1 : When VVSEN exceeds 1.52V. Thermal Throttling Control } Condition 2 : When VVSEN exceeds VDAC by 300mV (typ.). Intel IMVP-6.5 technology supports thermal throttling of the processor to prevent catastrophic thermal damage. The RT8152E/F includes a thermal monitoring circuit to detect an exceeded user defined temperature on a VR point. The thermal monitoring circuit senses the voltage change across NTC pin. Figure 12 shows the principle of setting the temperature threshold. Connect an external resistor divider between Vcc and GND. This divider uses a Negative Temperature Coefficient (NTC) thermistor and a resistor. The joint of the resistor divider is connected to the NTC pin in order to generate a voltage that is inversely proportional to temperature. The RT8152E/F pulls VRTT If either condition is valid, the RT8152E/F latches the LGATE = 1 and UGATE = 0 as crowbar to the output voltage of VR. Turn on all LS_FETs can lead to very large reverse inductor current and potentially result in negative output voltage of VR. To prevent the CPU from damaging by negative voltage. The RT8152E/F turns off all LS_FETs when VVSEN falls below −100mV. Under Voltage Protection (UVP) If VVSEN is lower than VDAC by 400mV (typ.) a UVP fault will be tripped. Once UVP is tripped, both high side and low side MOSFET will be turned off, and the internal discharge resistor at VSEN pin will be enabled. UVP is a latched protection, it can only be reset by cycling VRON or VCC. low if the voltage on the NTC pin is greater than 0.8 x VCC. The internal VRTT comparator has a hysteresis of 200mV (typ.) to prevent high frequency VRTT oscillation when the temperature is near the setting point. The minimum assertion/de-assertion time for VRTT toggling is 1.6ms (typ.). Negative Voltage Protection (NVP) During the state that VVSEN is lower than −100mV, the controller will force LGATE = 0 and UGATE = 0 for preventing negative voltage. Once VVSEN recovers to be higher than 0V, NVP will be suspended and LGATE = 1 will be enabled again. V CC VRTT CMP NTC NTC + - R TT + 0.8 x V CC Figure 12. Thermal Throttling Setting Principle DS8152E/F-04 April 2011 www.richtek.com 21 RT8152E/F Users can use the same NTC thermistor for both thermalthrottling and current limit setting as shown in Figure 13. Just divide the ROC1b into RTTa and RTTb, and write the VNTC equation at thermal throttling temperature TT°C : RTTa + RTTb = ROC1b ROC2 (24) ROC2 + RTTb × VCC = 0.8 × VCC + ROC1b + ROC1a // RNTC, TT (25) Solving (27) and (28) for RTTa and RTTb as : (26) RTTa = ROC1b − RTTb (27) V CC VRTT CMP There is a example for current monitor, the following design parameters are given : I(MAX) = 30A, RDROOP = 3mΩ, VCM(MAX) = 1V, RCMSET = 10kΩ RTTb = 4 x (ROC1a // RNTC, TT ) − ROC2 ROC1a The VCM(MAX) must be kept equal to 1V, I(MAX) is needed to follow the setting current of the IMVP6.5 definition with various CPU. The RDROOP is the load line setting of applications. The VCM(MAX) is clamped not higher than 1.15V. ⇒ RCM = 55.6kΩ Current Monitor Generator NTC - V CC_SENSE RCMSET CMSET CM V CM R CM R TTa C1 RGND NTC + VSEN R TTb + 0.8 x V CC Figure 14. Current Monitor Setting Principle OCSET R OC2 Inductor Selection Figure 13. Using Single NTC Thermistor for Thermal Throttling and Current Limit Setting Current Monitor Figure 14 shows the current monitor setting principle. Current monitor needs to meet IMVP6.5 specification, the RT8152E/F is based on the relation between RDROOP and load current to provide an easily setting and high accuracy current monitor indicator. The current monitor indication voltage VCM equation is shown as : VCM = 2 × ILOAD × RDROOP × RCM RCMSET (28) The switching frequency and ripple current determine the inductor value as follows : L(MIN) = VIN − VOUT × TON IRipple −MAX (30) where TON is the UGATE turn on period. Higher inductance yields in less ripple current and hence in higher efficiency. The flaw is the slower transient response of the power stage to load transients. This might increase the need for more output capacitors driving the cost up. Find a low loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. The core must be large enough not to be saturated at the peak inductor current. Where ILOAD is the output load current, RDROOP is the load line setting of applications, RCM and RCMSET is the current monitor current setting resistor. Output Capacitor Selection To find RCM and RCMSET base on : itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output VCM(MAX) RCM = R CMSET 2 × I(MAX) × RDROOP www.richtek.com 22 (29) Output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter capacitors can be found including, bulk capacitors closely located to the inductors and ceramic output capacitors in DS8152E/F-04 April 2011 RT8152E/F Maximum Power Dissipation (W) close proximity to the load. Latter ones are for midfrequency decoupling with especially small ESR and ESL values while the bulk capacitors have to provide enough stored energy to overcome the low frequency bandwidth gap between the regulator and the CPU. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Four Layers PCB 0 25 50 75 100 125 Ambient Temperature (°C) Figure 15. Derating Curve for RT8152E/F Package PD(MAX) = (TJ(MAX) − TA) / θJA Where T J(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8152E/F, The maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-32L 5x5 package, the thermal resistance θJA is 36°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (12°C − 25°C) / (36°C/W) = 2.778W for WQFN-32L 5x5 package Layout Considerations Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for optimum PC board layout : } Keep the high current paths short, especially at the ground terminals. } Keep the power traces and load connections short. This is essential for high efficiency. } The slew rate control capacitor should be connected from SOFT to RGND, and it should be placed physically close to IC. The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT8152E/F package, the Figure 15 of derating curve allows the designer to see the effect of Connect slew rate control capacitor at SOFT pin to RGND. } When trade offs in trace lengths must be made, it preferable to allow the inductor charging path to be made longer than the discharging path. } Place the current sense component close to the controller. ISEN and ISEN_N connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense accuracy. The PCB trace from the sense nodes should be parallel back to controller. } Route high speed switching nodes away from sensitive analog areas (SOFT, COMP, FB, VSEN, ISEN, ISEN_N, CM, etc...) rising ambient temperature on the maximum power allowed. DS8152E/F-04 April 2011 www.richtek.com 23 RT8152E/F Outline Dimension D D2 SEE DETAIL A L 1 E E2 e b 1 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 2 A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 4.950 5.050 0.195 0.199 D2 3.400 3.750 0.134 0.148 E 4.950 5.050 0.195 0.199 E2 3.400 3.750 0.134 0.148 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 32L QFN 5x5 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 24 DS8152E/F-04 April 2011