RT7275/76

®
RT7275/76
3A, 18V, 700kHz ACOTTM Synchronous Step-Down Converter
General Description
Features
The RT7275/76 are high-performance 700kHz 3A stepdown regulators with internal power switches and
synchronous rectifiers. They feature quick transient
response using their Advanced Constant On-Time
(ACOT TM) control architecture that provides stable

Fast Transient Response

operation with small ceramic output capacitors and without
complicated external compensation, among other benefits.
The input voltage range is from 4.5V to 18V and the output
is adjustable from 0.765V to 8V.

The proprietary ACOTTM control improves upon other fastresponse constant on-time architectures, achieving nearly
constant switching frequency over line, load, and output
voltage ranges. Since there is no internal clock, response
to transients is nearly instantaneous and inductor current
can ramp quickly to maintain output regulation without
large bulk output capacitance. The RT7275/76 are stable
with and optimized for ceramic output capacitors.

Steady 700kHz Switching Frequency
 At all Load Currents (RT7275)
 Discontinuous Operating Mode at Light Load
(RT7276)
3A Output Current
Advanced Constant On-Time (ACOTTM) Control
Optimized for Ceramic Output Capacitors
4.5V to 18V Input Voltage Range
Internal 90mΩ
Ω Switch and 60mΩ
Ω Synchronous
Rectifier
0.765V to 8V Adjustable Output Voltage








With internal 90mΩ switches and 60mΩ synchronous
rectifiers, the RT7275/76 display excellent efficiency and
good behavior across a range of applications, especially
for low output voltages and low duty cycles. Cycle-bycycle current limit, input under-voltage lock-out,
externally-adjustable soft-start, output under- and overvoltage protection, and thermal shutdown provide safe and
smooth operation in all operating conditions.
The RT7275 and RT7276 are each available in WDFN-10L
3x3 and PTSSOP-14 packages, with exposed thermal
pads.
Externally-adjustable, Pre-biased Compatible SoftStart
Cycle-by-Cycle Current Limit
Optional Output Discharge Function (PTSSOP-14
Only)
Output Over- and Under-voltage Shut-down
Applications






Industrial and Commercial Low Power Systems
Computer Peripherals
LCD Monitors and TVs
Green Electronics/Appliances
Point of Load Regulation for High-Performance DSPs,
FPGAs, and ASICs
Not Recommended for Sink/Source Applications
Fast-Transient Response
RT7275
Simplified Application Circuit
VIN
Input Signal
Power Good
RT7275/76
VIN
SW
VINR
EN
VOUT
(20mV/Div)
VOUT
BOOT
FB
PGOOD
VOUT
PVCC
SS
PGND GND
IOUT
(2A/Div)
VIN = 12V, VOUT = 1.05V, IOUT = 0 to 3A
Time (100μs/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT7275/76
Ordering Information
Pin Configurations
(TOP VIEW)
RT7275/76
Operating Mode
75 : Continuous Switching Mode
76 : Discontinuous Operating Mode
at Light Load
3
4
12
PGND
5
11
10
6
9
15
7
EN
FB
PVCC
SS
PGOOD
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

13
8
TSSOP-14 (Exposed Pad)
Note :

VINR
VIN
BOOT
SW
SW
PGND
PGND
14
2
1
2
3
4
5
PGND
Lead Plating System
G : Green (Halogen Free and Pb Free)
VOUT
FB
PVCC
SS
GND
PGOOD
EN
11
10
9
8
7
9
Package Type
CP : TSSOP-14 (Exposed Pad)
QW : WDFN-10L 3x3 (W-Type)
VIN
VIN
BOOT
SW
SW
WDFN-10L 3x3
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT7276GCP
RT7275GCP
RT7275GCP : Product Number
RT7275
GCPYMDNN
YMDNN : Date Code
RT7276GCP : Product Number
RT7276
GCPYMDNN
RT7276GQW
RT7275GQW
2C= : Product Code
4C= : Product Code
4C=YM
DNN
YMDNN : Date Code
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
2
YMDNN : Date Code
2C=YM
DNN
YMDNN : Date Code
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Absolute Maximum Ratings













(Note 1)
Supply Input Voltage, VIN, VINR (TSSOP-14 (Exposed Pad)) ----------------------------------------- −0.3V to 21V
Switch Node, SW ------------------------------------------------------------------------------------------------- −0.8V to (VVIN + 0.3V)
Switch Node, SW (<10ns) --------------------------------------------------------------------------------------- −5V to 25V
BOOT to SW ------------------------------------------------------------------------------------------------------- −0.3V to 6V
PVCC ---------------------------------------------------------------------------------------------------------------- −0.3V to 6V
PVCC to VIN (WDFN-10L 3x3) or VINR (TSSOP-14 (Exposed Pad)) --------------------------------- −18V to 0.3V
Other Pins ----------------------------------------------------------------------------------------------------------- −0.3V to 21V
Power Dissipation, PD @ TA = 25°C
TSSOP-14 (Exposed Pad) -------------------------------------------------------------------------------------- 2.50W
WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------- 1.67W
Package Thermal Resistance (Note 2)
TSSOP-14 (Exposed Pad), θJA -------------------------------------------------------------------------------- 40°C/W
WDFN-10L 3x3, θJA ----------------------------------------------------------------------------------------------- 60°C/W
WDFN-10L 3x3, θJC ----------------------------------------------------------------------------------------------- 7.5°C/W
Junction Temperature Range ------------------------------------------------------------------------------------ 150°C
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) -------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions



(Note 4)
Supply Input Voltage, VIN --------------------------------------------------------------------------------------- 4.5V to 18V
Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Current
Supply Current (Shutdown)
VEN = 0V
--
1
10
A
Supply Current (Quiescent)
VEN = 3V, VFB = 1V
--
0.7
--
mA
Logic Threshold
EN Voltage
Logic High
VIH
2
--
--
Logic Low
VIL
--
--
0.4
V
VFB Voltage and Discharge Resistance
Feedback Threshold Voltage
VFB_TH
4.5V  VIN  18V
0.757
Feedback Input Current
IFB
VFB = 0.8V
0.1
0
0.1
A
VOUT Discharge Resistance
R DIS
VEN = 0V, VVOUT = 0.5V
--
50
100

VPVCC
6V  VIN  18V, 0 < IPVCC  5mA
4.7
5.1
5.5
V
--
--
20
mV
0.765 0.773
V
PVCC Output
PVCC Output Voltage
PVCC Line Regulation
6V  VIN  18V, IPVCC = 5mA
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT7275/76
Parameter
Symbol
Min
Typ
Max
Unit
0  IPVCC  50mA
--
--
40
mV
IPVCC
VIN = 6V, VPVCC = 4V
--
110
--
mA
High Side
RDS(ON) _H
For WDFN-10L 3x3
--
90
--
High Side
RDS(ON) _H
For TSSOP-14 (Exposed Pad)
--
100
--
Low Side
RDS(ON) _L
--
60
--
3.5
4.5
5.7
A
--
150
--
C
--
20
--
C
--
145
--
ns
PVCC Load Regulation
Output Current
Test Conditions
On-Resistance (R DS(ON))
Switch On
Resistance
Current Limit (upper threshold) ILIM
LSW = 1.4H
m
Thermal Shutdown
Thermal Shutdown Threshold
TSD
Thermal Shutdown Hysteresis TSD
On-Time and Off-Time Control
On-Time
tON
VIN = 12V, VOUT = 1.05V
Minimum On-Time
tON(MIN)
--
60
--
ns
Minimum Off-Time
tOFF(MIN)
--
230
--
ns
Soft-Start
SS Charge Current
VSS = 0V
1.4
2
2.6
A
SS Discharge Current
VSS = 0.5V
0.05
0.1
--
mA
VVIN / VVINR Rising, Enable PVCC
Regulator
3.55
3.85
4.15
Threshold Hysteresis
--
0.3
--
VFB Rising
85
90
95
VFB Falling
--
85
--
PGOOD = 0.5V
--
5
--
mA
115
120
125
%
--
5
--
s
VFB Falling
65
70
75
Hysteresis
--
10
--
--
250
--
VIN UVLO
UVLO Threshold
V
Power Good
PGOOD Threshold
PGOOD Sink Current
%
Output Under Voltage and Over Voltage Protection
OVP Trip Threshold
VFB Rising
OVP Delay Time
UVP Trip Threshold
UVP Delay Time
%
s
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package. The PCB copper area of exposed pad is 70mm2.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
4
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Typical Operating Characteristics
Efficiency vs. Load Current
Efficiency vs. Load Current
100
RT7275
90
90
80
80
70
VOUT = 5V
VOUT = 2.5V
VOUT = 1.05V
60
50
40
30
RT7276
VOUT = 5V
VOUT = 2.5V
VOUT = 1.05V
70
Efficiency (%)
Efficiency (%)
100
60
50
40
30
20
20
10
10
VIN = 12V
0
0.001
0.01
0.1
1
VIN = 12V
0
0.001
10
0.01
Load Current (A)
1
10
Output Voltage vs. Load Current
Output Voltage vs. Load Current
1.048
0.1
Load Current (A)
1.09
RT7275
RT7276
1.08
VIN = 17V
VIN = 12V
Output Voltage (V)
Output Voltage (V)
1.046
1.044
1.042
VIN = 5V
1.040
VIN = 17V
VIN = 12V
1.07
1.06
1.05
VIN = 5V
1.04
1.03
1.02
VOUT = 1.05V
VOUT = 1.05V
1.01
1.038
0
0.5
1
1.5
2
2.5
0
3
0.5
RT7275
Switching Frequency (kHz)1
Switching Frequency (kHz) 1
900
750
1.5
2
2.5
3
Switching Frequency vs. Output Current
Switching Frequency vs. Load Current
800
1
Load Current (A)
Load Current (A)
VIN = 17V
VIN = 12V
VIN = 5V
700
650
VOUT = 1.05V
RT7276
800
700
600
VIN = 5V
VIN = 12V
VIN = 17V
500
400
300
200
100
VOUT = 1.05V
0
600
0
0.5
1
1.5
2
2.5
Output Current (A)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
3
0
0.5
1
1.5
2
2.5
3
Output Current (A)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT7275/76
Feedback Voltage vs. Temperature
Feedback Voltage vs. Input Voltage
0.770
Feedback Voltage (V)
Feedback Voltage (V)
0.770
0.765
VIN = 17V
VIN = 12V
VIN = 5V
0.760
0.755
0.765
0.760
0.755
IOUT = 0.1A
VOUT = 1.05V, IOUT = 0A
0.750
0.750
-50
-25
0
25
50
75
100
125
4
6
8
Temperature (°C)
10
12
14
16
18
Input Voltage (V)
EN Current vs. EN Voltage
Shutdown Current vs. Temperature
4
4.0
Shutdown Current (µA)1
EN Current (µA)
3.5
3
2
1
3.0
VIN = 17V
VIN = 12V
VIN = 5V
2.5
2.0
1.5
1.0
0.5
VOUT = 1.05V
VIN = 12V, VOUT = 1.05V
0
0.0
0
2
4
6
8
10
12
14
16
18
-50
-25
0.90
RT7275
50
75
100
125
RT7276
0.85
Quiescent Current (mA)
0.85
Quiescent Current (mA)
25
Quiescent Current vs. Temperature
Quiescent Current vs. Temperature
0.90
0
Temperature (°C)
EN Voltage (V)
VIN = 17V
VIN = 12V
0.80
0.75
0.70
VIN = 5V
0.65
0.60
VIN = 17V
VIN = 12V
0.80
0.75
0.70
VIN = 5V
0.65
0.60
0.55
0.55
VOUT = 1.05V
0.50
-50
-25
0
25
50
75
100
Temperature (°C)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
6
125
VOUT = 1.05V
0.50
-50
-25
0
25
50
75
100
125
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Maximum Output Current vs. Temperature
Current Limit Thresholds vs. Input Voltage
5.5
5.0
Upper Threshold
4.5
4.0
Lower Threshold
3.5
VOUT = 0V
Maximum Output Current (A)1
Current Limit Thresholds (A)
5.5
3.0
5.1
4.7
VIN = 17V
VIN = 12V
4.3
VIN = 5V
3.9
VOUT = 0V
3.5
5
7
9
11
13
15
17
-50
-25
0
50
75
100
125
Temperature (°C)
Input Voltage (V)
PVCC Output Voltage vs. Input Voltage
PVCC Output Voltage vs. Output Current
5.20
PVCC Output Voltage (V)
5.20
PVCC Output Voltage (V)
25
No Load
5.15
5mA Load
5.10
5.05
5.15
5.10
5.05
VIN = 12V, IOUT = 5mA
5.00
VIN = 12V
5.00
5
7
9
11
13
15
17
0
20
40
60
80
Input Voltage (V)
PVCC Output Current (mA)
Load Transient Response
Load Transient Response
RT7275
100
RT7275/RT7276
VOUT
(20mV/Div)
VOUT
(20mV/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 1.05V, IOUT = 0 to 3A
Time (100μs/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
VIN = 12V, VOUT = 1.05V, IOUT = 1A to 3A
Time (100μs/Div)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT7275/76
Output Ripple Voltage
Power On from VIN
VIN
(20V/Div)
VSW
(10V/Div)
VOUT
(1V/Div)
VSW
(10V/Div)
VOUT
(10mV/Div)
VIN = 12V, VOUT = 1.05V, IOUT = 3A
IOUT
(2A/Div)
VIN = 12V, VOUT = 1.05V, IOUT = 3A
Time (400ns/Div)
Time (4ms/Div)
Power Off from VIN
Power On from EN
VIN
(20V/Div)
VEN
(10V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
VSW
(10V/Div)
VSW
(10V/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 1.05V, IOUT = 3A
VIN = 12V, VOUT = 1.05V, IOUT = 3A
Time (4ms/Div)
Time (4ms/Div)
Power Off from EN
VEN
(10V/Div)
VOUT
(1V/Div)
VSW
(10V/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 1.05V, IOUT = 3A
Time (100μs/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
8
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Functional Pin Description
Pin No.
TSSOP-14
(Exposed Pad)
Pin Name
Pin Function
WDFN-10L 3x3
1
--
2
2
VOUT
Optional Output Voltage Discharge Connection. This open drain
output connects to ground when the device is disabled. If output
voltage discharge is desired, connect VOUT to the output
voltage.
FB
Feedback Input Voltage. Connect FB to the midpoint of the
external feedback resistive divider to sense the output voltage.
Place the resistive divider within 5mm from the FB pin. The IC
regulates VFB at 0.765V (typical).
3
3
PVCC
Linear Regulator Output. PVCC is the output of the internal
5.1V linear regulator powered by VIN (WDFN-10L 3x3) or VINR
(TSSOP-14 (Exposed Pad)). Connect a 1F ceramic capacitor
from PVCC to ground.
4
4
SS
Soft-Start Control. Connect an external capacitor between this
pin and ground to set the soft-start time.
5
--
GND
Analog Ground.
6
5
PGOOD
Open Drain Power-good Output. PGOOD connects to PGND
whenever VFB is less than 90% of its regulation threshold
(typical).
7
1
EN
Enable Control Input. Connect EN to a logic-high voltage to
enable the IC or to a logic-low voltage to disable. Do not leave
this high impedance input unconnected.
8, 9, 15
(Exposed pad)
11 (Exposed pad) PGND
10, 11
6, 7
12
8
13
14
9, 10
--
SW
Switching Node. SW is the Source of the internal N-channel
MOSFET switch and the Drain of the internal N-channel
MOSFET synchronous rectifier. Connect SW to the inductor
with a wide short PCB trace and minimize its area to reduce
EMI.
BOOT
Bootstrap Supply for High Side Gate Driver. Connect a 0.1F
capacitor between BOOT and SW to power the internal gate
driver.
VIN
Power Input. VIN is the Drain of the internal N-channel
MOSFET switch. Connect VIN to the input capacitor. For the
WDFN-10L 3x3 package, VIN also supplies power to the
internal linear regulator.
VINR
Internal Linear Regulator Supply Input. For the TSSOP-14
(Exposed Pad) package, VINR supplies power for the internal
linear regulator that powers the IC. Connect VIN to the input
voltage and bypass to ground with a 0.1F ceramic capacitor.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
Power Ground. PGND connects to the Source of the internal
N-channel MOSFET synchronous rectifier and to other power
ground nodes of the IC. The exposed pad and the 2 PGND pins
(TSSOP-14 (Exposed Pad)) should be well soldered to the
input and output capacitors and to a large PCB area for good
power dissipation.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT7275/76
Functional Block Diagram
VINR
TSSOP-14
(Exposed Pad)
BOOT
PVCC
VIN
(WDFN-10L 3x3)
Internal Regulator
VOUT
TSSOP-14
(Exposed Pad)
VREF
VBIAS
UGATE
Under & Over
Voltage
Discharge
Protection
PVCC
2µA
VIN
Switch
Controller
LGATE
0.9 VREF
+
FB
- -
On-Time
PGND
SW
Ripple
Gen.
SS
FB
SW
Driver
FB
Comparator
PGOOD
+
-
GND
TSSOP-14
(Exposed Pad)
Over Current
Protection PVCC
PGOOD
Comparator
EN
EN
Detailed Description
The RT7275/76 are high-performance 700kHz 3A stepdown regulators with internal power switches and
synchronous rectifiers. They feature an Advanced Constant
On-Time (ACOTTM) control architecture that provides
stable operation with ceramic output capacitors without
complicated external compensation, among other benefits.
The input voltage range is from 4.5V to 18V and the output
is adjustable from 0.765V to 8V.
The proprietary ACOTTM control scheme improves upon
other constant on-time architectures, achieving nearly
constant switching frequency over line, load, and output
voltage ranges. The RT7275/76 are optimized for ceramic
output capacitors. Since there is no internal clock,
response to transients is nearly instantaneous and inductor
current can ramp quickly to maintain output regulation
without large bulk output capacitance.
Constant On-Time (COT) Control
The heart of any COT architecture is the on-time oneshot. Each on-time is a pre-determined “fixed” period
that is triggered by a feedback comparator. This robust
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
10
arrangement has high noise immunity and is ideal for low
duty cycle applications. After the on-time one-shot period,
there is a minimum off-time period before any further
regulation decisions can be considered. This arrangement
avoids the need to make any decisions during the noisy
time periods just after switching events, when the
switching node (SW) rises or falls. Because there is no
fixed clock, the high-side switch can turn on almost
immediately after load transients and further switching
pulses can ramp the inductor current higher to meet load
requirements with minimal delays.
Traditional current mode or voltage mode control schemes
typically must monitor the feedback voltage, current
signals (also for current limit), and internal ramps and
compensation signals, to determine when to turn off the
high-side switch and turn on the synchronous rectifier.
Weighing these small signals in a switching environment
is difficult to do just after switching large currents, making
those architectures problematic at low duty cycles and in
less than ideal board layouts.
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Because no switching decisions are made during noisy
time periods, COT architectures are preferable in low duty
cycle and noisy applications. However, traditional COT
control schemes suffer from some disadvantages that
preclude their use in many cases. Many applications require
a known switching frequency range to avoid interference
with other sensitive circuitry. True constant on-time control,
where the on-time is actually fixed, exhibits variable
switching frequency. In a step-down converter, the duty
factor is proportional to the output voltage and inversely
proportional to the input voltage. Therefore, if the on-time
is fixed, the off-time (and therefore the frequency) must
change in response to changes in input or output voltage.
changes, the switch voltage drops change causing a
switching frequency variation with load current. Also, at
light loads if the inductor current goes negative, the switch
dead-time between the synchronous rectifier turn-off and
the high-side switch turn-on allows the switching node to
rise to the input voltage. This increases the effective ontime and causes the switching frequency to drop
noticeably.
Modern pseudo-fixed frequency COT architectures greatly
improve COT by making the one-shot on-time proportional
to VOUT and inversely proportional to VIN. In this way, an
on-time is chosen as approximately what it would be for
an ideal fixed-frequency PWM in similar input/output
voltage conditions. The result is a big improvement but
the switching frequency still varies considerably over line
and load due to losses in the switches and inductor and
other parasitic effects.
actual switching frequency and modifying the on-time with
a feedback loop to keep the average switching frequency
in the desired range.
Another problem with many COT architectures is their
dependence on adequate ESR in the output capacitor,
making it difficult to use highly-desirable, small, low-cost,
but low-ESR ceramic capacitors. Most COT architectures
use AC current information from the output capacitor,
generated by the inductor current passing through the
ESR, to function in a way like a current mode control
system. With ceramic capacitors the inductor current
information is too small to keep the control loop stable,
like a current mode system with no current information.
ACOTTM Control Architecture
Making the on-time proportional to VOUT and inversely
proportional to VIN is not sufficient to achieve good
constant-frequency behavior for several reasons. First,
voltage drops across the MOSFET switches and inductor
cause the effective input voltage to be less than the
measured input voltage and the effective output voltage to
be greater than the measured output voltage. As the load
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
One way to reduce these effects is to measure the actual
switching frequency and compare it to the desired range.
This has the added benefit eliminating the need to sense
the actual output voltage, potentially saving one pin
connection. ACOTTM uses this method, measuring the
To achieve good stability with low-ESR ceramic capacitors,
ACOTTM uses a virtual inductor current ramp generated
inside the IC. This internal ramp signal replaces the ESR
ramp normally provided by the output capacitor's ESR.
The ramp signal and other internal compensations are
optimized for low-ESR ceramic output capacitors.
ACOTTM One-shot Operation
The RT7275/76 control algorithm is simple to understand.
The feedback voltage, with the virtual inductor current ramp
added, is compared to the reference voltage. When the
combined signal is less than the reference the on-time
one-shot is triggered, as long as the minimum off-time
one-shot is clear and the measured inductor current
(through the synchronous rectifier) is below the current
limit. The on-time one-shot turns on the high-side switch
and the inductor current ramps up linearly. After the ontime, the high-side switch is turned off and the synchronous
rectifier is turned on and the inductor current ramps down
linearly. At the same time, the minimum off-time one-shot
is triggered to prevent another immediate on-time during
the noisy switching time and allow the feedback voltage
and current sense signals to settle. The minimum off-time
is kept short (230ns typical) so that rapidly-repeated ontimes can raise the inductor current quickly when needed.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT7275/76
Discontinuous Operating Mode (RT7276 Only)
After soft start, the RT7275 operates in fixed frequency
mode to minimize interference and noise problems. The
RT7276 uses variable-frequency discontinuous switching
at light loads to improve efficiency. During discontinuous
switching, the on-time is immediately increased to add
“hysteresis” to discourage the IC from switching back to
continuous switching unless the load increases
substantially.
The IC returns to continuous switching as soon as an ontime is generated before the inductor current reaches zero.
The on-time is reduced back to the length needed for
700kHz switching and encouraging the circuit to remain
in continuous conduction, preventing repetitive mode
transitions between continuous switching and
discontinuous switching.
Current Limit
The RT7275/76 current limit is a cycle-by-cycle “valley”
type, measuring the inductor current through the
synchronous rectifier during the off-time while the inductor
current ramps down. The current is determined by
measuring the voltage between source and drain of the
synchronous rectifier, adding temperature compensation
for greater accuracy. If the current exceeds the upper
current limit, the on-time one-shot is inhibited until the
inductor current ramps down below the upper current limit
plus a wide hysteresis band of about 1A and drops below
the lower current limit level. Thus, only when the inductor
current is well below the upper current limit is another ontime permitted. This arrangement prevents the average
output current from greatly exceeding the guaranteed
upper current limit value, as typically occurs with other
valley-type current limits. If the output current exceeds
the available inductor current (controlled by the current
limit mechanism), the output voltage will drop. If it drops
below the output under-voltage protection level (see next
section) the IC will stop switching to avoid excessive heat.
The RT7275 also includes a negative current limit to protect
the IC against sinking excessive current and possibly
damaging the IC. If the voltage across the synchronous
rectifier indicates the negative current is too high, the
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
synchronous rectifier turns off until after the next highside on-time. The RT7276 does not sink current and
therefore does not need a negative current limit.
Output Over-voltage Protection and Under-voltage
Protection
The RT7275/76 include output over-voltage protection
(OVP). If the output voltage rises above the regulation
level, the high-side switch naturally remains off and the
synchronous rectifier turns on. If the output voltage remains
high the synchronous rectifier remains on until the inductor
current reaches the negative current limit (RT7275) or until
it reaches zero (RT7276). If the output voltage remains
high, the IC's switches remain off. If the output voltage
exceeds the OVP trip threshold for longer than 5μs
(typical), the IC's OVP is triggered.
The RT7275/76 include output under-voltage protection
(UVP). If the output voltage drops below the UVP trip
threshold for longer than 250μs (typical) the IC's UVP is
triggered.
There are two different behaviors for OVP and UVP events,
one for the WDFN-10L 3x3 packages and one for the
TSSOP-14 (Exposed Pad) packages.

Hiccup Mode (WDFN-10L 3x3 Only)

T he RT7275GQW/RT7276GQW, use hiccup mode OVP
and UVP. When the protection function is triggered, the
IC will shut down for a period of time and then attempt
to recover automatically. Hiccup mode allows the circuit
to operate safely with low input current and power
dissipation, and then resume normal operation as soon
as the overload or short circuit is removed. During hiccup
mode, the shutdown time is determined by the capacitor
at SS. A 0.5μA current source discharges VSS from its
starting voltage (normally VPVCC). The IC remains shut
down until VSS reaches 0.2V, about 40ms for a 3.9nF
capacitor. At that point the IC begins to charge the SS
capacitor at 2μA, and a normal start-up occurs. If the
fault remains, OVP and UVP protection will be enabled
when VSS reaches 2.2V (typical). The IC will then shut
down and discharge the SS capacitor from the 2.2V
level, taking about 17ms for a 3.9nF SS capacitor.
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76

Latch-Off Mode (TSSOP-14 (Exposed Pad) Only)

The RT7275GCP/RT7276GCP, use latch-off mode OVP
and UVP. When the protection function is triggered the
IC will shut down. The IC stops switching, leaving both
switches open, and is latched off. To restart operation,
toggle EN or power the IC off and then on again.
Shut-down, Start-up and Enable (EN)
The enable input (EN) has a logic-low level of 0.4V. When
VEN is below this level the IC enters shutdown mode and
supply current drops to less than 10μA. When VEN exceeds
its logic-high level of 2V the IC is fully operational.
Between these 2 levels there are 2 thresholds (1.2V typical
and 1.4V typical). When VEN exceeds the lower threshold
the internal bias regulators begin to function and supply
current increases above the shutdown current level.
Switching operation begins when VEN exceeds the upper
threshold. Unlike many competing devices, EN is a high
voltage input that can be safely connected to VIN (up to
18V) for automatic start-up.
Input Under-voltage Lock-out
In addition to the enable function, the RT7275/76 feature
an under-voltage lock-out (UVLO) function that monitors
the internal linear regulator output (PVCC). To prevent
operation without fully-enhanced internal MOSFET
switches, this function inhibits switching when PVCC
drops below the UVLO-falling threshold. The IC resumes
switching when PVCC exceeds the UVLO-rising threshold.
Soft-Start (SS)
The RT7275/76 soft-start uses an external pin (SS) to
clamp the output voltage and allow it to slowly rise. After
VEN is high and PVCC exceeds its UVLO threshold, the
IC begins to source 2μA from the SS pin. An external
capacitor at SS is used to adjust the soft-start timing.
The available capacitance range is from 2.7nF to 220nF.
Do not leave SS unconnected.
output voltage may be pre-biased to some positive level
before start-up. Once the VSS ramp charges enough to
raise the internal reference above the feedback voltage,
switching will begin and the output voltage will smoothly
rise from the pre-biased level to its regulated level. After
VSS rises above about 2.2V output over-and under-voltage
protections are enabled and the RT7275 begins
continuous-switching operation.
Internal Regulator (PVCC)
An internal linear regulator (PVCC) produces a 5.1V supply
from VIN that powers the internal gate drivers, PWM logic,
reference, analog circuitry, and other blocks. If VIN is 6V
or greater, PVCC is guaranteed to provide significant power
for external loads.
PGOOD Comparator
PGOOD is an open drain output controlled by a comparator
connected to the feedback signal. If FB exceeds 90% of
the internal reference voltage, PGOOD will be high
impedance. Otherwise, the PGOOD output is connected
to PGND.
External Bootstrap Capacitor (C6)
Connect a 0.1μF low ESR ceramic capacitor between
BOOT and SW. This bootstrap capacitor provides the gate
driver supply voltage for the high side N-channel MOSFET
switch.
Over Temperature Protection
The RT7275/76 includes an over temperature protection
(OTP) circuitry to prevent overheating due to excessive
power dissipation. The OTP will shut down switching
operation when the junction temperature exceeds 150°C.
Once the junction temperature cools down by
approximately 20°C the IC will resume normal operation
with a complete soft-start. For continuous operation,
provide adequate cooling so that the junction temperature
does not exceed 150°C.
During start-up, while the SS capacitor charges, the
RT7275/76 operate in discontinuous switching mode with
very small pulses. This prevents negative inductor currents
and keeps the circuit from sinking current. Therefore, the
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT7275/76
Typical Application Circuit
RT7275/76
VIN
C1
10µF x 2
C2
0.1µF
VIN
VINR
Output Signal
PVCC
R3 100k
Input Signal
C4
1µF
C5
3.9nF
SW
BOOT
FB
L1
1.4µH
C6
0.1µF
C7
22µF x 2
R1
8.25k
R2
22k
PGOOD
EN
PVCC
SS
C3
VOUT
1.05V/3A
VOUT
PGND GND
Table 1. Suggested Component Values (VIN = 12V)
VOUT (V)
R1 (k)
R2 (k)
C3 (pF)
L1 (H)
C7 (F)
1
6.81
22.1
--
1.4
22 to 68
1.05
8.25
22.1
--
1.4
22 to 68
1.2
12.7
22.1
--
1.4
22 to 68
1.8
30.1
22.1
5 to 22
2
22 to 68
2.5
49.9
22.1
5 to 22
2
22 to 68
3.3
73.2
22.1
5 to 22
2
22 to 68
5
124
22.1
5 to 22
3.3
22 to 68
7
180
22.1
5 to 22
3.3
22 to 68
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Design Procedure
Inductor Selection
Selecting an inductor involves specifying its inductance
and also its required peak current. The exact inductor value
is generally flexible and is ultimately chosen to obtain the
best mix of cost, physical size, and circuit efficiency.
Lower inductor values benefit from reduced size and cost
and they can improve the circuit's transient response, but
they increase the inductor ripple current and output voltage
ripple and reduce the efficiency due to the resulting higher
peak currents. Conversely, higher inductor values increase
efficiency, but the inductor will either be physically larger
or have higher resistance since more turns of wire are
required and transient response will be slower since more
time is required to change current (up or down) in the
inductor. A good compromise between size, efficiency,
and transient response is to use a ripple current (ΔIL) about
20-50% of the desired full output load current. Calculate
the approximate inductor value by selecting the input and
output voltages, the switching frequency (f SW), the
maximum output current (IOUT(MAX)) and estimating a ΔIL
as some percentage of that current.
L=
VOUT   VIN  VOUT 
VIN  fSW  IL
Once an inductor value is chosen, the ripple current (ΔIL)
is calculated to determine the required peak inductor
current.
VOUT   VIN  VOUT 
I
IL =
and IL(PEAK) = IOUT(MAX)  L
VIN  fSW  L
2
To guarantee the required output current, the inductor
needs a saturation current rating and a thermal rating that
exceeds IL(PEAK). These are minimum requirements. To
maintain control of inductor current in overload and shortcircuit conditions, some applications may desire current
ratings up to the current limit value. However, the IC's
output under-voltage shutdown feature make this
unnecessary for most applications.
IL(PEAK) should not exceed the minimum value of IC's upper
current limit level or the IC may not be able to meet the
desired output current. If needed, reduce the inductor ripple
current (ΔIL) to increase the average inductor current (and
the output current) while ensuring that IL(PEAK) does not
exceed the upper current limit level.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
For best efficiency, choose an inductor with a low DC
resistance that meets the cost and size requirements.
For low inductor core losses some type of ferrite core is
usually best and a shielded core type, although possibly
larger or more expensive, will probably give fewer EMI
and other noise problems.
Considering the Typical Operating Circuit for 1.05V output
at 3A and an input voltage of 12V, using an inductor ripple
of 1A (33%), the calculated inductance value is :
L=
1.05V  12V  1.05V 
= 1.4μH
12V  700kHz  1A
The ripple current was selected at 1A and, as long as we
use the calculated 1.4μH inductance, that should be the
actual ripple current amount. Typically the exact calculated
inductance is not readily available and a nearby value is
chosen. In this case 1.4μH was available and actually used
in the typical circuit. To illustrate the next calculation,
assume that for some reason is was necessary to select
a 1.8μH inductor (for example). We would then calculate
the ripple current and required peak current as below :
1.05V  12V  1.05V 
IL =
= 0.76A
12V  700kHz  1.8μH
and IL(PEAK) = 3A  0.76 = 3.38A
2
For the 1.8μH value, the inductor's saturation and thermal
rating should exceed 3.38A. Since the actual value used
was 1.4μH and the ripple current exactly 1A, the required
peak current is 3.5A.
Input Capacitor Selection
The input filter capacitors are needed to smooth out the
switched current drawn from the input power source and
to reduce voltage ripple on the input. The actual
capacitance value is less important than the RMS current
rating (and voltage rating, of course). The RMS input ripple
current (IRMS) is a function of the input voltage, output
voltage, and load current :
IRMS = IOUT 
VOUT   VVIN  VOUT 
VVIN
Ceramic capacitors are most often used because of their
low cost, small size, high RMS current ratings, and robust
surge current capabilities. However, take care when these
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT7275/76
capacitors are used at the input of circuits supplied by a
wall adapter or other supply connected through long, thin
wires. Current surges through the inductive wires can
induce ringing at the RT7275/76's input which could
potentially cause large, damaging voltage spikes at VIN.
If this phenomenon is observed, some bulk input
capacitance may be required. Ceramic capacitors (to meet
the RMS current requirement) can be placed in parallel
with other types such as tantalum, electrolytic, or polymer
(to reduce ringing and overshoot).
Choose capacitors rated at higher temperatures than
required. Several ceramic capacitors may be paralleled to
meet the RMS current, size, and height requirements of
the application. The typical operating circuit uses two 10μF
and one 0.1μF low ESR ceramic capacitors on the input.
Output Capacitor Selection
The RT7275/76 are optimized for ceramic output capacitors
and best performance will be obtained using them. The
total output capacitance value is usually determined by
the desired output voltage ripple level and transient response
requirements for sag (undershoot on positive load steps)
and soar (overshoot on negative load steps).
Output Ripple
Output ripple at the switching frequency is caused by the
inductor current ripple and its effect on the output
capacitor's ESR and stored charge. These two ripple
components are called ESR ripple and capacitive ripple.
Since ceramic capacitors have extremely low ESR and
relatively little capacitance, both components are similar
in amplitude and both should be considered if ripple is
critical.
VRIPPLE = VRIPPLE(ESR)  VRIPPLE(C)
VRIPPLE(ESR) = IL  RESR
IL
VRIPPLE(C) =
8  COUT  fSW
For the Typical Operating Circuit for 1.05V output and an
inductor ripple of 1A, with 2 x 22μF output capacitance
each with about 5mΩ ESR including PCB trace resistance,
the output voltage ripple components are :
VRIPPLE(ESR) = 1A  2.5m = 2.5mV
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
16
VRIPPLE(C) =
1A
= 4mV
8  44μF  0.7MHz
VRIPPLE = 2.5mV  4mV = 6.5mV
Output Transient Undershoot and Overshoot
In addition to voltage ripple at the switching frequency,
the output capacitor and its ESR also affect the voltage
sag (undershoot) and soar (overshoot) when the load steps
up and down abruptly. The ACOT transient response is
very quick and output transients are usually small.
However, the combination of small ceramic output
capacitors (with little capacitance), low output voltages
(with little stored charge in the output capacitors), and
low duty cycle applications (which require high inductance
to get reasonable ripple currents with high input voltages)
increases the size of voltage variations in response to
very quick load changes. Typically, load changes occur
slowly with respect to the IC's 700kHz switching frequency.
But some modern digital loads can exhibit nearly
instantaneous load changes and the following section
shows how to calculate the worst-case voltage swings in
response to very fast load steps.
The output voltage transient undershoot and overshoot each
have two components : the voltage steps caused by the
output capacitor's ESR, and the voltage sag and soar due
to the finite output capacitance and the inductor current
slew rate. Use the following formulas to check if the ESR
is low enough (typically not a problem with ceramic
capacitors) and the output capacitance is large enough to
prevent excessive sag and soar on very fast load step
edges, with the chosen inductor value.
The amplitude of the ESR step up or down is a function of
the load step and the ESR of the output capacitor:
VESR_STEP = IOUT  RESR
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor value,
the input-to-output voltage differential, and the maximum
duty cycle. The maximum duty cycle during a fast transient
is a function of the on-time and the minimum off-time since
the ACOTTM control scheme will ramp the current using
on-times spaced apart with minimum off-times, which is
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
as fast as allowed. Calculate the approximate on-time
(neglecting parasitics) and maximum duty cycle for a given
input and output voltage as :
VOUT
tON
tON =
and DMAX =
VIN  fSW
tON  tOFF(MIN)
The actual on-time will be slightly longer as the IC
compensates for voltage drops in the circuit, but we can
neglect both of these since the on-time increase
compensates for the voltage losses. Calculate the output
voltage sag as :
VSAG =
L  (IOUT )2
2  COUT   VIN(MIN)  DMAX  VOUT 
The amplitude of the capacitive soar is a function of the
load step, the output capacitor value, the inductor value
and the output voltage :
L  (IOUT )
2  COUT  VOUT
2
VSOAR =
For the Typical Operating Circuit for 1.05V output, the
circuit has an inductor 1.4μH and 2 x 22μF output
capacitance with 5mΩ ESR each. The ESR step is 3A x
2.5mΩ = 7.5mV which is small, as expected. The output
voltage sag and soar in response to full 0A-3A-0A
instantaneous transients are :
1.05V
t ON =
= 125ns
12V  700kHz
and DMAX =
VSAG =
125ns
= 0.35
125ns  230ns
1.4μH  (3A)2
= 45mV
2  44μF  12V  0.35  1.05V 
1.4μH  (3A)
= 136mV
2  44μF  1.05V
2
VSOAR =
The sag is about 4% of the output voltage and the soar is
a full 13% of the output voltage. The ESR step is negligible
here but it does partially add to the soar, so keep that in
mind whenever using higher-ESR output capacitors.
The soar is typically much worse than the sag in highinput, low-output step-down converters because the high
input voltage demands a large inductor value which stores
lots of energy that is all transferred into the output if the
load stops drawing current. Also, for a given inductor, the
soar for a low output voltage is a greater voltage change
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
and an even greater percentage of the output voltage. This
is illustrated by comparing the previous to the next
example.
The Typical Operating Circuit for 12V to 3.3V with a 2μH
inductor and 2 x 22μF output capacitance can be used to
illustrate the effect of a higher output voltage. The output
voltage sag and soar in response to full 0A-3A-0A
instantaneous transients are calculated as follows :
t ON =
3.3V
= 392ns
12V  700kHz
and DMAX =
392ns
= 0.63
392ns  230ns
VSAG =
2μH  (3A)2
= 48mV
2  44μF  12V  0.63  3.3V 
VSOAR =
2μH  (3A)2
= 62mV
2  44μF  3.3V
In this case the sag is about 1.5% of the output voltage
and the soar is only 2% of the output voltage.
Any sag is always short-lived, since the circuit quickly
sources current to regain regulation in only a few switching
cycles. With the RT7275, any overshoot transient is
typically also short-lived since the converter will sink
current, reversing the inductor current sharply until the
output reaches regulation again. The RT7276's
discontinuous operation at light loads prevents sinking
current so, for that IC, the output voltage will soar until
load current or leakage brings the voltage down to normal.
Most applications never experience instantaneous full load
steps and the RT7275/76's high switching frequency and
fast transient response can easily control voltage regulation
at all times. Also, since the sag and soar both are
proportional to the square of the load change, if load steps
were reduced to 1A (from the 3A examples preceding) the
voltage changes would be reduced by a factor of almost
ten. For these reasons sag and soar are seldom an issue
except in very low-voltage CPU core or DDR memory
supply applications, particularly for devices with high clock
frequencies and quick changes into and out of sleep
modes. In such applications, simply increasing the amount
of ceramic output capacitor (sag and soar are directly
proportional to capacitance) or adding extra bulk
capacitance can easily eliminate any excessive voltage
transients.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
17
RT7275/76
In any application with large quick transients, always
calculate soar to make sure that over-voltage protection
will not be triggered. Under-voltage is not likely since the
threshold is very low (70%), that function has a long delay
(250μs), and the IC will quickly return the output to
regulation. Over-voltage protection has a minimum
threshold of 115% and short delay of 5μs and can actually
be triggered by incorrect component choices, particularly
for the RT7276 which does not sink current.
Output Capacitors Stability Criteria
The RT7275/76's ACOTTM control architecture uses an
internal virtual inductor current ramp and other
compensation that ensures stability with any reasonable
output capacitor. The internal ramp allows the IC to operate
with very low ESR capacitors and the IC is stable with
very small capacitances. Therefore, output capacitor
selection is nearly always a matter of meeting output
voltage ripple and transient response requirements, as
discussed in the previous sections. For the sake of the
unusual application where ripple voltage is unimportant
and there are few transients (perhaps battery charging or
LED lighting) the stability criteria are discussed below.
The equations giving the minimum required capacitance
for stable operation include a term that depends on the
output capacitor's ESR. The higher the ESR, the lower
the capacitance can be and still ensure stability. The
equations can be greatly simplified if the ESR term is
removed by setting ESR to zero. The resulting equation
gives the worst-case minimum required capacitance and
it is usually sufficiently small that there is usually no need
for the more exact equation.
The required output capacitance (COUT) is a function of
the inductor value (L) and the input voltage (VIN) :
11
COUT  5.23  10
VIN  L
The worst-case high capacitance requirement is for low
VIN and small inductance, so a 5V to 3.3V converter is
used for an example. Using the inductance equation in a
previous section to determine the required inductance :
3.3V   5V  3.3V 
L=
= 1.6μH
5V  700kHz  1A
Therefore, the required minimum capacitance for the 5V
to 3.3V converter is :
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
18
11
COUT  5.23  10
= 6.6μF
5V  1.6μH
Using the 12V to 1.05V typical application as another
example :
11
COUT  5.24  10
= 3.1μF
12V  1.4μH
Any ESR in the output capacitor lowers the required
minimum output capacitance, sometimes considerably.
For the rare application where that is needed and useful,
the equation including ESR is given here :
VOUT
COUT 
2  fSW  VIN  (RESR  13647  L  VOUT )
As can be seen, setting RESR to zero and simplifying the
equation yields the previous simpler equation. To allow
for the capacitor's temperature and bias voltage coefficients,
use at least double the calculated capacitance and use a
good quality dielectric such as X5R or X7R with an
adequate voltage rating since ceramic capacitors exhibit
considerable capacitance reduction as their bias voltage
increases.
Feed-forward Capacitor (C3)
The RT7275/76 are optimized for ceramic output capacitors
and for low duty cycle applications. This optimization
makes circuit stability easy to achieve with reasonable
output capacitors. However, the optimization affects the
quality factor (Q) of the circuit and therefore its transient
response. To avoid an under-damped response (high Q)
and its potential ringing, the internal compensation was
chosen to achieve perfect damping for low output voltages,
where the FB divider has low attenuation (VOUT is close
to VREF). For high-output voltages, with high feedback
attenuation, the circuit’s response becomes over-damped
and transient response can be slowed. In high-output
voltage circuits (VOUT > 1.5V) transient response is
improved by adding a small “feed-forward” capacitor (C3)
across the upper FB divider resistor, to increase the
circuit's Q and reduce damping to speed up the transient
response without affecting the steady-state stability of
the circuit. Choose a capacitor value that gives, together
with the divider impedance at FB, a time-constant between
100ns and 0.5μs. The divider impedance at FB is R1 in
parallel with R2. C3 can be safely left out in low-output
voltage circuits and if fast transient response is not required.
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Applications Information
Current-Sinking Applications (RT7275)
Soft-Start
The RT7275's is not recommended for current sinking
applications even though its continuous switching
operation allows the IC to sink some current. Sinking
enables a fast recovery from output voltage overshoot
caused by load transients and is normally useful for
applications requiring negative currents, such as DDR VTT
bus termination applications and changing-output voltage
applications where the output voltage needs to slew
quickly from one voltage to another. However, the IC's
negative current limit is set low (about 1.6A) and the current
limit behavior latches the synchronous rectifier off until
the high-side switch's next pulse, to prevent the possibility
of IC damage from large negative currents. Therefore,
sinking current is not necessarily available at all times.
The RT7275/76 contains an external soft-start clamp that
gradually raises the output voltage. The soft-start timing
can be programmed by the external capacitor between
SS pin and GND. The chip provides a 2μA charge current
for the external capacitor. If a 3.9nF capacitor is used,
the soft-start will be 2.6ms (typ.). The available capacitance
range is from 2.7nF to 220nF.
C5 (nF)  1.365
t SS (ms) =
ISS ( A)
If implementing applications where current-sinking may
occur, take care to allow for the current that is delivered
to the input supply. A step-down converter in sinking
operation functions like a backwards step-up converter.
The current that is sunk at its output terminals is delivered
up to its input terminals. If this current has no outlet, the
input voltage will rise.
A good arrangement for long-term sinking applications is
for a sinking supply (supply A) that is sinking current
sourced from supply B, to both be powered by the same
input supply. That way, any current delivered back to the
input by supply A is current that just left the input through
supply B. In this way, the current simply makes a round
trip and the input supply will not rise.
In cases where this is not possible, make sure that there
are sufficient other loads on the input supply to prevent
that supply's voltage from rising high enough to cause
damage to itself or any of its loads. In cases where the
sinking is not long-term, such as output-voltage slewing
applications, make sure there is sufficient input capacitance
to control any input voltage rise. The worst-case voltage
rise is :
C
 VOUT
VIN = OUT
CIN
Enable Operation (EN)
For automatic start-up the high-voltage EN pin can be
connected to VIN, either directly or through a 100kΩ
resistor. Its large hysteresis band makes EN useful for
simple delay and timing circuits. EN can be externally
pulled to VIN by adding a resistor-capacitor delay (REN
and CEN in Figure 1). Calculate the delay time using EN's
internal threshold where switching operation begins (1.4V,
typical).
An external MOSFET can be added to implement digital
control of EN when no system voltage above 2V is available
(Figure 2). In this case, a 100kΩ pull-up resistor, REN, is
connected between VIN and the EN pin. MOSFET Q1 will
be under logic control to pull down the EN pin. To prevent
enabling circuit when VIN is smaller than the VOUT target
value or some other desired voltage level, a resistive voltage
divider can be placed between the input voltage and ground
and connected to EN to create an additional input undervoltage lockout threshold (Figure 3).
EN
VIN
REN
EN
RT7275/76
CEN
GND
Figure 1. External Timing Control
VIN
Enable
REN
100k
EN
Q1
RT7275/76
GND
Figure 2. Digital Enable Control Circuit
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
19
RT7275/76
VIN
External BOOT Bootstrap Diode
REN1
EN
REN2
RT7275/76
GND
Figure 3. Resistor Divider for Lockout Threshold Setting
Output Voltage Setting
Set the desired output voltage using a resistive divider
from the output to ground with the midpoint connected to
FB. The output voltage is set according to the following
equation :
R1
VOUT = 0.765  (1
)
R2
VOUT
R1
FB
RT7275/76
R2
GND
Figure 4. Output Voltage Setting
Place the FB resistors within 5mm of the FB pin. Choose
R2 between 10kΩ and 100kΩ to minimize power
consumption without excessive noise pick-up and
calculate R1 as follows :
R2  (VOUT  0.765V)
0.765V
For output voltage accuracy, use divider resistors with 1%
R1 =
or better tolerance.
Under Voltage Lockout Protection
The RT7275/76 feature an under-voltage lock-out (UVLO)
function that monitors the internal linear regulator output
(PVCC) and prevents operation if VPVCC is too low. In some
multiple input voltage applications, it may be desirable to
use a power input that is too low to allow VPVCC to exceed
the UVLO threshold. In this case, if there is another lowpower supply available that is high enough to operate the
PVCC regulator, connecting that supply to VINR (TSSOP14 (Exposed Pad) only) will allow the IC to operate, using
the lower-voltage high-power supply for the DC/DC power
path. Because of the internal linear regulator, any supply
regulated or unregulated) between 4.5V and 18V will
operate the IC.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
20
When the input voltage is lower than 5.5V it is
recommended to add an external bootstrap diode between
VIN (or VINR) and the BOOT pin to improve enhancement
of the internal MOSFET switch and improve efficiency.
The bootstrap diode can be a low cost one such as 1N4148
or BAT54.
5V
BOOT
RT7275/76
0.1µF
SW
Figure 5. External Bootstrap Diode
External BOOT Capacitor Series Resistance
The internal power MOSFET switch gate driver is
optimized to turn the switch on fast enough for low power
loss and good efficiency, but also slow enough to reduce
EMI. Switch turn-on is when most EMI occurs since VSW
rises rapidly. During switch turn-off, SW is discharged
relatively slowly by the inductor current during the deadtime between high-side and low-side switch on-times.
In some cases it is desirable to reduce EMI further, at the
expense of some additional power dissipation. The switch
turn-on can be slowed by placing a small (<10Ω)
resistance between BOOT and the external bootstrap
capacitor. This will slow the high-side switch turn-on and
VSW's rise. To remove the resistor from the capacitor
charging path (avoiding poor enhancement due to undercharging the BOOT capacitor), use the external diode
shown in figure 5 to charge the BOOT capacitor and place
the resistance between BOOT and the capacitor/diode
connection.
PVCC Capacitor Selection
Decouple PVCC to PGND with a 1μF ceramic capacitor.
High grade dielectric (X7R, or X5R) ceramic capacitors
are recommended for their stable temperature and bias
voltage characteristics.
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Maximum Power Dissipation (W)1
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of the IC package and the PCB layout, the rate
of surrounding airflow, and the difference between the
junction and ambient temperatures. The maximum power
dissipation can be calculated by the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
the TSSOP-14 (Exposed Pad) package the thermal
resistance, θJA, is 40°C/W on a standard JEDEC 51-7
four-layer thermal test board. For the WDFN-10L 3x3
package the thermal resistance, θJA, is 60°C/W on a
standard JEDEC 51-7 four-layer thermal test board. These
standard thermal test layouts have a very large area with
long 2oz. copper traces connected to each IC pin and
very large, unbroken 1oz. internal power and ground planes.
Meeting the performance of the standard thermal test
board in a typical tiny board area requires wide copper
traces well-connected to the IC's backside pad leading to
exposed copper areas on the component side of the board
as well as good thermal vias from the backside pad
connecting to a wide inner-layer ground plane and, perhaps,
to an exposed copper area on the board's solder side.
Using the backside tab in this way, 40°C/W is achievable
in a small area with either package.
The maximum power dissipation at TA = 25°C can be
calculated by the following formulas:
P D(MAX) = (125°C − 25°C) / (40°C/W) = 2.50W for
TSSOP-14 (Exposed Pad) package
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
Four-Layer PCB
TSSOP-14 (Exposed Pad)
2.5
2.0
1.5
WDFN-10L3x3
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the RT7275/76.

Keep the traces of the main current paths as short and
wide as possible.

Put the input capacitor as close as possible to the device
pins (VIN and PGND).

The high-frequency switching node (SW) has large
voltage swings and fast edges and can easily radiate
noise to adjacent components. Keep its area small to
prevent excessive EMI, while providing wide copper
traces to minimize parasitic resistance and inductance.
Keep sensitive components away from the SW node or
provide ground traces between for shielding, to prevent
stray capacitive noise pickup.

Connect the feedback network to the output capacitors
rather than the inductor. Place the feedback components
near the FB pin.

The exposed pad, PGND, and GND should be connected
to large copper areas for heat sinking and noise
protection. Provide dedicated wide copper traces for the
power path ground between the IC and the input and
output capacitor grounds, rather than connecting each
of these individually to an internal ground plane.

Avoid using vias in the power path connections that have
switched currents (from CIN to PGND and CIN to VIN)
and the switching node (SW).
P D(MAX) = (125°C − 25°C) / (60°C/W) = 1.67W for
WDFN-10L 3x3 package
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curves in Figure 6 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.0
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
21
RT7275/76
Place the feedback components
as close to the FB as possible
for better regulation.
VOUT
R1
VOUT
2
FB
3
PVCC
R2 CVCC
4
SS
5
GND
6
PGOOD
7
EN
Place the input and output
capacitors as close to the
IC as possible.
PGND
VINR
VIN
BOOT
SW
SW
PGND
PGND
14
13
12
PGND
11
10
15
9
8
CIN
CBOOT
L
VOUT
COUT
SW should be connected to inductor by
Wide and short trace. Keep sensitive
components away from this trace.
(a). For TSSOP-14 (Exposed Pad) Package
Place the feedback components
as close to the FB as possible
for better regulation.
Place the input and output
capacitors as close to the
IC as possible.
VOUT
R1
CVCC
R2
EN
FB
PVCC
SS
PGOOD
1
2
3
4
5
PGND
PGND
11
PGND
10
9
8
7
6
CIN
VIN
VIN CBOOT
BOOT
SW
SW
L
COUT
SW should be connected to
inductor by Wide and short trace.
Keep sensitive components away
from this trace.
VOUT
(b). For WDFN-10L 3x3 Package
Figure 7. PCB Layout Guide
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
22
is a registered trademark of Richtek Technology Corporation.
DS7275/76-01 July 2015
RT7275/76
Outline Dimension
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
1.000
1.200
0.039
0.047
A1
0.000
0.150
0.000
0.006
A2
0.800
1.050
0.031
0.041
b
0.190
0.300
0.007
0.012
D
4.900
5.100
0.193
0.201
e
0.650
0.026
E
6.300
6.500
0.248
0.256
E1
4.300
4.500
0.169
0.177
L
0.450
0.750
0.018
0.030
U
1.900
2.900
0.075
0.114
V
1.600
2.600
0.063
0.102
14-Lead TSSOP (Exposed Pad) Plastic Package
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS7275/76-01 July 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
23
RT7275/76
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
24
DS7275/76-01 July 2015