® RT7241A 12A, 23V, 500kHz, ACOTTM Synchronous Buck Converter with VTT LDO for Memory Power Supply General Description The RT7241A provides complete protection features including OCP, OVP, UVP, and thermal shutdown. The RT7241A is available in the UQFN-18L 3x4 package. The RT7241A provides a complete power supply for DDR3/ DDR3L/LPDDR3/DDR4 memory systems. It integrates an Advanced Constant On-Time (ACOTTM) mode synchronous Buck converter with a 1.5A sink/source tracking linear regulator. Applications The PWM converter provides low quiescent supply current, high efficiency, excellent transient response, and high DC output accuracy needed for stepping down highvoltage batteries to generate low-voltage chipset RAM supplies in notebook computers. The ACOTTM control scheme handles wide input/output voltage ratios with ease and provides a very fast response to load transients with no external compensators. DDR3/DDR3L/LPDDR3/DDR4 Memory Power Supplies Notebook computers Marking Information 00= : Product Code YMDNN : Date Code 00=YM DNN The 1.5A sink/source VTT LDO maintains fast transient response only requiring 10μF ceramic output capacitance. The RT7241A supports all of the sleep state controls placing VTT at high-Z in S3 and discharging VDDQ and VTT in S4/S5. Simplified Application Circuit VIN VIN CIN BOOT RT7241A PHASE CB L VDDQ VDD VDD CVDD RPGOOD PGOOD PGOOD S3 S5 R1 FB S3 S5 GND COUT R2 PGND VDDQ VLDOIN VTT VTTSNS VTTGND CS CVTT VTT RCS Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT7241A DDR3/DDR3L/LPDDR3/DDR4 Complete Solution PWM Converter (VDDQ) 100μ μA Low Quiescent Supply Current at S3 Mode TM ACOT Mode Performs Fast Transient Response Support MLCC Output Capacitors Integrated Low On-Resistance MOSFETs 17mΩ Ω of High-Side MOSFET 4.5mΩ Ω of Low-Side MOSFET Adjustable from 0.6V to 1.5V Output Range for 1.5V (DDR3), 1.35V (DDR3L), 1.2V (LPDDR3) and 1.2V (DDR4) 4.5V to 23V Battery Input Range 500kHz Switching Frequency Resistor Adjustable Valley Current Limit Over-/Under-Voltage Protection Internal Voltage Ramp Soft-Start Power Good Indicator 1.5A LDO (VTT) Capable to Sink and Source up to 1.5A LDO Input Available to Optimize Power Losses Require Only 10μ μF Ceramic Output Capacitor Integrated Divider Tracks 1/2 VDDQ for VTT Accuracy ±20mV for VTT Support High-Z in S3 and Soft-Off in S4/S5 Tracking Mode Discharge Control Thermal Capable Flip-chip (FC) Package for 12A VDDQ Converter and 1.5A VTT LDO RoHS Compliant and Halogen Free Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 RT7241A Package Type QUF : UQFN-18L 3x4 (FC) (U-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Pin Configurations (TOP VIEW) S5 CS FB GND VDD Ordering Information 18 17 16 15 14 S3 BOOT PHASE PHASE 13 PGOOD 12 VIN 1 2 3 11 PGND 10 PGND 4 5 6 7 8 9 VDDQ VLDOIN VTT VTTGND VTTSNS Features UQFN-18L 3x4 (FC) is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Function Pin Description Pin No. Pin Name Pin Function 1 S3 VTT LDO Enable Control Input. Do not leave this pin floating. 2 BOOT Bootstrap Supply for High-Side Gate Driver. A capacitor is needed to drive the power switch's gate above the supply voltage. It is connected between the PHASE and BOOT pins to form a floating supply across the power switch driver. 3, 4 PHASE 5 VDDQ 6 VLDOIN Power Supply for the VTT LDO. 7 VTT Power Output for the VTT LDO. 8 VTTGND Power Ground for the VTT LDO. 9 VTTSNS Voltage Sense Input for the VTT LDO. Connect to the terminal of the VTT LDO output capacitor. PGND Power Ground for VDDQ. 12 VIN Supply Input for VDDQ. 13 PGOOD Open-Drain Power Good Indicator Output. 14 VDD Analog Supply Input. 15 GND Analog Ground. 16 FB Feedback Voltage Input. Connect to a resistive voltage divider from VDDQ to GND to adjust the output of PWM converter. 17 CS Current Limit Threshold Setting Input. Connect to GND through the setting resistor. 18 S5 PWM Converter Enable Control Input. Do not leave this pin floating. 10, 11 Switch Node. External inductor connection for VDDQ. Reference Input for the VTT LDO. An internal discharging circuit is connected to this pin. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT7241A Function Block Diagram Buck Converter VIN BOOT UVLO 4.2V VDD Internal SST S5 Thermal Protection PHASE PWM Control and Protect Logic PGND PGOOD 0.6V FB Over Current Protection + - CS GND VTT LDO VDDQ Thermal Shutdown VLDOIN - S5 Control Logic + S3 + + VTT + - VTTSNS VTTGND Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Absolute Maximum Ratings (Note 1) VIN to PGND -------------------------------------------------------------------------------------------- −0.3V to 27V SW to PGND -------------------------------------------------------------------------------------------- −0.3V to 27.3V BOOT to PGND ----------------------------------------------------------------------------------------- −0.6V to 33.3V S3,VDDQ,VLDOIN,VTT,VTTSNS,PGOOD,VDD,FB,CS,S5 to GND ------------------------ −0.3V to 6V PGND to GND ------------------------------------------------------------------------------------------- −0.3V to 0.3V PGND to VTTGND -------------------------------------------------------------------------------------- −0.3V to 0.3V GND to VTTGND ---------------------------------------------------------------------------------------- −0.3V to 0.3V Power Dissipation, PD @ TA = 25°C UQFN-18L 3x4 (FC) ------------------------------------------------------------------------------------ 1.46W Package Thermal Resistance (Note 2) UQFN-18L 3x4 (FC), θJA ------------------------------------------------------------------------------ 68.2°C/W UQFN-18L 3x4 (FC), θJC ------------------------------------------------------------------------------ 5.2°C/W Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------ 260°C Junction Temperature ---------------------------------------------------------------------------------- 150°C Storage Temperature Range ------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) --------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 3) Supply Input Voltage, VIN ---------------------------------------------------------------------------- 4.5V to 23V Junction Temperature Range ------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 80 100 130 A -- 1 -- A Supply Current IVLDOIN BIAS Current FB forced above the regulation point, VS5 = 2V, VS3 = 0V VS5 = VS3 = 2V, VTT = No Load IVLDOIN Standby Current VS5 = 2V, VS3 = 0V, VTT = No Load -- 0.1 10 A Shutdown Current VS5 = VS3 = 0V -- 2.5 10 A 0.6 -- 1.5 V -- 100 -- k VS5 = 0V -- 15 -- RDS(ON)_H VBOOT VPHASE = 5V -- 17 -- RDS(ON)_L -- 4.5 -- -- 16 -- Quiescent Supply Current PWM Converter VDDQ Voltage Range VDDQ Input Resistance VDDQ Shutdown Discharge Resistance Switch On-Resistance Switch On-Resistance m Current Limit Current Limit ILIM Valley current of low-side switch, RCS = 165k Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 A is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT7241A Parameter Symbol Test Conditions Min Typ Max Unit Switching Frequency and Min. Off Timer Switching Frequency f SW 425 500 575 kHz Minimum On Time tON -- 60 -- ns Minimum Off Time tOFF 160 200 240 ns 112 117 122 % -- 5 -- s 60 70 80 % -- 2 -- s 0.594 0.6 0.606 V VFB = 0.6V 1 0.1 1 A From S5 high to 90% of VREF 0.5 1 1.5 ms Logic-High 0.8 -- -- Logic-Low -- -- 0.4 Output Under-Voltage and Over-Voltage Protection OVP Trip Threshold VOVP OVP Propagation Delay TOVPDLY UVP Trip Threshold VUVP UVP Propagation Delay TUVPDLY Measured at FB, with respect to reference voltage FB force above OVP threshold Measured at FB, with respect to reference voltage FB force below UVP threshold Reference and Soft-Start FB Reference Voltage VREF FB Input Bias Current Soft-Start Time tSS Enable and UVLO S3, S5 Input Voltage V VDD Input UVLO Threshold Wake up 3.9 4.2 4.5 V VDD Input UVLO Hysteresis Shutdown -- 0.2 -- V Measured at FB, with respect to reference, no load 87 91 95 % -- 3 -- % -- 2.5 -- s -- -- 0.4 V -- -- 1 A -- 165 -- C -- 25 -- C VDDQ = VLDOIN = 1.2V / 1.35V / 1.5V / 1.8V, |IVTT| = 0A 20 -- 20 VDDQ = VLDOIN = 1.2V / 1.35V / 1.5V / 1.8V, |IVTT| = 1A 30 -- 30 VDDQ = VLDOIN = 1.2V / 1.35V, |IVTT| = 1.2A 40 -- 40 VDDQ = VLDOIN = 1.5V / 1.8V, |IVTT| = 1.5A 40 -- 40 Power Good Trip Threshold (Raising) Trip Threshold (Hysteresis) Falling edge, FB forced below PGOOD trip threshold ISINK = 1mA Fault Propagation Delay Output Low Voltage Leakage Current ILEAK High state, forced to 5V Thermal Shutdown Thermal Shutdown TSD Thermal Shutdown Hysteresis TSD VTT LDO VTT Output Tolerance VVTTTOL Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 mV is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Parameter Symbol Test Conditions Min Typ Max Unit VTT Source Current Limit IVTTOCLSRC VTT = 0V 1.6 2.6 3.6 A VTT Sink Current Limit IVTTOCLSNK VTT = VDDQ 1.6 2.6 3.6 A VTT Leakage Current IVTTLK V S5 = 5V, S3 = 0V, VTT = VDDQ 2 10 -- 10 A VTTSNS Leakage Current IVTTSNSLK ISINK = 1mA 1 -- 1 A VTT Discharge Resistance RDSCHRG S5 = S3 = 0V -- 6 -- Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT7241A Typical Application Circuit 12 VIN CIN 4.7µF x 2 VIN 14 VDD CVDD 1µF VDD RPGOOD 100k 13 PGOOD S3 S5 RCS 165k PGOOD 1 S3 18 S5 17 CS 15 GND RBOOT (Optional) 2.2 BOOT 2 RT7241A PHASE 3, 4 CBOOT 0.1µF L 0.56µH CFF 100pF FB 16 10, 11 PGND VDDQ VLDOIN R1 14.3k R2 12k 5 VDDQ 1.35V CVDDQ 22µF x 5 6 VTT 7 VTTSNS 9 8 VTTGND CVTT 10µF VTT Figure 1. Typical Application Circuit for VOUT = 1.35V Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Typical Operating Characteristics Performace waveforms are tested on the evaluation board of the Typical Application Circuit, VIN = 12V, VOUT = 1.35V, L = 0.56˜H, TJ = 25°C, unless otherwise noted. Efficiency vs. Load Current Switching Frequency vs. Load Current 550 95 540 90 Efficiency (%) 85 80 VIN = 7.4V VIN = 12V VIN = 19V 75 70 65 60 VDDQ = 1.35V, VDD = 5V, fSW = 500kHz, L = 0.56μH, DCR = 1.8mΩ 55 50 0.001 0.010 0.100 1.000 10.000 Switching Frequency (kHz)1 100 530 520 510 500 VIN = 7.4V VIN = 12V VIN = 19V 490 480 470 460 VDDQ = 1.35V, VDD = 5V, S5 = 5V 450 100.000 2 3 4 5 6 Load Current (A) 7 8 9 10 11 12 Load Current (A) Quiescent Current vs. VDD Input Voltage Shutdown Current vs. VDD Input Voltage 10 125 Shutdown Current (μA)1 Quiescent Current (μA) 9 123 120 118 115 113 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 7 6 5 4 3 2 1 VIN = 12V, S5 = 5V, S3 = GND, No Switching 110 8 VIN = 12V, S5 = 5V, S3 = GND 0 4.5 5.5 VDD Input Voltage (V) 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 VDD Input Voltage (V) VTT Output Voltage vs. Load Current VDDQ Output Voltage vs. Load Current 0.705 1.40 1.39 1.38 Output Voltage (V) Output Voltage (V) 0.695 0.685 0.675 0.665 1.37 1.36 1.35 1.34 1.33 1.32 0.655 VIN = 12V, VDDQ = 1.35V, VDD = 5V 0.645 -1.5 -1 -0.5 0 0.5 1 Load Current (A) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 1.5 1.31 1.30 0.00 VIN = 12V, VDDQ = 1.35V, VDD = 5V 0.01 0.10 1.00 10.00 Load Current (A) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT7241A VDDQ Power On by S5 VDDQ Power On by S5 VDDQ (400mV/Div) VDDQ (400mV/Div) S5 (5V/Div) S5 (5V/Div) PGOOD (5V/Div) IL (2A/Div) PGOOD (5V/Div) IL (10A/Div) VIN = 12V, No Load Time (200μs/Div) Time (200μs/Div) VDDQ Power On by VDD VDDQ Power On by VDD VDDQ (400mV/Div) VDDQ (400mV/Div) VDD (5V/Div) VDD (5V/Div) PGOOD (5V/Div) IL (2A/Div) PGOOD (5V/Div) IL (10A/Div) VIN = 12V, No Load, VDD Hot Plug VIN = 12V, ILOAD = 12A, VDD Hot Plug Time (200μs/Div) Time (200μs/Div) VDDQ Power Off by S5 VDDQ Power Off by S5 VDDQ (400mV/Div) VDDQ (400mV/Div) S5 (5V/Div) S5 (5V/Div) PGOOD (5V/Div) IL (1A/Div) PGOOD (5V/Div) IL (10A/Div) VIN = 12V, No Load Time (2ms/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 VIN = 12V, ILOAD = 12A VIN = 12V, ILOAD = 12A Time (10μs/Div) is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A VDDQ Power Off by VDD VDDQ Power Off by VDD VDDQ (400mV/Div) VDDQ (400mV/Div) VDD (5V/Div) VDD (5V/Div) PGOOD (5V/Div) IL (1A/Div) PGOOD (5V/Div) IL (10A/Div) VIN = 12V, No Load VIN = 12V, ILOAD = 12A Time (10ms/Div) Time (10μs/Div) VTT Power On by S3 VTT Power Off by S3 VDDQ (400mV/Div) VTT (400mV/Div) VDDQ (400mV/Div) VTT (400mV/Div) S3 (5V/Div) S3 (5V/Div) IL (2A/Div) IL (2A/Div) VIN = 12V, No Load VIN = 12V, No Load Time (10μs/Div) Time (20ms/Div) VTT Power On by S5 VTT Power Off by S5 VDDQ (400mV/Div) VTT (400mV/Div) VDDQ (400mV/Div) VTT (400mV/Div) S5 (5V/Div) S5 (5V/Div) IL (2A/Div) IL (2A/Div) VIN = 12V, No Load Time (200μs/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 VIN = 12V, No Load Time (1ms/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT7241A UVP VDDQ Load Transient VDDQ (1V/Div) VDDQ (50mV/Div) SW (10V/Div) PGOOD (5V/Div) IL (5A/Div) VIN = 12V, ILOAD = 1.2A to 12A @ 2.5A/μs Time (100μs/Div) IL (10A/Div) VIN = 12V, Pulse Load Time (20μs/Div) OVP VDDQ (1V/Div) VIN (10V/Div) PGOOD (5V/Div) IL (5A/Div) VIN = 12V, VDDQ = 1.56V, No Load Time (10ms/Div) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Application Information The RT7241A is high-performance 500kHz 12A step-down regulators with internal power switches and synchronous rectifiers. It features an Advanced Constant On-Time (ACOT TM) control architecture that provides stable operation for ceramic output capacitors without complicated external compensation, among other benefits. The input voltage range is from 4.5V to 23V. The output voltage is adjustable from 0.6V to 1.5V. The proprietary ACOT TM control scheme improves conventional constant on-time architectures, achieving nearly constant switching frequency over line, load, and output voltage ranges. Since there is no internal clock, response to transients is nearly instantaneous and inductor current can ramp quickly to maintain output regulation without large bulk output capacitance. The 1.5A sink/source VTT LDO maintains fast transient response, only requiring 10μF of ceramic output capacitance. The RT7241A supports all of the sleep state controls, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5. ACOTTM Control Architecture Making the on-time proportional to VOUT and inversely proportional to VIN is not sufficient to achieve good constant-frequency behavior for several reasons. First, voltage drops across the MOSFET switches and inductor cause the effective input voltage to be less than the measured input voltage and the effective output voltage to be greater than the measured output voltage as sensing input and output voltage from LX pin. When the load change, the switch voltage drops change causing a switching frequency variation with load current. Also, at light loads if the inductor current goes negative, the switch dead-time between the synchronous rectifier turn-off and the high-side switch turn-on allows the switching node to rise to the input voltage. This increases the effective ontime and causes the switching frequency to drop noticeably. One way to reduce these effects is to measure the actual switching frequency and compare it to the desired range. This has the added benefit eliminating the need to sense the actual output voltage, potentially saving one pin Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 connection. ACOTTM uses this method, measuring the actual switching frequency and modifying the on-time with a feedback loop to keep the average switching frequency in the desired range. In order to achieve good stability with low-ESR ceramic capacitors, ACOTTM uses a virtual inductor current ramp generated inside the IC. This internal ramp signal replaces the ESR ramp normally provided by the output capacitor’s ESR. The ramp signal and other internal compensations are optimized for low-ESR ceramic output capacitors. ACOTTM One-shot Operation The RT7241A control algorithm is simple to understand. The feedback voltage, with the virtual inductor current ramp added, is compared to the reference voltage. When the combined signal is less than the reference, the on-time one-shot is triggered, as long as the minimum off-time one-shot is clear and the measured inductor current (through the synchronous rectifier) is below the current limit. The on-time one-shot turns on the high-side switch and the inductor current ramps up linearly. After the ontime, the high-side switch is turned off and the synchronous rectifier is turned on and the inductor current ramps down linearly. At the same time, the minimum off-time one-shot is triggered to prevent another immediate on-time during the noisy switching time and allow the feedback voltage and current sense signals to settle. The minimum off-time is kept short (200ns typical) so that rapidly-repeated ontimes can raise the inductor current quickly when needed. Diode Emulation Mode In diode emulation mode, the RT7241A automatically reduces switching frequency at light load conditions to maintain high efficiency. This reduction of frequency is achieved smoothly. As the output current decreases from heavy load condition, the inductor current is also reduced, and eventually comes to the point that its current valley touches zero, which is the boundary between continuous conduction and discontinuous conduction modes. To emulate the behavior of diodes, the low-side MOSFET allows only partial negative current to flow when the inductor free wheeling current becomes negative. As the load current is further decreased, it takes longer and longer is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT7241A time to discharge the output capacitor to the level that requires the next “ON” cycle. In reverse, when the output current increases from light load to heavy load, the switching frequency increases to the preset value as the inductor current reaches the continuous conduction. The transition load point to the light load operation is shown in Figure 2. and can be calculated as follows : IL Slpoe = (VIN - VOUT) / L IPEAK VTT Linear Regulator The RT7241A integrates a high performance low dropout linear regulator that is capable of sourcing and sinking currents up to 1.5A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough for keeping track of VDDQ/2 within 40mV at all conditions, including fast load transient. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of the VTT output capacitor(s) as a separate trace from the VTT pin. For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 10μF. ILOAD = IPEAK / 2 Current Limit Setting for VDDQ (CS) The RT7241A current limit is adjustable by CS pin and it tON t Figure 2. Boundary Condition of CCM/DEM ILOAD (VIN VOUT ) tON 2L where tON is the on-time. The switching waveforms may appear noisy and asynchronous when light load causes diode emulation operation. This is normal and results in high efficiency. Trade offs in DEM noise vs. light load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load transient response (especially at low input voltage levels). During discontinuous switching, the on-time is immediately increased to add “hysteresis” to discourage the IC from switching back to continuous switching unless the load increases substantially. The IC returns to continuous switching as soon as an on-time is generated before the inductor current reaches zero. The on-time is reduced back to the length needed for 500kHz switching and encouraging the circuit to remain in continuous conduction, preventing repetitive mode transitions between continuous switching and discontinuous switching. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a cycle-by-cycle “valley” type, measuring the inductor current through the synchronous rectifier during the offtime while the inductor current ramps down. The current is determined by measuring the voltage between source and drain of the synchronous rectifier, adding temperature compensation for greater accuracy. If the current exceeds the current limit, the on-time one-shot is inhibited until the inductor current ramps down below the current limit. Thus, only when the inductor current is well below the current limit, another on-time is permitted. If the output current exceeds the available inductor current (controlled by the current limit mechanism), the output voltage will drop. If it drops below the output under-voltage protection level (see next section) the IC will stop switching to avoid excessive heat. The RT7241A also includes a negative current limit to protect the IC against sinking excessive current and possibly damaging the IC. If the voltage across the synchronous rectifier indicates the negative current is too high, the synchronous rectifier turns off until after the next high side on-time. The RT7241A provides adjustable OCP setting via change the RCS to decide the current limit. The current limit can be derived by the following equation : ILIM = 2.64 x 106/RCS The default setting of RCS is 165kΩ, which means current limit is 16A. The maximum current limit should be lower than 20A. is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Output Over-voltage Protection and Under-voltage Protection for VDDQ The RT7241A includes output over-voltage protection (OVP). If the output voltage rises above the regulation level, the high-side switch naturally remains off and the synchronous rectifier will periodically turn on until the inductor current reaches the negative current limit or undervoltage protection is triggered. If the output voltage exceeds the OVP trip threshold for longer than 5μs (typical), the IC's OVP is triggered. The RT7241A also includes output under-voltage protection (UVP). If the output voltage drops below the UVP trip threshold for longer than 2μs (typical) the IC's UVP is triggered. The RT7241A uses latch-off mode OVP and UVP. When the protection function is triggered, the IC will shut down. The IC stops switching and is latched off. To restart operation, toggle S5 or power the IC off by VDD and then on again. Current Protection for VTT Output Management by S3, S5 Control In DDR2/DDR3 memory applications, it is important to always keep VDDQ higher than VTT/VTTREF, even during start-up and shutdown. The RT7241A provides this management by simply connecting both S3 and S5 terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in notebook PC system. All VDDQ and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ is kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT output is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the two outputs are disabled and discharged to ground. The code of each state represents the following: S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 1) Table 1. S3 and S5 Truth Table STATE S3 S5 VDDQ VTT S0 Hi Hi On On S3 Lo Hi On Off(Hi-Z) S4/S5 Lo Lo Off (Discharge) Off (Discharge) The LDO has an internally fixed constant over current limit of 2.6A while operating at normal condition. VDD Under Voltage Lockout (UVLO) In addition to the enable function, the RT7241A features an UVLO function that monitors the VDD voltage. To prevent operation without fully-enhanced internal MOSFET switches, this function inhibits switching when VDD voltage drops below the UVLO-falling threshold. The IC resumes switching when VDD voltage exceeds the UVLO-rising threshold. Over Temperature Protection The RT7241A includes an over temperature protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP will shut down switching operation when the junction temperature exceeds 165°C. Once the junction temperature cools down by approximately 25°C the IC will resume normal operation with a complete soft-start. For continuous operation, provide adequate cooling so that the junction temperature does not exceed 165°C. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 VDDQ and VTT Tracking Discharge Mode The RT7241A discharges VDDQ and VTT outputs when S5 is low or in the S4/S5 state. In tracking discharge mode, the RT7241A discharges outputs through the internal switch and VTT output tracks half of the VDDQ voltage during this discharge. Note that if VLDOIN is supplied by external volatge source, an input decoupling capacitor about 10μF is needed at the input. The VTT LDO can handle up to 1.5A for both source/sink, and discharge with high-Z in S3. Soft-Start The RT7241A provides an internal soft-start function to prevent large inrush current and output voltage overshoot when the converter starts up. The soft-start (SS) automatically begins once the chip is enabled. During softstart, it clamps the ramping of internal reference voltage which is compared with FB signal. The typical soft-start duration is 1ms. is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT7241A Power Good Output (PGOOD) The power good output is an open drain output that requires a pull-up resistor. When the output voltage is 20% (typical) below its set voltage, PGOOD will be pulled low. It is held low until the output voltage returns to 93% of its set voltage once more. During soft-start, PGOOD is actively held low and only allowed to be pulled high after soft-start is over and the output reaches 93% of its set voltage. There is a 2.5μs delay built into PGOOD circuitry to prevent false transition. External Bootstrap Capacitor (CBOOT) Connect a 0.1μF low ESR ceramic capacitor between BOOT pin and LX pin. This bootstrap capacitor provides the gate driver supply voltage for the high side N-channel MOSFET switch. The internal power MOSFET switch gate driver is optimized to turn the switch on fast enough for low power loss and good efficiency, but also slow enough to reduce EMI. Switch turn-on is when most EMI occurs since VSW rises rapidly. During switch turn-off, SW is discharged relatively slowly by the inductor current during the deadtime between high-side and low-side switch on-times. In some cases it is desirable to reduce EMI further, at the expense of some additional power dissipation. The switch turn-on can be slowed by placing a small (<10Ω) resistance between BOOT and the external bootstrap capacitor. This will slow the high-side switch turn-on and VSW's rise. Setting the Output Voltage The output voltage of RT7241A is adjustable and with valley control. There is an easy way to determine the output voltage only by two resistors, R1 and R2. As the feedback circuit shown in Figure 3, the relation of VOUT and VREF can be derived as VOUT = (1+R1/R2) x VREF readily. Generally, the stability is a serious issue for converter. In order to achieve better performance on stability and transient, a feed-forward capacitor, CFF, is added to increase the noise margin and transient response of loop control. However, there is a tradeoff of adding a feed-forward capacitor. An additional dc offset will be generated on output voltage due to the amplified feedback ripple by feedforward compensator. This is not always the case that Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 every CFF makes the same value of dc offset, it is based on different pole and zero placement generated by R1, R2 and C FF. For simplicity, a symbol named Vdc,offset is supposed to be the value of dc offset. This value may influence the performance (e.g. regulation or peak value of VOUT) of converter slightly, the suggested CFF is to select a pair of pole and zero to provide the maximum phase lead at switching frequency. VOUT,valley = 1 + R1 VREF + Vdc,offset R2 VOUT,valley is the valley of output voltage, and Vdc,offset is used for describing the additional dc offset on VOUT, the value is related to the output voltage ripple and CFF. VOUT R1 CFF (opt.) FB RT7241A R2 GND Figure 3. The Equivalent Circuit of Feedback Loop Inductor Selection Selecting an inductor involves specifying its inductance and also its required peak current. The exact inductor value is generally flexible and is ultimately chosen to obtain the best mix of cost, physical size, and circuit efficiency. Lower inductor values benefit from reduced size and cost and they can improve the circuit’s transient response, but they increase the inductor ripple current and output voltage ripple and reduce the efficiency due to the resulting higher peak currents. Conversely, higher inductor values increase efficiency, but the inductor will either be physically larger or have higher resistance since more turns of wire are required and transient response will be slower since more time is required to change current (up or down) in the inductor. A good compromise between size, efficiency, and transient response is to use a ripple current (ΔIL) about 20-50% of the desired full output load current. Calculate the approximate inductor value by selecting the input and output voltages, the switching frequency (f SW), the maximum output current (IOUT(MAX)) and estimating a ΔIL as some percentage of that current. V (VIN VOUT ) L OUT VIN fSW IL is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Once an inductor value is chosen, the ripple current (ΔIL) is calculated to determine the required peak inductor current. V (VIN VOUT ) I IL OUT and IL(PEAK) IOUT(MAX) L VIN fSW L 2 To guarantee the required output current, the inductor needs a saturation current rating and a thermal rating that exceeds IL(PEAK). These are minimum requirements. To maintain control of inductor current in overload and shortcircuit conditions, some applications may desire current ratings up to the current limit value. However, the IC's output under-voltage shutdown feature make this unnecessary for most applications. For best efficiency, choose an inductor with a low DC resistance that meets the cost and size requirements. For low inductor core losses some type of ferrite core is usually best and a shielded core type, although possibly larger or more expensive, will probably give fewer EMI and other noise problems. Input Capacitor Selection High quality ceramic input decoupling capacitor, such as X5R or X7R, with values greater than 20μF are recommended for the input capacitor. The X5R and X7R ceramic capacitors are usually selected for power regulator capacitors because the dielectric material has less capacitance variation and more temperature stability. Voltage rating and current rating are the key parameters when selecting an input capacitor. Generally, selecting an input capacitor with voltage rating 1.5times greater than the maximum input voltage is a conservatively safe design. The input capacitor is used to supply the input RMS current, which can be approximately calculated using the following equation : IRMS VOUT V I 2 (1 OUT ) IOUT 2 L VIN VIN 12 The next step is to select a proper capacitor for RMS current rating. One good design uses more than one capacitor with low Equivalent Series Resistance (ESR) in parallel to form a capacitor bank. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be approximately calculated using the following equation : Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 VIN IOUT VIN V (1 OUT ) CIN fSW VOUT VIN The typical operating circuit is recommended to use two 10μF and low ESR ceramic capacitors on the input. Output Capacitor Selection The RT7241A is optimized for ceramic output capacitors and best performance will be obtained using them. The total output capacitance value is usually determined by the desired output voltage ripple level and transient response requirements for sag (undershoot on positive load steps) and soar (overshoot on negative load steps). Output ripple at the switching frequency is caused by the inductor current ripple and its effect on the output capacitor's ESR and stored charge. These two ripple components are called ESR ripple and capacitive ripple. Since ceramic capacitors have extremely low ESR and relatively little capacitance, both components are similar in amplitude and both should be considered if ripple is critical. VRIPPLE VRIPPLE(ESR) VRIPPLE(C) VRIPPLE(ESR) IL RESR VRIPPLE(C) IL 8 COUT fSW In addition to voltage ripple at the switching frequency, the output capacitor and its ESR also affect the voltage sag (undershoot) and soar (overshoot) when the load steps up and down abruptly. The ACOT transient response is very quick and output transients are usually small. However, the combination of small ceramic output capacitors (with little capacitance), low output voltages (with little stored charge in the output capacitors), and low duty cycle applications (which require high inductance to get reasonable ripple currents with high input voltages) increases the size of voltage variations in response to very quick load changes. Typically, load changes occur slowly with respect to the IC's 500kHz switching frequency. But some modern digital loads can exhibit nearly instantaneous load changes and the following section shows how to calculate the worst-case voltage swings in response to very fast load steps. The amplitude of the ESR step up or down is a function of the load step and the ESR of the output capacitor : is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT7241A VESR_STEP IOUT RESR Thermal Considerations The amplitude of the capacitive sag is a function of the load step, the output capacitor value, the inductor value, the input-to-output voltage differential, and the maximum duty cycle. The maximum duty cycle during a fast transient is a function of the on-time and the minimum off-time since the ACOTTM control scheme will ramp the current using on-times spaced apart with minimum off-times, which is as fast as allowed. Calculate the approximate on-time (neglecting parasitics) and maximum duty cycle for a given input and output voltage as : VOUT tON tON and DMAX VIN fSW tON + tOFF(MIN) For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : The actual on-time will be slightly longer as the IC compensates for voltage drops in the circuit, but we can neglect both of these since the on-time increase compensates for the voltage losses. Calculate the output voltage sag as : For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For UQFN-18L 3x4 (FC) package, the thermal resistance, θJA, L ( IOUT )2 2 COUT ( VIN(MIN) DMAX VOUT ) The amplitude of the capacitive soar is a function of the load step, the output capacitor value, the inductor value and the output voltage : VSOAR 2 L (IOUT ) 2 COUT VOUT Most applications never experience instantaneous full load steps and the RT7241A's high switching frequency and fast transient response can easily control voltage regulation at all times. Therefore, sag and soar are seldom an issue except in very low-voltage CPU core or DDR memory supply applications, particularly for devices with high clock frequencies and quick changes into and out of sleep modes. In such applications, simply increasing the amount of ceramic output capacitor (sag and soar are directly proportional to capacitance) or adding extra bulk capacitance can easily eliminate any excessive voltage transients. In any application with large quick transients, it should calculate soar and sag to make sure that over-voltage protection and under-voltage protection will not be triggered. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. is 68.2°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (68.2°C/W) = 1.46W for UQFN-18L 3x4 (FC) package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 4 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 2.0 Maximum Power Dissipation (W)1 VSAG PD(MAX) = (TJ(MAX) − TA) / θJA Four-Layer PCB 1.6 1.2 0.8 0.4 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 4. Derating Curve of Maximum Power Dissipation is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Layout Considerations Layout is very important in high frequency switching converter design. The PCB can radiate excessive noise and contribute to converter instability with improper layout. Certain points must be considered before starting a layout using the RT7241A. Make the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins (VIN and GND). Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high voltage switching node. Phase node encounters high frequency voltage swings so it should be kept in a small area. Keep sensitive components away from the phase node to prevent stray as possible. VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for VLDOIN, an input bypass capacitor should be placed as close as possible to the pin with short and wide trace. The output capacitor for VTT should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL of the trace. It is strongly recommended to connect VTTSNS to the positive node of VTT output capacitor(s) as a separate trace from the high current power line to avoid additional ESR and/or ESL. If it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. It is also recommended to minimize any additional ESR and/or ESL of ground trace between the GND pin and the output capacitor(s). The GND pin should be connected to a strong ground plane for heat sinking and noise protection. Avoid using vias in the power path connections that have switched currents (from CIN to GND and CIN to VIN) and the switching node (Phase). An example of PCB layout guide is shown in Figure 5 for reference. CFF The voltage divider must be connected as close to the chip as possible PGND RCS PGND CS FB GND VDD R2 S5 Phase should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. VDDQ R1 18 17 16 15 14 CVDD 13 PGOOD The input capacitor must be placed near the chip PGND COUT S3 1 BOOT 2 PHASE 3 12 VIN CBOOT CIN L 7 VTT 8 9 VTTSNS VDDQ 6 VTTGND 5 VDDQ 11 PGND 10 PGND 4 VTT PHASE VLDOIN The output capacitor must be placed near the chip PGND CVTT Figure 5. PCB Layout Guide Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7241A-00 January 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT7241A Outline Dimension Symbol A A1 A3 D E b b1 b2 b3 L L1 L2 L3 L4 e K K1 K2 K3 K4 K5 K6 K7 H Dimensions In Millimeters Min. 0.500 0.000 0.100 2.900 3.900 0.150 0.350 0.150 0.200 0.325 1.390 0.300 1.950 0.420 Max. 0.600 0.050 0.175 3.100 4.100 0.250 0.450 0.250 0.300 0.425 1.490 0.400 2.050 0.520 Dimensions In Inches Min. 0.020 0.000 0.004 0.114 0.154 0.006 0.014 0.006 0.008 0.013 0.055 0.012 0.077 0.017 0.450 0.490 1.370 2.215 2.965 1.060 1.510 1.935 2.685 0.150 Max. 0.024 0.002 0.007 0.122 0.161 0.010 0.018 0.010 0.012 0.017 0.059 0.016 0.081 0.020 0.018 0.019 0.054 0.087 0.117 0.042 0.059 0.076 0.106 0.006 U-Type 18L QFN 3x4 (FC) Package Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS7241A-00 January 2016 RT7241A Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS7241A-00 January 2016 www.richtek.com 21