CYPRESS LUPA-4000

LUPA-4000
Data Sheet
LUPA-4000
4M Pixel
CMOS Image Sensor
Datasheet
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 1 of 49
LUPA-4000
Data Sheet
Document history record
Issue
Date
1.0 August, 2004
1.0 November, 2004
1.1
November, 2004
1.2
December 23, 2004
Description of changes
Origination
Correct bias voltages precharge_bias and
Pre_load
Updated timing diagrams and timing
explanation
Added Cypress equivalent part numbers,
ordering information
Added Cypress Document # 38-05712
Rev ** in the document footer.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 2 of 49
LUPA-4000
Data Sheet
TABLE OF CONTENTS
1
PREAMBLE ..........................................................................................................5
1.1
1.2
1.3
2
OVERVIEW .........................................................................................................5
MAIN FEATURES ................................................................................................5
PART NUMBER ...................................................................................................5
SPECIFICATIONS...............................................................................................6
2.1 GENERAL SPECIFICATIONS .................................................................................6
2.2 ELECTRO-OPTICAL SPECIFICATIONS ...................................................................6
2.2.1 Overview ....................................................................................................6
2.2.2 Spectral response curve .............................................................................7
2.2.3 Photo-voltaic response curve.....................................................................8
2.3 FEATURES AND GENERAL SPECIFICATIONS.........................................................9
2.4 ELECTRICAL SPECIFICATIONS ..........................................................................10
2.4.1 Recommended operating conditions ........................................................10
3
SENSOR ARCHITECTURE .............................................................................11
3.1 THE 6-T PIXEL .................................................................................................12
3.2 FRAME RATE AND WINDOWING ........................................................................13
3.2.1 Frame rate ...............................................................................................13
3.2.2 ROI read out (windowing) .......................................................................13
3.3 OUTPUT AMPLIFIER..........................................................................................14
3.4 PIXEL ARRAY DRIVERS.....................................................................................14
3.5 COLUMN AMPLIFIERS.......................................................................................15
3.6 ANALOG TO DIGITAL CONVERTER...................................................................15
3.6.1 ADC timing ..............................................................................................16
3.6.2 Setting of the ADC reference voltages .....................................................16
3.7 SYNCHRONOUS SHUTTER .................................................................................17
3.8 NON-DESTRUCTIVE READOUT (NDR) ..............................................................17
3.9 OPERATION AND SIGNALLING ..........................................................................18
3.9.1 Power supplies and ground .....................................................................18
3.9.2 Start-up sequence.....................................................................................20
3.9.3 Biasing and analog signals......................................................................20
3.10
PIXEL ARRAY SIGNALS .................................................................................22
3.10.1
Digital signals.......................................................................................24
3.10.2
Test signals ...........................................................................................24
4
TIMING AND READ OUT OF THE IMAGE SENSOR................................26
4.1 TIMING OF THE PIXEL ARRAY ...........................................................................27
4.2 READ OUT OF THE IMAGE SENSOR ....................................................................29
4.2.1 X- and Y-addressing.................................................................................29
4.2.2 Reduced Row Overhead Time timing.......................................................32
4.2.2.a
4.2.2.b
Standard timing (200ns)................................................................................................33
Back-up timing (ROT =100-200 ns).............................................................................33
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 3 of 49
LUPA-4000
Data Sheet
4.2.3 Precharging of the buses .........................................................................34
4.3 SERIAL-PARALLEL-INTERFACE (SPI) ..............................................................35
5
PIN LIST..............................................................................................................36
6
GEOMETRY AND MECHANICAL SPECIFICATIONS .............................40
6.1
6.2
6.3
6.4
BARE DIE .........................................................................................................40
PACKAGE DRAWING .........................................................................................41
BONDING PADS ................................................................................................43
BONDING DIAGRAM .........................................................................................44
7
HANDLING AND SOLDERING PRECAUTIONS ........................................45
8
ORDERING INFORMATION ..........................................................................46
APPENDIX A: LUPA-4000 EVALUATION SYSTEM.........................................47
APPENDIX B: FREQUENTLY ASKED QUESTIONS .....................................48
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 4 of 49
LUPA-4000
Data Sheet
1 Preamble
1.1 Overview
This document describes the interfacing and the driving of the LUPA-4000 image
sensor. This 4 mega-pixel CMOS active pixel sensor features synchronous shutter and
a maximal frame-rate of 15fps in full resolution. The readout speed can be boosted by
means of sub sampling and windowed Region Of Interest (ROI) readout. High
dynamic range scenes can be captured using the double and multiple slope
functionality.
The sensor can be used with one or two outputs. Two on chip 10-bit ADC’s can be
used to convert the analog data to a 10-bit digital word stream. The sensor uses a 3wire Serial-Parallel (SPI) interface. It is housed in a 127-pin ceramic PGA package.
This datasheet allows the user to develop a camera-system based on the described
timing and interfacing.
1.2 Main features
The main features of the image sensor are identified as:
•
•
•
•
•
•
•
•
•
•
•
•
2048 x 2048 active pixels (4M pixel resolution).
12 µm2 square pixels (based on the high-fill factor active pixel sensor
technology of FillFactory (US patent No. 6,225,670 and others)).
Peak QE x FF of 37.50%.
Optical format: 24,6 mm x 24,6 mm
Pixel rate of 66 MHz using a 33 MHz system clock.
Optical dynamic range: 66 dB (2000:1) in single slope operation and up to 90
dB in multiple slope operation.
2 On-chip 10 bit, 33 MSamples/s ADC.
Full snapshot shutter.
Random programmable windowing and sub-sampling modes.
127-pin PGA package
Binning (Voltage averaging in X-direction)
Programmable read out direction (X and Y)
1.3 Part Number
Name
LUPA-4000-M
CYIL1SM4000AA-GBC (preliminary)
Package
127 pin
ceramic PGA
Monochrome / color
Monochrome
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 5 of 49
LUPA-4000
Data Sheet
2 Specifications
2.1 General specifications
Table 1: General specifications
Parameter
Specification
Remarks
Pixel
architecture
Pixel size
Resolution
Pixel rate
6T-pixel
Shutter type
Pipelined snapshot
shutter
15 frames/second
Based on the high fill-factor active pixel sensor
technology of FillFactory
The resolution and pixel size results in a 24,6 mm x
24,6mm optical active area.
Using a 33 MHz system clock and 1 or 2 parallel
outputs.
Full snapshot shutter (integration during read out is
possible).
Frame rate increase possible with ROI read out and/or
sub sampling.
Full frame rate
12 µm x 12 µm
2048 x2048
66 MHz
2.2 Electro-optical specifications
2.2.1 Overview
Table 2: Electro-optical specifications
Parameter
Specification
Remarks
FPN
PRNU
Conversion gain
Output
signal
amplitude
Saturation charge
Sensitivity
<1.25 % RMS
<2.5% RMS
13.5 uV/electron
1V
of max. output swing
at 25% and 75% (% of the signal)
@ output (measured).
Converted by 2 on-chip 10-bit ADC’s in 2x10 parallel
digital outputs. Or to be used with external ADC’s
Peak QE * FF
Peak SR * FF
80.000 e2090 V.m2/W.s
11.61 V/lux.s
37.5 %
0.19 A/W
Dark current (@ 21
°C)
Noise
electrons
<140 mV/s
or 10000 e-/s
< 40 e-
S/N ratio
Spectral sensitivity
range
Parasitic sensitivity
2000:1
400 – 1000 nm
66 dB.
< 1/5000
I.e. sensitivity of the storage node during read out (after
integration).
MTF
Power dissipation
64%
<200 mWatt
Average white light.
Visible band only (180 lx = 1 W/m2).
Average QE*FF = 35%.
Average SR*FF = 0.15 A/W.
See spectral response curve.
Typical (without ADC’s).
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 6 of 49
LUPA-4000
Data Sheet
2.2.2 Spectral response curve
QE 40%
0.20
QE 30%
QE 25%
0.18
QE 20%
Spectral response [A/W]
0.16
0.14
0.12
0.10
QE 10%
0.08
0.06
0.04
0.02
0.00
400
500
600
700
800
900
1000
Wavelength [nm]
Figure 1: Spectral response curve
Figure 1 shows the spectral response characteristic. The curve is measured directly on
the pixels. It includes effects of non-sensitive areas in the pixel, e.g. interconnection
lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE * FF is
37.5% approximately between 500 and 700 nm. In view of a fill factor of 60%, the
QE is thus larger than 60% between 500 and 700 nm.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 7 of 49
LUPA-4000
Data Sheet
2.2.3 Photo-voltaic response curve
1.2
1
Output swing [V]
0.8
0.6
0.4
0.2
0
0
20000
40000
60000
80000
100000
120000
140000
# electrons
Figure 2: Photo-voltaic response curve
Figure 2 shows the pixel response curve in linear response mode. This curve is the
relation between the electrons detected in the pixel and the output signal. The
resulting voltage-electron curve is independent of any parameters. The voltage to
electrons conversion gain is 13.5 µV/electron.
Note that the upper part of the curve (near saturation) is actually a logarithmic
response.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 8 of 49
LUPA-4000
Data Sheet
2.3 Features and general specifications
Table 3: Features and general specifications
Feature
Specification/Description
Electronic shutter type
Windowing (ROI)
Sub-sampling and binning
modes
Read out direction
Extended dynamic range
Full snapshot shutter (integration during read out is possible).
Randomly programmable ROI read out.
2:1 subsampling and voltage averaging is possible (only in the Xdirection).
Read out direction can be reversed in X and Y.
Multiple slope (up to 90 dB optical dynamic range).
The output rate of 66 Mpixels/s can be achieved with either 1 or 2
analog outputs.
2 on-chip 10-bit ADC’s @ 33 Msamples/s.
Nominal 2.5V (some supplies require 3.3V).
3.3V.
0°C to 60°C; with degradation of dark current.
Analog output
Digital output
Supply voltage VDD
Logic levels
Operational temperature range
Interface
Package
Power dissipation
Mass
Output amplifiers
External output load
Number of outputs
Serial-to Parallel Interface (SPI).
127 pin PGA package
<200mW
<100g
Differential
R > 10 kΩ
C < 20 pF (<10 pF is advised)
1 at 66 Mpixels/sec
2 at 33Mpixels/sec
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 9 of 49
LUPA-4000
Data Sheet
2.4 Electrical specifications
2.4.1 Recommended operating conditions
Table 4: Recommended operation conditions
Symbol
Parameter
Vaa
Power supply column read out
module.
Power supply column read out
module
Power supply digital modules
Power supply output stages
Power supply reset drivers
Power supply multiple slope reset
driver
Power supply memory element
(high level)
Power supply memory element
(low level)
Power supply pixel array
Power supply for Precharge offstate
Commercial operating
temperature.
Va3
Vdd
Voo
Vres
Vres_ds
Vmem_h
Vmem_l
Vpix
Vpre_l
TA
Min
Typ
Max
2.5
3.3
Unit
V
3.3
V
2.5
2.5
2.5
3.3
3.5
V
V
V
2.0
2.5
3.3
V
2.5
3.3
3.5
V
2.0
2.6
3.0
V
2.0
2.6
3.3
V
-0.4
0
0
V
0
30
60
°C
Note:
1. All parameters are characterized for DC conditions after thermal equilibrium
has been established.
2. Unused inputs must always be tied to an appropriate logic level, e.g. either
VDD or GND.
3. This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however it is recommended that normal
precautions be taken to avoid application of any voltages higher than the
maximum rated voltages to this high impedance circuit.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 10 of 49
LUPA-4000
Data Sheet
3 Sensor architecture
A schematic drawing of the architecture is given in the block diagram below. The
image core consists of a pixel array, one X- and two Y-addressing registers (only one
drawn), pixel array drivers and column amplifiers. The image sensor of 2048 * 2048
pixels is read out in progressive scan. One or two output amplifiers read out the
image sensor. The output amplifiers are working at 66MHz pixel rate nominal speed
or each at 33MHz pixel rate in case the 2 output amplifiers are used to read out the
imager. The complete image sensor has been designed for operation up to 66MHz.
The structure allows having a programmable addressing in the x-direction in steps of
2 and in the y-direction in steps of 2 (only even start addresses in X- and Y-direction
are possible). The starting point of the address is uploadable by means of the SerialParallel Interface (SPI).
On chip drivers
select drivers
y shift register
eos_y
Reset, mem_hl,
precharge, samp
pixel array
2048 * 2048
Column amplifiers
Clk_y sync_y
eos_x
X shift register
Clk_x
Logic blocks
SPI
DAC
2 differentia
outputs
sync_x
Figure 3: Block diagram of the image sensor
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 11 of 49
LUPA-4000
Data Sheet
3.1 The 6-T pixel
To obtain the global shutter feature combined with a high sensitivity and good
Parasitic Light Sensitivity (PLS), the pixel architecture given in the figure below is
implemented.
Vpix
Reset
Vmem
Sample
Row-Select
Figure 4: 6T-pixel architecture
This pixel architecture is designed in a 12 * 12 µm2 pixel pitch. The pixel is designed
to meet the specifications as described in Tables 1, 2 and 3.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 12 of 49
LUPA-4000
Data Sheet
3.2 Frame rate and windowing
3.2.1 Frame rate
To obtain a frame rate a 15 frames /sec, one needs 1 output amplifier, working at
66MHz pixel rate or 2 output amplifiers working at 33MHz each (assuming a Row
Overhead Time (ROT) of 200nsec).
The frame period of the LUPA-4000 sensor can be calculated as follows:
Frame period = FOT + (Nr. Lines * (ROT + pixel period * Nr. Pixels)
with: FOT: Frame Overhead Time = 5 us.
Nr. Lines: Number of Lines read out each frame (Y).
Nr. Pixels: Number of pixels read out each line (X).
ROT: Row Overhead Time = 200 ns (nominal; can be further reduced).
Pixel period: 1/66 MHz = 15.15 ns.
Example read out of the full resolution at nominal speed (66 MHz pixel rate):
Frame period = 5 us + (2048 * (200 ns + 15.15 ns * 2048) = 64 ms
=> 15 fps.
3.2.2 ROI read out (windowing)
Windowing can easily be achieved by a serial–parallel uploadable interface in which
the starting point of the x- and y-address is uploaded. This downloaded starting point
initiates the shift register in the x- and y-direction triggered by the Sync_x and Sync_y
pulse. The minimum step size for the x-address and the y-address is 2 (only even start
addresses can be chosen). The size of both address registers is 10 bits. When for
instance the addresses 0000000001 and 0000000001 are uploaded, the readout will
start at line 2 and column 2.
Table 5: Frame rate as function of ROI read out and/or sub sampling
Image Resolution
(X*Y)
2048 x 2048
1024 x 2048
1024 x 1024
640 x 480
Frame rate
[frames/s]
15
31
62
210
Frame readout
time [ms]
67
32
16
4.7
Comment
Full resolution.
Subsample in X-direction.
ROI read out.
ROI read out.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 13 of 49
LUPA-4000
Data Sheet
3.3 Output amplifier
1 output amplifier working at 66Mpixels/sec is required to bring the whole pixel array
of 2048 by 2048 pixels at the required frame rate to the outside world. A second
output stage is also foreseen to convert the analog data on-chip by 2 10-bit ADC’s
each working at 33 MHz. By having a second output stage working in parallel, the
pixel rate can be more relaxed to 33MHz for both output amplifiers. Using only one
output-stage, the output signal will be the result of multiplexing between the 2 internal
buses. When using 2 output-stages, both outputs will be in phase.
Each output-stage has 2 outputs. One output is the pixel signal; the second output is a
DC signal which offset can be programmed using a 7-bit word. The DC signal can be
used for common mode rejection between the 2 signals. The disadvantage is an
increase in power dissipation however this can be reduced by setting the highest DAC
voltage by means of the SPI.
Image sensor
Out1: Pixel signal
7bits
SPI
DAC
Out2: dc signal
Figure 5: Output stage architecture
The output voltage of Out1 will be between 1.3V (dark level) and 0.3V (white level)
and depends on process variations and voltage supply settings. The output voltage of
Out2 is determined by the DAC.
3.4 Pixel array drivers
We have foreseen on this image sensor on chip drivers for the pixel array signals. Not
only the driving on system level is easy and flexible, also the maximum currents
applied to the sensor are controlled on chip. This means that the charging on sensor
level is fixed and that the sensor cannot be overdriven from externally. In the
paragraph on the timing, the operation of the on-chip drivers is explained more in
detail.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 14 of 49
LUPA-4000
Data Sheet
3.5 Column amplifiers
The column amplifiers are designed for minimum power dissipation and minimum
loss of signal for this reason multiple biasing signals are needed.
The column amplifiers also have the “voltage-averaging” feature integrated. In case
of voltage averaging mode, the voltage average between 2 columns is taken and read
out. In this mode only 2:1 pixels have to be read out.
To achieve the voltage-averaging mode, an additional external digital signal called
“voltage-averaging” is required in combination with a bit from the SPI.
3.6 Analog to Digital Converter
The LUPA4000 has a two 10 bit flash analog digital converters running nominally at
33 Msamples/s. The ADC’s are electrically separated from the image sensor. The
inputs of the ADC should be tied externally to the outputs of the output amplifiers.
One ADC will sample the even columns and the other one will sample the odd
columns. Although the input range of the ADC is between 1V and 2V and the output
range of the analog signal is only between 0.3V and 1.3V, the analog output and
digital input may be tied to each other directly. This is possible because there is an on
chip level-shifter located in front of the ADC to lift up the analog signal to the ADC
range.
Table 6: ADC specifications
Parameter
Specification
Input range
Quantization
Nominal data rate
DNL (linear conversion mode)
INL (linear conversion mode)
Input capacitance
Power dissipation @ 33 MHz
Conversion law
1 – 2V (*)
10 Bits
33 Msamples/s
Typ. < 0.4LSB RMS
Typ. < 3.5 LSB
< 2 pF
50 mW
Linear / Gamma-corrected
(*): The internal ADC range will be typ. 50mV lower then the external applied
ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal
resistors in the ADC.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 15 of 49
LUPA-4000
Data Sheet
3.6.1 ADC timing
The ADC converts the pixel data on the falling edge of the ADC_CLOCK but it takes 2
clock cycles before this pixel data is at the output of the ADC. This pipeline delay is
shown in Figure 6.
Figure 6: ADC timing
3.6.2 Setting of the ADC reference voltages
2.5V
RHIGH_ADC
REF_HIGH ~ 2 V
external
internal
RADC
REF_LOW ~ 1 V
external
RLOW_ADC
Figure 7: In- and external ADC connections
The internal resistor RADC has a value of approximately 300 Ω.
This results in the values for the external resistors:
Resistor
Value (Ω)
RADC_VHIGH
RADC
RADC_VLOW
75
300
220
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 16 of 49
LUPA-4000
Data Sheet
The values of the resistors depend on the value of RADC. The voltage difference
between ADC_VLOW and ADC_VHIGH should be at least 1.0V to assure proper
working of the ADC.
3.7 Synchronous shutter
In a synchronous (snapshot) shutter light integration takes place on all pixels in
parallel, although subsequent readout is sequential.
COMMON SAMPLE&HOLD
Flash could occur here
COMMON RESET
Line number
Time axis
Integration time
Burst Readout time
Figure 8: Synchronous shutter operation
Figure 8 shows the integration and read out sequence for the synchronous shutter. All
pixels are light sensitive at the same period of time. The whole pixel core is reset
simultaneously and after the integration time all pixel values are sampled together on
the storage node inside each pixel. The pixel core is read out line by line after
integration. Note that the integration and read out cycle can occur in parallel or in
sequential mode. (ref. 4. Timing and read out of the image sensor)
3.8 Non-destructive readout (NDR)
The sensor can also be read out in a non-destructive way. After a pixel is initially
reset, it can be read multiple times, without resetting. The initial reset level and all
intermediate signals can be recorded. High light levels will saturate the pixels
quickly, but a useful signal is obtained from the early samples. For low light levels,
one has to use the later or latest samples.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 17 of 49
LUPA-4000
Data Sheet
time
Figure 9. Principle of non-destructive readout.
Essentially an active pixel array is read multiple times, and reset only once. The
external system intelligence takes care of the interpretation of the data. Table 7
summarizes the advantages and disadvantages of non-destructive readout.
Table 7: Advantages and disadvantages of non-destructive readout.
Advantages
Low noise – as it is true CDS.
Disadvantages
System memory required to record the
reset level and the intermediate samples.
High sensitivity – as the conversion Requires multiples readings of each pixel,
capacitance is kept rather low.
thus higher data throughput.
High dynamic range – as the results Requires system level digital calculations.
includes signal for short and long
integrations times.
3.9 Operation and signalling
One can distinguish the different signals into different groups:
• Power supplies and grounds
• Biasing and Analog signals
• Pixel array signals
• Digital signals
• Test signals
3.9.1 Power supplies and ground
Every module on chip, as there are: column amplifiers, output stages, digital modules,
drivers… has its own power supply and ground. Off chip the grounds can be
combined, but not all power supplies may be combined. This results in several
different power supplies, but this is required to reduce electrical cross-talk and to
improve shielding, dynamic range and output swing.
On chip we have the ground lines of every module which are kept separately to
improve shielding and electrical cross talk between them.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 18 of 49
LUPA-4000
Data Sheet
An overview of the supplies is given in table 8 and 9. Table 9 summarizes the
supplies related to the pixel array signals, where table 8 summarizes the supplies
related with all other modules.
Table 8: Power supplies
Name
Vaa
DC Current
7mA
Max.current
50mA
Typ.
2.5V
Max.
Va3
10mA
50mA
3.3V
3.3V
Vdd
Voo
Vdda
Vddd
1mA
20mA
1mA
1mA
200mA
20mA
200mA
200mA
2.5V
2.5V
2.5V
2.5V
Description
Power supply column readout
module.
Power supply column readout
module. Should be tuneable to 3.3V
max.
Power supply digital modules
Power supply output stages
Analog supply of ADC circuitry
Digital supply of ADC circuitry
Table 9: Overview of the power supplies related to the pixel signals
Name
Max.
current
200mA
200mA
Min.
Typ.
Max.
Description
Vres
Vres_ds
DC
current
1mA
1mA
2.5V
2.0V
3.3V
2.5V
3.5V
3.3V
Vmem_h
1mA
200mA
2.5V
3.3V
3.5V
Vmem_l
1mA
200mA
2.0V
2.5 V
3.0V
Vdd
Vpix
1mA
12mA
200mA
500mA
2.0V
2.0V
2.5V
2.5V
3.0V
3.3V
Vpre_l
1mA
200mA
-400mV
0V
0V
Power supply reset drivers.
Power supply dual slope reset
drivers.
Power supply memory elements in
pixel for high voltage level
Power supply memory elements in
pixel for low voltage level. Should
be tuneable
Power supply for Sample
Power supply pixel array. Should
be tuneable to 3.3V
Power supply for Precharge in
off-stat. May be connected to
ground.
The maximum currents mentioned in table 8 and 9 are peak currents which occur once
per frame (except for Vres_ds in multiple slope mode). All power supplies should be
able to deliver these currents except for Vmem_l and Vpre_l, which must be able to
sink this current.
The maximum peak current for Vpix should not be higher than 500mA. It is important
to notice that no power supply filtering on chip is implemented and that noise on these
power supplies can contribute immediately to the noise on the signal. Especially the
voltage supplies Vpix and Vaa are important to be well noise free.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 19 of 49
LUPA-4000
Data Sheet
3.9.2 Start-up sequence
The LUPA-4000 will go in latch up (draw high current) as soon as all power supplies
are turned on at the same time. The sensor will come out of latch-up and start working
normally as soon as it is being clocked. A power supply with a 400 mA limit is
recommended to avoid damage to the sensor. It is recommended to avoid the time that
the device is in the latch-up state, so clocking of the sensor should start as soon as
possible (i.e. as soon as the system is turned on).
In order to completely avoid latch-up of the image sensor, the next sequence should
be taken into account:
o Apply Vdd
o Apply clocks and digital pulses to the sensor
o Count 2048 clock_x and 2048 clock_y pulses to empty the shift
registers
o Apply other supplies
3.9.3 Biasing and analog signals
The analog output levels that may be expected are between 0.3V for a white,
saturated, pixel and 1.3V for a black pixel.
2 Output stages are foreseen, each consisting of 2 output amplifiers, resulting in 4
outputs. 1 Output amplifier is used for the analog signal resulting from the pixels.
The second amplifier is used for a dc reference signal. The dc-level from the buffer is
defined by a DAC, which is controlled by a 7-bit word downloaded in the SPI.
Additionally, an extra bit in the SPI defines if 1 output or the 2 output stages are used.
Table 10 summarizes the biasing signals required to drive this image sensor. For
optimisation reasons of the biasing of the column amplifiers with respect to power
dissipation, we need several biasing resistors. This optimisation results in an increase
of signal swing and dynamic range.
Table 10: Overview of bias signals
Signal
Out_load
dec_x_load
muxbus_load
nsf_load
Comment
Connect with 60 KΩ to
Voo and capacitor of
100 nF to Gnd
Connect with 2 MΩ to
Vdd and capacitor of
100 nF to Gnd
Connect with 25 KΩ to
Vaa and capacitor of
100 nF to Gnd
Connect with 5 KΩ to
Vaa and capacitor of
100 nF to Gnd
Related module
DC-level
Output stage
0.7 V
X-addressing
0.4 V
Multiplex bus
0.8 V
Column amplifiers
1.2 V
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 20 of 49
LUPA-4000
Data Sheet
Signal
uni_load_fast
uni_load
pre_load
col_load
dec_y_load
psf_load
precharge_bias
Comment
Connect with 10KΩ to
Vaa and capacitor of
100 nF to Gnd
Connect with 1MΩ to
Vaa and capacitor of
100 nF to Gnd
Connect with 3 KΩ to
Vaa and capacitor of
100 nF to Gnd
Connect with 1 MΩ to
Vaa and capacitor of
100 nF to Gnd
Connect with 2 MΩ to
Vdd and capacitor of
100 nF to Gnd
Connect with 1 MΩ to
Vaa and capacitor of
100 nF to Gnd
Connect with 1kΩ to
Vdd and capacitor of at
least 200nF to Gnd.
Related module
DC-level
Column amplifiers
1.2 V
Column amplifiers
0.5 V
Column amplifiers
0.6 V
Column amplifiers
0.5 V
Y-addressing
0.4 V
Column amplifiers
0.5 V
Pixel drivers
1.4V
Each biasing signal determines the operation of a corresponding module in the sense
that it controls speed and dissipation. Some modules have 2 biasing resistors: one to
achieve the high speed and another to minimize power dissipation.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 21 of 49
LUPA-4000
Data Sheet
3.10 Pixel array signals
The Pixel array of the image sensor requires digital control signals and several
different power supplies. This paragraph explains the relation between the control
signals and the applied supplies and the internal generated pixel array signals.
From figure 9 one can see that the internal generated pixel array signals are Reset,
Sample, Precharge, Vmem and Row_select. These are internal generated signals
derived by on chip drivers from external applied signals. Row_select is generated by
the y addressing and will not be discussed in this paragraph.
The function of each of the signals is:
Reset: Resets the pixel and initiates the integration time. If reset is high than the
photodiode is forced to a certain voltage, depending on Vpix, which is the pixel
supply; and depending on the high level of reset signal. The higher these signals or
supplies are, the higher the voltage-swing. The limitation on the high level of Reset
and Vpix is 3.3V. Nevertheless, it has no sense increasing Vpix without increasing
the reset level. The opposite does make sense. Additionally, it is this reset pulse that
also controls the dual or multiple slope feature inside the pixel. By giving a reset
pulse during integration, but not at full reset level, the photodiode is reset to a new
value, only if his value is sufficient decreased due to light illumination.
The low level of reset is 0V, but the high level is 2.5V or higher (3.3V) for the normal
reset and a lower (<2.5V) level for the multiple slope reset.
Precharge: Precharge serves as a load for the first source follower in the pixel and is
activated to overwrite the current information on the storage node by the new
information on the photodiode. Precharge is controlled by an external digital signal
between 0 and 2.5V.
Sample: Samples the photodiode information onto the memory element. This signal
is also a standard digital level between 0 and 2.5V
Vmem: this signal increases the information on the memory element with a certain
offset. This way one can increase the output voltage variation. Vmem changes
between Vmem_l (2.5V) and Vmem_h (3.3V).
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 22 of 49
LUPA-4000
Data Sheet
Figure 10: Internal timing of the pixel. Levels are defined by the pixel array voltage supplies (For
the correct polarities of the signals refer to table 11).
The signals in figure 10 are generated from the on chip drivers. These on chip drivers
need 2 types of signals to generate the exact type of signal. It needs digital control
signals between 0 and 3.3V (internally converted to 2.5V) with normal driving
capability and power supplies. The control signals are required to indicate the
moment they need to occur and the power supplies indicate the level.
Vmem is made of a control signal Mem_hl and 2 supplies Vmem_h and Vmem_l. If
the signal Mem_hl is the logic “0” than the internal signal Vmem is low, if Mem_hl is
logic “1” the internal signal Vmem is high.
Reset is made by means of 2 control signals: Reset and Reset_ds and 2 supplies: Vres
and Vres_ds. Depending on the signal that becomes active, the corresponding supply
level is applied to the pixel.
Table 11 summarizes the relation between the internal and external pixel array
signals.
Table 11: Overview of the in- and external pixel array signals
Internal Signal
Vlow
Vhigh
Precharge
0
0.45V
Sample
0
2.5V
Reset
0
2.5 – 3.3V
Vmem
2.0– 2.5V
2.5-3.3V
External
control signal
Precharge
(AL)
Sample (AL)
Reset (AH) &
Reset_ds (AH)
Mem_hl (AL)
Low DClevel
Vpre_l
Gnd
Gnd
Vmem_l
High DC-level
Controlled by
bias-resistor
Vdd
Vres &
Vres_ds
Vmem_h
AH: Active High
AL: Active Low
In case the dual slope operation is desired, one needs to give a second reset pulse to a
lower reset level during integration. This can be done by the control signal Reset_ds
and by the power supply Vres_ds that defines the level to which the pixel has to be
reset.
Note that Reset is dominant over Reset_ds, which means that the high voltage level
will be applied for reset, if both pulses occur at the same time.
Note that multiple slopes are possible having multiple Reset_ds pulses with a lower
Vres_ds level for each pulse given within the same integration time.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 23 of 49
LUPA-4000
Data Sheet
The rise and fall times of the internal generated signals are not very fast (200nsec). In
fact they are made rather slow to limit the maximum current through the power supply
lines (Vmem_h, Vmem_l, Vres, Vres_ds, Vdd). Current limitation of those power
supplies is not required. Nevertheless, it is advisable to limit the currents not higher
than 400mA.
The power supply Vmem_l must be able to sink this current because it must be able to
discharge the internal capacitance from the level Vmem_h to the level Vmem_l. The
external control signals should be capable of driving input capacitance of about 10pF.
3.10.1 Digital signals
The digital signals control the readout of the image sensor. These signals are:
• Sync_y (AH): Starts the readout of the frame. This pulse synchronises the yaddress register: active high. This signal is at the same time the end of the
frame or window and determines the window width.
• Clock_y (AH): Clock of the y-register. On the rising edge of this clock, the
next line is selected.
• Sync_x (AH): Starts the readout of the selected line at the address defined by
the x-address register. This pulse synchronises the x-address register: active
high. This signal is at the same time the end of the line and determines the
window length.
• Clock_x (AH): Determines the pixel rate. A clock of 33MHz is required to
achieve a pixel rate of 66MHz.
• Spi_data (AH): the data for the SPI
• Spi_clock (AH): clock of the serial parallel interface. This clock downloads
the data into the SPI register.
• Spi_load (AH): when the SPI register is uploaded, then the data will be
internally available on the rising edge of SPI_load
• Sh_kol (AL): control signal of the column readout. Is used in sample & hold
mode and in binning mode
• Norowsel (AH): Control signal of the column readout. (See timing)
• Pre_col (AL): Control signal of the column readout to reduce row blanking
time
• Voltage averaging (AH): Signal required obtaining voltage averaging of 2
pixels.
3.10.2 Test signals
The test structures implemented in this image sensor are:
• Array of pixels (6*12) which outputs are tied together: used for spectral
response measurement.
• Temperature diode (2): Apply a forward current of 10-100µA and measure the
voltage VT of the diode. VT varies linear with the temperature (VT decreases
with approximately 1,6 mV/°C).
• End of scan pulses (do not use to trigger other signals):
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 24 of 49
LUPA-4000
Data Sheet
o Eos_x: end of scan signal: is an output signal, indicating when the end
of the line is reached. Is not generated when doing windowing
o Eos_y: end of scan signal: is an output signal, indicating when the end
of the frame is reached. Is not generated when doing windowing.
o Eos_spi: output signal of the SPI to check if the data is transferred
correctly through the SPI.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 25 of 49
LUPA-4000
Data Sheet
4 Timing and read out of the image sensor
The timing of the LUPA-4000 sensor consists of 2 parts. The first part is related with
the control of the pixels, the integration time and the signal level. The second part is
related with the readout of the image sensor. As this image sensor is able for full
synchronous shutter, integration time and readout can be in parallel or sequential.
In the parallel mode the integration time of the frame I is ongoing during readout of
frame I-1. Figure 11 shows this parallel timing structure.
.
Read frame I
Read frame I + 1
Integration I + 1
Integration I + 2
Figure 11:Integration and read out in parallel
The control of the readout of the frame and of the integration time are independent of
each other with the only exception that the end of the integration time from frame I+1
is the beginning of the readout of frame I+1.
The LUPA-4000 sensor also can be used in sequential mode (triggered snapshot
mode) where readout and integration will be sequentially. Figure 12 shows this
sequential timing sequence.
Integration I
Read frame I
Integration I +1
Read frame I +1
Figure 12: Integration and readout sequentially
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 26 of 49
LUPA-4000
Data Sheet
4.1 Timing of the pixel array
The first part of the timing is related with the timing of the pixel array. This implies
the control of the integration time, the synchronous shutter operation and the sampling
of the pixel information onto the memory element inside each pixel. The signals
needed for this control are described in the previous paragraph 3.9 and in figure 10.
Figure 13 shows the external applied signals required to control the pixel array. At
the end of the integration time from frame I+1, the signals Mem_hl, Precharge and
Sample have to be given. The reset signal controls the integration time, which is
defined as the time between the falling edge of reset and the rising edge of sample.
Figure 13: Timing of the pixel array: The integration time is determined by the falling edge of the
reset pulse. The longer the pulse is high, the shorter the integration time. At the end of the integration
time, the information has to be stored onto the memory element for readout.
Timing specifications for each signal are:
Symbol
Table 12: Timing specifications
Name
Value
a
Mem_HL
b
Precharge
Sample
Precharge-Sample
Integration time
c
d
e
5 – 8,2
µsec
3 – 6 µsec
5 – 8 µsec
> 2 µsec
> 1 µsec
Falling edge of Precharge is equal or later than falling edge of Vmem.
Sample is overlapping with precharge.
Rising edge of Vmem is more than 200nsec after rising edge of Sample.
Rising edge of reset is equal or later than rising edge of Vmem.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 27 of 49
LUPA-4000
Data Sheet
The timing of the pixel array is straightforward. Before the frame is read, the
information on the photodiode needs to be stored onto the memory element inside the
pixels. This is done by means of the signals Mem_hl, Precharge and Sample. When
precharge is activated it serves as a load for the first source follower in the pixel.
Sample stores the photodiode information onto the memory element. Mem_hl pumps
up this value to reduce the loss of signal in the pixel and this signal must be the
envelop of Precharge and Sample. After Mem_hl is high again, the readout of the
pixel array can start. The frame blanking time or frame overhead time is thus the time
that Mem_hl is low, which is about 5µsec. Once the readout starts, the photodiodes
can all be initialised by reset for the next integration time. The minimal integration
time is the minimal time between the falling edge of reset and the rising edge of
sample. Keeping the slow fall times of the corresponding internal generated signals in
mind, the minimal integration time is about 2 µsec.
An additional reset pulse of minimum 2 µsec can be given during integration by
asserting Reset_ds to implement the double slope integration mode.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 28 of 49
LUPA-4000
Data Sheet
4.2 Read out of the image sensor
As soon as the information of the pixels is stored in to the memory element of each
pixel, this information can be readout sequentially. As seen in the previous section,
integration and readout can also be done in parallel.
The readout timing is straightforward and is basically controlled by means of sync
and clock pulses.
Figure 14 shows the top level concept of this timing. The readout of a frame consists
of the frame overhead time, the selection of the lines sequentially and the readout of
the pixels of the selected line.
Read frame I
Integration I + 2
Readout Lines
F.O.T
L1
L2
L3
L2048
Readout pixels
R.O.T
C1
C2
C2048
Figure 14: Readout of the image sensor. F.O.T: Frame overhead time. R.O.T: Row overhead time.
L: selection of line, C: Selection of column.
The readout of an image consists of the FOT (Frame overhead time) and the
sequential selection of all pixels. The FOT is the overhead time between 2 frames to
transfer the information on the photodiode to the memory elements. From figure 13 it
should be clear that this time is the time that Mem_hl is low (typically 5 µs). After
the FOT the information is stored into the memory elements and a sequential selection
of rows and columns makes sure the frame is read.
4.2.1 X- and Y-addressing
To readout a frame the lines are selected sequentially. Figure 15 gives the timing to
select the lines sequentially. This is done by means of a Clock_y and a Sync_y signal.
The Sync_y signals synchronises the y-addressing and initialises the y-address
selection registers. The start address is the address downloaded in the SPI multiplied
by 2.
On the rising edge of Clock_y the next line is selected. The Sync_y signal is
dominant and from the moment it occurs the y-address registers are initialised. If a
Sync_y pulse is given before the end of the frame is reached, only a part of the frame
will be read. To obtain a correct initialisation Sync_y must contain at least 1 rising
edge of Clock_y when it is active.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 29 of 49
LUPA-4000
Data Sheet
Figure 15: X- and Y-addressing
Table 13: Read-out timing specifications
Symbol
Name
Value
Sync_Y
>20ns
a
Sync_Y-Clock_Y
>0ns
b
Clock_Y-Sync_Y
>0ns
c
NoRowSel
>50ns
d
Pre_col
>50ns
e
200ns (more
information
on this timing
Sh_col
f
can be found
in section
4.2.2.a)
Voltage averaging
>20ns
g
Sync_X-Clock_X
>0ns
h
As soon as a new line is selected, it has to be read out by the output amplifiers.
Before the pixels of the selected line can be multiplexed onto the output amplifiers,
one has to wait a certain time, indicated as the ROT or Row overhead time shown in
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 30 of 49
LUPA-4000
Data Sheet
figure 15. This is the time to get the data stable from the pixels to the output bus
before the output stages. This ROT is in fact lost time and rather critical in a highspeed sensor. Different timings to reduce this ROT are explained in next paragraph.
During the selection of 1 line, 2048 pixels are selected. These 2048 pixels have to be
readout by 1 (or 2) output amplifier.
Please note that the pixel rate is the double frequency of the Clock_x frequency. To
obtain a pixel rate of 66 MHz, one needs to apply a pixel clock Clock_x of 33MHz.
When only 1 analog output is used 2 pixels are output every Clock_x period. When
Clock_x is high, the first pixel is selected, when Clock_x is low, the next pixel is
selected. Consequently, during 1 complete period of Clock_x 2 pixels are readout by
the output amplifier.
If 2 analog outputs are used each Clock-X period 1 pixel is presented at each output.
Figure 16: X-addressing. From bottom to top: Clock_x, Sync_x, internal selection pixel 1&2, internal
selection pixel 3&4, internal selection pixel 5 & 6.
The first pixel that is selected is the x-address downloaded in the SPI. The starting
address is the number downloaded into the SPI, multiplied with 2.
Windowing is achieved by a starting address downloaded in the SPI and the size of
the window. In the x-direction, the size is determined by the moment a new Clock_y
is given. In the y-direction, the sync_y pulse determines the size. Consequently, the
best way to obtain a certain window is by using an internal counter in the controller.
Figure 16 is the simulation result after extraction of the layout module from a
different sensor to show the principle. In this figure the pixel clock has a frequency of
50MHz, which would result in a pixel rate of 100 Msamples/sec.
Figure 17 shows the relation between the applied Clock_x and the output signal.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 31 of 49
LUPA-4000
Data Sheet
Pixel 1
Pixel2….: Pixel period : 20nsec
saturated
Output 1
dark
Sync_x
Clock_x:
25MHz
Figure 17: output signal related to Clock_x signal. From bottom to top: Clock_x, Sync_x and output.
The output level before the first pixel is the level of the last pixel of previous line.
As soon as Sync_x is high and 1 rising edge of Clock_x occurs, the pixels are brought
to the analog outputs. This is again the simulation result of a comparable sensor to
show the principle.
Please note there is a time difference between the clock edge and the moment the data
is seen at the output. As this time difference is very difficult to predict in advance, it
is advisable to have the ADC sampling clock flexible to set an optimal Adc sampling
point. The time differences can easily vary between 5 – 15nsec and have to be tested
on the real devices.
4.2.2 Reduced Row Overhead Time timing
The row overhead time is the time between the selection of lines that one has to wait
to get the data stable at the column amplifiers.
This row overhead time is a loss in time, which should be reduced as much as
possible.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 32 of 49
LUPA-4000
Data Sheet
4.2.2.a
Standard timing (200ns)
Figure 18: Standard timing for the R.O.T. Only pre_col and Norowsel control signals are required.
In this case the control signals Norowsel and pre_col are made active for about 20nsec
from the moment the next line is selected. The time these pulses have to be active is
related with the biasing resistance Pre_load. The lower this resistance, the shorter the
pulse duration of Norowsel and pre_col may be. After these pulses are given, one has
to wait for at least 180nsec before the first pixels can be sampled. For this mode
Sh_col must be made active all the time.
4.2.2.b
Back-up timing (ROT =100-200 ns)
A straightforward way of reducing the R.O.T is by using a sample and hold function.
By means of Sh_col the analog data is tracked during the first 100nsec during the
selection of a new set of lines. After 100nsec, the analog data is stored. The ROT is
in this case reduced to 100nsec, but as the internal data was not stable yet dynamic
range is lost because not the complete analog levels are reached yet after 100ns.
Figure 18 shows this principle. Sh_col is now a pulse of 100ns-200ns starting at the
same moment as pre_col and Norowsel. The duration of Sh_col is equal to the ROT.
The shorter this time the shorter the ROT will be however this lowers also the
dynamic range.
In case “voltage averaging” is required, the sensor must work in this mode with
Sh_col signal and a “voltage averaging” signal must be generated after Sh_col drops
and before the readout starts (see figure 15).
Figure 19: Reduced standard ROT by means of Sh_col signal. pre_col (short pulse) , Norowsel (short
pulse) and Sh_col (large pulse).
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 33 of 49
LUPA-4000
Data Sheet
4.2.3 Precharging of the buses
This timing mode is exactly the same as the mode without sample and hold, except
that the prebus1 and prebus2 signals are activated. It should be noticed that the
precharging of the buses can be combined with all of the timing modes discussed
above. The idea is to have a short pulse of about 5ns to precharge the output buses to
a well-known level. This mode makes the ghosting of bad columns impossible.
In this mode, Nsf_load must be made much larger (at least 1Mohms).
Figure 20: X- and Y-addressing with precharging of the buses
Table 14: Read-out timing specifications with precharching of the buses
Symbol
Name
Value
Sync_Y
>20ns
a
Sync_Y-Clock_Y
>0ns
b
Clock_Y-Sync_Y
>0ns
c
NoRowSel
>50ns
d
Pre_col
>50ns
e
200ns (or cst
high,
Sh_col
f
depending on
timing mode)
Voltage averaging
>20ns
g
Sync_X-Clock_X
>0ns
h
As short as
Prebus pulse
i
possible
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 34 of 49
LUPA-4000
Data Sheet
4.3 Serial-Parallel-Interface (SPI)
The SPI is required to upload the different modes. Table 15 shows the parameters and
there bit position
Table 15: SPI parameters
Parameter
Y-direction
Y-address
X-voltage averaging enable
X-subsampling
X-direction
X-address
Nr output amplifiers
DAC
Bit nr.
Remarks
1: from bottom to top
Bit 1 is LSB
1: Enabled
1: Subsampling
0: From left to right
Bit 14 is LSB
0: 1 Output
Bit 25 is LSB
0
1-10
11
12
13
14-23
24
25-31
When all zeros are loaded into the SPI, the sensor will start at pixel 0,0. The scanning
will be from left to right and from top to bottom. There will be no sub-sampling or
voltage averaging and only one output is used. The DAC will have the lowest level at
its output.
When using sub sampling, only even X-addresses may be applied.
To sensor
D
Load_addr
32 outputs to sensor
Bit 31
spi_in
Q
Clock_spi
C
Entire uploadable block
Load_addr
Spi_in
D
Clock_spi
Bit 0
Q
C
Unity Ce ll
Clock_spi
spi_in
B0
B1
B2
Load_addr
B31
command
applied to
sensor
Figure 20: SPI block diagram and timing
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 35 of 49
LUPA-4000
Data Sheet
5 Pin list
Table 16 is a list of all the pins and their functionalities.
Table 16: Pin list
Pad
Pin
E1
F1
D2
G2
Pin Name
1
2
3
4
sync_x
eos_x
vdd
clock_x
Pin Type
Input
Testpin
Supply
Input
5
G1
eos_spi
Testpin
6
7
8
9
10
11
12
13
14
15
16
17
18
19
F2
H1
H2
J2
J1
K1
M2
L1
M1
N2
P1
P2
N1
P3
spi_data
spi_load
spi_clock
gndo
out2
out2DC
voo
out1DC
out1
gndo
vaa
gnda
va3
vpix
Input
Input
Input
Ground
Output
Output
Supply
Output
Output
Ground
Supply
Ground
Supply
Supply
20
Q1
psf_load
Input
21
Q2
nsf_load
Input
22
R1
muxbus_load
Input
23
R2
uni_load_fast
Input
24
Q3
pre_load
Input
25
Q4
out_load
Input
26
N3
dec_x_load
Input
27
Q5
uni_load
Input
28
Q6
col_load
Input
Description
Digital input. Synchronises the X-address register.
Indicates when the end of the line is reached.
Power supply digital modules.
Digital input. Determines the pixel rate.
Checks if the data is transferred correctly through the
SPI.
Digital input. Data for the SPI.
Digital input. Loads data into the SPI.
Digital input. Clock for the SPI.
Ground output stages
Analog output 2.
Reference output 2.
Power supply output stages
Reference output 1.
Analog output 1.
Ground output stages.
Power supply analog modules.
Ground analog modules.
Power supply column modules.
Power supply pixel array.
Analog reference input. Biasing for column modules.
Connect with R=1MΩ to Vaa and decouple with
C=100nF to gnda.
Analog reference input. Biasing for column modules.
Connect with R=5kΩ to Vaa and decouple with
C=100nF to gnda.
Analog reference input. Biasing for multiplex bus.
Connect with R=25kΩ to Vaa and decouple with
C=100nF to gnda.
Analog reference input. Biasing for column modules.
Connect with R=10kΩ to Vaa and decouple with
C=100nF to gnda.
Analog reference input. Biasing for column modules.
Connect with R=3kΩ to Vaa and decouple with
C=100nF to gnda.
Analog reference input. Biasing for output stage.
Connect with R=60kΩ to Vaa and decouple with
C=100nF to gnda.
Analog reference input. Biasing for X-addressing.
Connect with R=2MΩ to Vdd and decouple with
C=100nF to gndd.
Analog reference input. Biasing for column modules.
Connect with R=1MΩ to Vaa and decouple with
C=100nF to gnda.
Analog reference input. Biasing for column modules.
Connect with R=1MΩ to Vaa and decouple with
C=100nF to gnda.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 36 of 49
LUPA-4000
Data Sheet
Pad
Pin
Pin Name
Pin Type
29
Q7
dec_y_load
Input
30
31
32
33
34
R3
M3
L2
L3
Q8
vdd
gndd
prebus1
prebus2
sh_col
Supply
Ground
Input
Input
Input
35
R4
pre_col
Input
36
37
38
R5
R6
R7
norowsel
clock_y
sync_y
Input
Input
Input
39
K2
eos_y_r
Testpin
40
41
42
43
44
45
46
Q9
Q10
R8
R9
R10
R11
Q11
temp_diode_p
temp_diode_n
vpix
vmem_l
vmem_h
vres
vres_ds
Testpin
Testpin
Supply
Supply
Supply
Supply
Supply
47
R12
ref_low
Input
48
Q12
linear_conv
Input
49
bit_9
63
P15
Q14
Q15
R13
R14
R15
P14
Q13
R16
Q16
P16
N14
N15
L16
L15
vdda
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Supply
Supply
Supply
Supply
64
N16
bit_inv
Input
65
M16
CMD_SS
Input
66
L14
analog_in
Input
67
M15
CMD_FS
Input
50
51
52
53
54
55
56
57
58
59
60
61
62
bit_8
bit_7
bit_6
bit_5
bit_4
bit_3
bit_2
bit_1
bit_0
clock
gndd
vddd
gnda
Description
Analog reference input. Biasing for Y-addressing.
Connect with R=2MΩ to Vdd and decouple with
C=100nF to gndd.
Power supply digital modules.
Ground digital modules.
Digital input. Control signal to reduce readout time.
Digital input. Control signal to reduce readout time.
Digital input. Control signal of the column readout.
Digital input. Control signal of the column readout to
reduce row-blanking time.
Digital input. Control signal of the column readout.
Digital input. Clock of the Y-addressing.
Digital input. Synchronises the Y-address register.
Indicates when the end of frame is reached when
scanning in the ‘right’ direction.
Anode of temperature diode.
Cathode of temperature diode.
Power supply pixel array.
Power supply Vmem drivers.
Power supply Vmem drivers.
Power supply reset drivers.
Power supply reset drivers.
Analog reference input. Low reference voltage of ADC.
(see figure 7 for exact resistor value)
Digital input. 0= linear conversion; 1= gamma
correction.
Digital output 1 <9> (MSB).
Digital output 1 <8>.
Digital output 1 <7>.
Digital output 1 <6>.
Digital output 1 <5>.
Digital output 1 <4>.
Digital output 1 <3>.
Digital output 1 <2>.
Digital output 1 <1>.
Digital output 1 <0> (LSB).
ADC clock input.
Digital GND of ADC circuitry.
Digital supply of ADC circuitry (nominal 2.5V).
Analog GND of ADC circuitry.
Analog supply of ADC circuitry (nominal 2.5V).
Digital input. 0=no inversion of output bits; 1 =
inversion of output bits.
Analog reference input. Biasing of second stage of ADC.
Connect to VDDA with R=50kΩ and decouple with
C=100 nF to GNDa.
Analog input of 1st ADC.
Analog reference input. Biasing of first stage of ADC.
Connect to VDDA with R=50kΩ and decouple with
C=100 nF to GNDa.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 37 of 49
LUPA-4000
Data Sheet
Pad
Pin
Pin Name
Pin Type
68
M14
ref_high
Input
69
70
K14
J14
vres_ds
vres
Supply
Supply
71
J15
vpre_l
Supply
72
73
74
J16
K15
K16
vdd
vmem_h
vmem_l
Supply
Supply
Supply
75
H15
ref_low
Input
76
H16
linear_conv
Input
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
G16
F16
E16
G15
G14
F14
E14
D16
E15
F15
D15
C15
D14
B16
B14
bit_9
bit_8
bit_7
bit_6
bit_5
bit_4
bit_3
bit_2
bit_1
bit_0
clock
gndd
vddd
gnda
vdda
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Supply
Supply
Supply
Supply
92
C16
bit_inv
Input
93
A16
CMD_SS
Input
94
B15
analog_in
Input
95
A15
CMD_FS
Input
96
A14
ref_high
Input
97
98
99
100
101
102
103
104
105
106
107
108
C14
B13
A13
A9
A10
A11
A12
B7
B8
B9
B10
B11
vres_ds
vres
vmem_h
vmem_l
vpix
reset
reset_ds
mem_hl
precharge
sample
temp_diode_n
temp_diode_p
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Testpin
Testpin
Description
Analog reference input. High reference voltage of ADC.
(see figure 7 for exact resistor value)
Power supply reset drivers.
Power supply reset drivers.
Power supply precharge drivers. Must be able to sink
current. Can also be connected to ground.
Power supply digital modules.
Power supply Vmem drivers.
Power supply Vmem drivers.
Analog reference input. Low reference voltage of ADC.
(see figure 7 for exact resistor value)
Digital input. 0= linear conversion; 1= gamma
correction.
Digital output 2 <9> (MSB).
Digital output 2 <8>.
Digital output 2 <7>.
Digital output 2 <6>.
Digital output 2 <5>.
Digital output 2 <4>.
Digital output 2 <3>.
Digital output 2 <2>.
Digital output 2 <1>.
Digital output 2 <0> (LSB).
ADC clock input.
Digital GND of ADC circuitry.
Digital supply of ADC circuitry (nominal 2.5V).
Analog GND of ADC circuitry.
Analog supply of ADC circuitry (nominal 2.5V).
Digital input. 0=no inversion of output bits; 1 =
inversion of output bits.
Biasing of second stage of ADC. Connect to VDDA with
R=50kΩ and decouple with C=100 nF to GNDa.
Analog input 2nd ADC.
Analog reference input. Biasing of first stage of ADC.
Connect to VDDA with R=50kΩ and decouple with
C=100 nF to GNDa.
Analog reference input. High reference voltage of ADC.
(see figure 7 for exact resistor value)
Power supply reset drivers.
Power supply reset drivers.
Power supply Vmem drivers.
Power supply Vmem drivers.
Power supply pixel array.
Digital input. Control of reset signal in the pixel.
Digital input. Control of double slope reset in the pixel.
Digital input. Control of Vmem signal in pixel.
Digital input. Control of Vprecharge signal in pixel.
Digital input. Control of Vsample signal in pixel.
Cathode of temperature diode.
Anode of temperature diode.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 38 of 49
LUPA-4000
Data Sheet
Pad
Pin
Pin Name
Pin Type
109
B6
precharge_bias
Input
110
111
112
A8
A7
B12
photodiode
gndd
vdd
Testpin
Ground
Supply
113
A6
eos_y_l
Testpin
114
115
116
A1
A5
A2
sync_y
clock_y
norowsel
Input
Input
Input
117
A3
volt. averaging
Input
118
B5
pre_col
Input
119
120
121
122
123
124
125
126
127
A4
B1
B2
C1
D1
B4
B3
C2
E2
sh_col
prebus2
prebus1
dec_y_load
vpix
va3
gnda
vaa
gndd
Input
Input
Input
Input
Supply
Supply
Ground
Supply
Ground
Description
Analog reference input. Biasing for pixel array. (see
table 10 for exact resistor and capacitor value)
Output photodiode.
Ground digital modules.
Power supply digital modules.
Indicates when the end of frame is reached when
scanning in the ‘left’ direction.
Digital input. Synchronises the Y-address register.
Digital input. Clock of the Y-addressing.
Digital input. Control signal of the column readout.
Digital input. Control signal of the voltage averaging
in the column readout.
Digital input. Control signal of the column readout to
reduce row-blanking time.
Digital input. Control signal of the column readout.
Digital input. Control signal to reduce readout time.
Digital input. Control signal to reduce readout time.
Analog reference input. Biasing for Y-addressing.
Power supply pixel array.
Power supply column modules.
Ground analog modules.
Power supply analog modules.
Ground digital modules.
REMARKS:
1. All pins with the same name can be connected together.
2. All digital input are active high (unless mentioned otherwise).
3. All unused inputs should be tied to a non-active level (e.g. VDD or GND).
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 39 of 49
LUPA-4000
Data Sheet
6 Geometry and mechanical specifications
6.1 Bare die
27200 µm
Pixel array of 2048 x 2048 pixels
Pixel 0,0
25610 µm
Figure 21: Die figure of the LUPA-4000
Pixel 0,0 is located at 478 µm from the left side of the die and 1366 µm from the
bottom side of the die.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 40 of 49
LUPA-4000
Data Sheet
6.2 Package drawing
The LUPA-4000 is packaged in a 127-pin PGA package.
Figure 22: Package drawing of the LUPA-4000 package
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 41 of 49
LUPA-4000
Data Sheet
Figure 23: LUPA-4000 package specifications with die
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 42 of 49
LUPA-4000
Data Sheet
6.3 Bonding pads
The bonding pads are located as indicated below.
Figure 24: Placing of the bonding pads on the LUPA-4000 package
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 43 of 49
LUPA-4000
Data Sheet
6.4 Bonding diagram
The die is bonded to the bonding pads of the package as indicated below.
Figure 25: Bonding pads diagram of the LUPA-4000 package
The die will be placed in the package in a way that the center of the light sensitive
area will match the center of the package.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 44 of 49
LUPA-4000
Data Sheet
7 Handling and soldering precautions
Special care should be given when soldering image sensors with color filter arrays
(RGB color filters), onto a circuit board, since color filters are sensitive to high
temperatures. Prolonged heating at elevated temperatures may result in deterioration
of the performance of the sensor. The following recommendations are made to ensure
that sensor performance is not compromised during end-users’ assembly processes.
Board Assembly:
Device placement onto boards should be done in accordance with strict ESD controls
for Class 0, JESD22 Human Body Model, and Class A, JESD22 Machine Model
devices. Assembly operators should always wear all designated and approved
grounding equipment; grounded wrist straps at ESD protected workstations are
recommended including the use of ionized blowers. All tools should be ESD
protected.
Manual Soldering:
When a soldering iron is used the following conditions should be observed:
Use a soldering iron with temperature control at the tip.
The soldering iron tip temperature should not exceed 350°C.
The soldering period for each pin should be less than 5 seconds.
Precautions and cleaning:
Avoid spilling solder flux on the cover glass; bare glass and particularly glass with
antireflection filters may be adversely affected by the flux. Avoid mechanical or
particulate damage to the cover glass.
It is recommended that isopropyl alcohol (IPA) is used as a solvent for cleaning the
image sensor glass lid. When using other solvents, it should be confirmed beforehand
whether the solvent will dissolve the package and/or the glass lid or not.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 45 of 49
LUPA-4000
Data Sheet
8 Ordering Information
FillFactory Part Number
LUPA-4000-M
Cypress Semiconductor Part Number
CYIL1SM4000AA-GBC
Disclaimer
The LUPA-4000 is only to be used for non-military applications. A strict exclusivity
agreement prevents us to sell the LUPA-4000 to customers who intend to use it for
military applications.
FillFactory image sensors are only warranted to meet the specifications as described
in the production data sheet. Specifications are subject to change without notice.
Please contact [email protected] for more information.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 46 of 49
LUPA-4000
Data Sheet
APPENDIX A: LUPA-4000 evaluation system
For evaluating purposes an LUPA-4000 evaluation kit is available.
The LUPA-4000 evaluation kit consists of a multifunctional digital board (memory,
sequencer and IEEE 1394 Fire Wire interface) and an analog image sensor board.
Visual Basic software (under Win 2000 or XP) allows the grabbing and display of
images and movies from the sensor. All acquired images and movies can be stored in
different file formats (8 or 16-bit). All setting can be adjusted on the fly to evaluate
the sensors specs. Default register values can be loaded to start the software in a
desired state.
Figure 26: Content of the LUPA-4000 evaluation kit
Please contact Fillfactory ([email protected]) if you want any more information
on the evaluation kit.
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 47 of 49
LUPA-4000
Data Sheet
APPENDIX B:
Q:
A:
Frequently Asked Questions
How does the dual (multiple) slope extended dynamic range mode works?
Reset pulse
Read out
Double slope reset pulse
Reset level 1
p1
Reset level 2
p2
p3
p4
Saturation level
Double slope reset time (usually 510% of the total integration time)
Total integration time
Figure 27: Dual slope diagram
The green lines are the analog signal on the photodiode, which decrease as a result of
exposure. The slope is determined by the amount of light at each pixel (the more light
the steeper the slope). When the pixels reach the saturation level the analog signal will
not change despite further exposure. As you can see without any double slope pulse
pixels p3 and p4 will reach saturation before the sample moment of the analog values,
no signal will be acquired without double slope. When double slope is enabled a
second reset pulse will be given (blue line) at a certain time before the end of the
integration time. This double slope reset pulse resets the analog signal of the pixels
BELOW this level to the reset level. After the reset the analog signal starts to decrease
with the same slope as before the double slope reset pulse. If the double slope reset
pulse is placed at the end of the integration time (90% for instance) the analog signal
that would have reach the saturation levels aren't saturated anymore (this increases the
optical dynamic range) at read out. It's important to notice that pixel signals above
the double slope reset level will not be influenced by this double slope reset pulse (p1
and p2).
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 48 of 49
LUPA-4000
Data Sheet
Document History Page
Document Title: LUPA-4000 4M CMOS Image Sensor
Document Number:
Rev.
**
ECN
No.
310396
38-05712
Issue Date
See ECN
Orig. of
Change
SIL
Description
of Change
Initial
Cypress
release
(EOD)
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Contact: [email protected]
Document #: 38-05712 Rev.**(Revision 1.2 )
Page 49 of 49