MT8809 ISO-CMOS 8x8 Analog Switch Array

MT8809
8x8 Analog Switch Array
ISO-CMOS
Data Sheet
Features
September 2011
•
Internal control latches and address decoder
•
Short setup and hold times
•
Wide operating voltage: 4.5 V to 13.2 V
•
12 Vpp analog signal capability
•
RON 65  max. @ VDD = 12 V, 25C
•
RON 10  @ VDD = 12 V, 25C
•
Full CMOS switch for low distortion
•
Minimum feedthrough and crosstalk
Description
•
Low power consumption ISO-CMOS technology
•
Internal pull-up resistor for RESET pin
The Zarlink MT8809 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and
high reliability. The device contains a 8 x 8 array of
crosspoint switches along with a 6 to 64 line decoder
and latch circuits. Any one of the 64 switches can be
addressed by selecting the appropriate six address
bits. The selected switch can be turned on or off by
applying a logical one or zero to the DATA input. Chip
Select (CS) allows the crosspoint array to be cascaded
for matrix expansion.
Ordering Information
MT8809AP1
MT8809APR1
MT8809AE1
Key systems
•
PBX systems
•
Mobile radio
•
Test equipment/instrumentation
•
Analog/digital multiplexers
•
Audio/Video switching
CS
Tubes
Tape & Reel
Tubes
* Pb Free Matte Tin
-40C to +85C
Applications
•
28 Pin PLCC*
28 Pin PLCC*
28 Pin PDIP*
DATA RESET
STROBE
1
VDD
VSS
1
AX0
AX2
AY0
6 to 64
Decoder
8 x 8
Switch
Array
Latches
AY1
AY2
64
64
•••••••••••••••••••
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1988 - 2011, Zarlink Semiconductor Inc. All Rights Reserved.
••••••••••••••••
AX1
Xi I/O
(i=0-7)
MT8809
Data Sheet
Change Summary
Changes from the September 2005 issue to the September 2011 issue.
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AY1
AY0
AX2
AX1
AX0
X1
X3
X5
X7
VDD
Y0
Y1
Y2
Y3
4
3
2
1
28
27
26
AY2
STROBE
CS
DATA
VSS
X0
X2
X4
X6
RESET
Y7
Y6
Y5
Y4
Removed leaded packages as per PCN notice.
DATA
CS
STROBE
AY2
AY1
AY0
AX2
Ordering Information
VSS
X0
X2
X4
X6
RESET
Y7
5
6
7
8
9
10
11

12
13
14
15
16
17
18
1
Change
25
24
23
22
21
20
19
AX1
AX0
X1
X3
X5
X7
VDD
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Page
28 PIN PLCC
28 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
1
AY2
2
Description
AY2 Address Line (Input).
STROBE STROBE (Input): enables function selected by address and data. Address must be stable
before STROBE goes low and DATA must be stable on the rising edge of STROBE. Active
Low.
Chip Select (Input): this is used to select the device. Active Low.
3
CS
4
DATA
5
VSS
6-9
X0, X2,
X4, X6
X0, X2, X4 and X6 Analog (Inputs/Outputs): these are connected to the X0, X2, X4 and
X6 rows of the switch array.
10
RESET
Master RESET (Input): this is used to turn off all switches regardless of the condition of
CS. A 100 k internal pull-up resistor is also provided. This can be used in conjunction
with a 0.1 F capacitor (connected to the RESET pin) to perform power-on reset of the
device. Active Low.
11-18
Y7 - Y0
Y7 - Y0 Analog (Inputs/Outputs): these are connected to the Y0 - Y7 columns of the
switch array.
DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
Ground Reference.
2
Zarlink Semiconductor Inc.
MT8809
Data Sheet
Pin Description
Pin #
Name
19
VDD
20-23
X7, X5,
X3, X1
Description
Positive Power Supply.
X7, X5, X3 and X1 Analog (Inputs/Outputs): these are connected to the X7, X5, X3 and
X1 rows of the switch array.
24-26
AX0-AX2 AX0 - AX2 Address Lines (Inputs).
27, 28
AY0, AY1 AY0 and AY1 Address Lines (Inputs).
Functional Description
The MT8809 is an analog switch matrix with an array size of 8 x 8. The switch array is arranged such that there are
8 columns by 8 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs.
The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high
degree of isolation when turned off. The control memory consists of a 64 bit write only RAM in which the bits are
selected by the address inputs (AY0-AY2, AX0-AX2). Data is presented to the memory on the DATA input. Data is
asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are low and are
latched on the rising edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint
switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed
memory location are altered when data is written into memory. The remaining switches retain their previous states.
Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the
control memory. A logical “0” on the RESET input will asynchronously return all memory locations to logical “0”
turning off all crosspoint switches regardless of whether CS is high or low.
Address Decode
The six address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal
for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to
a location, RESET must be high and CS must go low while the address and data are set up. Then the STROBE
input is set low and then high causing the data to be latched. The data can be changed while STROBE is low,
however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on
the rising edge of STROBE in order for correct data to be written to the latch.
3
Zarlink Semiconductor Inc.
MT8809
Data Sheet
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
1
Supply Voltage
VDD
VSS
-0.3
-0.3
15.0
VDD+0.3
V
V
2
Analog Input Voltage
VINA
-0.3
VDD+0.3
V
3
Digital Input Voltage
VIN
VSS-0.3
VDD+0.3
V
4
Current on any I/O Pin
15
mA
5
Storage Temperature
+150
C
0.6
W
I
-65
TS
6 Package Power Dissipation
PLASTIC DIP
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
TO
-40
25
85
C
1
Operating Temperature
2
Supply Voltage
VDD
4.5
13.2
V
3
Analog Input Voltage
VINA
VSS
VDD
V
4
Digital Input Voltage
VIN
VSS
VDD
V
DC Electrical Characteristics†Characteristics
1
Quiescent Supply Current
Test Conditions
Voltages are with respect to VSS = 0 V, VDD = 12 V unless otherwise stated.
Sym.
Min.
Typ.‡
Max.
Units
1
100
A
All digital inputs at VIN = VSS
VDD except RESET = VDD.
120
400
A
All digital inputs at VIN = VSS
or VDD except RESET = VSS.
0.5
1.6
mA
All digital inputs at VIN = 2.4 V,
VDD = 5.0 V
5
15
mA
All digital inputs at VIN = 3.4 V
1
500
nA
IVXi - VYjI = VDD - VSS
See Appendix, Fig. A.1
0.8
V
IDD
2
Off-state Leakage Current
(See G.9 in Appendix)
IOFF
3
Input Logic “0” level
VIL
4
Input Logic “1” level
VIH
6
Input Leakage (digital pins)
ILEAK
3.0
Test Conditions
V
0.1
10
A
All digital inputs at VIN = VSS
or VDD; RESET = VDD
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
4
Zarlink Semiconductor Inc.
MT8809
Data Sheet
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics
Sym.
25C
70C
Typ.
Max.
Typ.
85C
Max.
Typ.
Units
Test Conditions
Max.
1
On-state VDD =12 V
ResistanceVDD=10V
VDD= 5V
(See G.1, G.2, G.3 in
Appendix)
RON
45
55
120
65
75
185
75
85
215
80
90
225



VSS = 0 V,VDC = VDD/2,
IVXi-VYjI = 0.4 V
See Appendix, Fig. A.2
2
Difference in on-state
resistance between
two switches
(See G.4 in Appendix)
RO
5
10
10
10

VDD = 12 V, VSS = 0,
VDC = VDD/2,
IVXi-VYjI = 0.4 V
See Appendix, Fig. A.2
N
AC Electrical Characteristics† - Crosspoint Performance- VDC is the external DC offset at the analog I/O pins. Voltages are
with respect to VDD = 5 V, VDC = 0 V, VSS = -7 V, unless otherwise stated.
Characteristics
Sym.
Typ.‡
Min.
Max.
Units
Test Conditions
1
Switch I/O Capacitance
CS
20
pF
f = 1 MHz
2
Feedthrough Capacitance
CF
0.2
pF
f = 1 MHz
3
Frequency Response
Channel “ON”
20LOG(VOUT/VXi)=-3 dB
F3dB
45
MHz
Switch is “ON”; VINA = 2 Vpp
sinewave; RL = 1 k
See Appendix, Fig. A.3
4
Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD
0.01
%
Switch is “ON”; VINA = 2 Vpp
sinewave f = 1 kHz; RL= 1 k
5
Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
FDT
-95
dB
All Switches “OFF”; VINA=
2Vpp sinewave f = 1 kHz;
RL = 1 k.
See Appendix, Fig. A.4
6
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk
-45
dB
VINA = 2Vpp sinewave
f = 10 MHz; RL = 75 .
-90
dB
VINA = 2Vpp sinewave
f = 10kHz; RL = 600 .
-85
dB
VINA=2Vpp sinewave
f = 10 kHz; RL = 1 k.
-80
dB
VINA = 2Vpp sinewave
f = 1 kHz; RL = 10 k.
Refer to Appendix, Fig. A.5
for test circuit.
ns
RL = 1 k; CL = 50 pF
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
7
Propagation delay through
switch
tPS
30
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better.
5
Zarlink Semiconductor Inc.
MT8809
Data Sheet
AC Electrical Characteristics† - Control and I/O Timings- VDC is the external DC offset applied at the analog I/O pins.
Voltages are with respect to VDD = 5 V, VDC = 0 V, VSS = -7 V, unless otherwise stated.
Min.
Typ.‡
Characteristics
Sym.
Max.
Units
Test Conditions
1
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CXtalk
30
mVpp
VIN=3V+VDC squarewave;
RIN=1 k, RL=1 k.
See Appendix, Fig. A.6
2
Digital Input Capacitance
CDI
10
pF
3
Switching Frequency
FO
4
Setup Time DATA to STROBE
tDS
10
ns
RL= 1 k,
CL= 50 pF ¿ Å
5
Hold Time DATA to STROBE
tDH
10
ns
RL= 1 k,
CL= 50 pF Å¿
6
Setup Time Address to STROBE
tAS
10
ns
RL= 1 k,
CL= 50 pF Å¿
7
Hold Time Address to STROBE
tAH
10
ns
RL= 1 k,
CL= 50 pF Å¿
8
Setup Time CS to STROBE
tCSS
10
ns
RL= 1 k,
CL= 50 pF Å¿
9
Hold Time CS to STROBE
tCSH
10
ns
RL= 1 k,
CL= 50 pF ¿Å
10
STROBE Pulse Width
tSPW
20
ns
RL= 1 k,
CL= 50 pF ¿Å
11
RESET Pulse Width
tRPW
40
ns
RL= 1 k,
CL= 50 pF Å¿
12
STROBE to Switch Status Delay
tS
40
100
ns
RL= 1 k,
CL=50 pF Å¿
13
DATA to Switch Status Delay
tD
50
100
ns
RL= 1 k,
CL= 50 pF Å¿
14
RESET to Switch Status Delay
tR
35
100
ns
RL= 1 k,
CL= 50 pF ¿Å
20
f = 1 MHz
MHz
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5 ns.
‡ Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Å¿Refer to Appendix, Fig. A.7 for test circuit.
tCSS
CS
tCSH
50%
50%
tRPW
RESET
tSPW
STROBE
50%
ADDRESS
50%
50%
tR
tR
50%
50%
50%
tAS
DATA
50%
tAH
50%
50%
tDS
tDH
ON
SWITCH*
OFF
tS
tD
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
6
Zarlink Semiconductor Inc.
MT8809
AY2
AY1
AY0
AX2
AX1
AX0
Connection
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Data Sheet
AY2
AY1
AY0
AX2
AX1
AX0
Y0
Y0
Y0
Y0
Y0
Y0
Y0
Y0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y4
X0
X1
X2
X3
X4
X5
X6
X7
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y5
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y6
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Table 1 - Address Decode Truth Table
7
Zarlink Semiconductor Inc.
Connection
MT8809
8x8 Analog Switch Array
ISO-CMOS
Data Sheet
Features
September 2005
•
Internal control latches and address decoder
•
Short setup and hold times
•
Wide operating voltage: 4.5 V to 13.2 V
•
12 Vpp analog signal capability
•
RON 65 Ω max. @ VDD = 12 V, 25°C
•
∆RON ≤ 10 Ω @ VDD = 12 V, 25C
•
Full CMOS switch for low distortion
•
Minimum feedthrough and crosstalk
•
Low power consumption ISO-CMOS technology
•
Internal pull-up resistor for RESET pin
Ordering Information
MT8809AE
MT8809AP
MT8809APR
MT8809AP1
MT8809APR1
MT8809AE1
Key systems
•
PBX systems
•
Mobile radio
•
Test equipment/instrumentation
•
Analog/digital multiplexers
•
Audio/Video switching
CS
Pin
Pin
Pin
Pin
Pin
Pin
PDIP
PLCC
PLCC
PLCC*
PLCC*
PDIP*
Tubes
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
* Pb Free Matte Tin
-40°C to +85°C
Description
The Zarlink MT8809 is fabricated in Zarlink’s ISOCMOS technology providing low power dissipation and
high reliability. The device contains a 8 x 8 array of
crosspoint switches along with a 6 to 64 line decoder
and latch circuits. Any one of the 64 switches can be
addressed by selecting the appropriate six address
bits. The selected switch can be turned on or off by
applying a logical one or zero to the DATA input. Chip
Select (CS) allows the crosspoint array to be cascaded
for matrix expansion.
Applications
•
28
28
28
28
28
28
DATA RESET
STROBE
1
VDD
VSS
1
AX0
AX2
AY0
6 to 64
Decoder
8 x 8
Switch
Array
Latches
AY1
AY2
64
64
•••••••••••••••••••
Yi I/O (i=0-7)
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1988 - 2005, Zarlink Semiconductor Inc. All Rights Reserved.
••••••••••••••••
AX1
Xi I/O
(i=0-7)
MT8809
DATA
CS
STROBE
AY2
AY1
AY0
AX2
AY1
AY0
AX2
AX1
AX0
X1
X3
X5
X7
VDD
Y0
Y1
Y2
Y3
4
3
2
1
28
27
26
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
X0
X2
X4
X6
RESET
Y7
5
6
7
8
9
10
11
•
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
25
24
23
22
21
20
19
AX1
AX0
X1
X3
X5
X7
VDD
Y6
Y5
Y4
Y3
Y2
Y1
Y0
AY2
STROBE
CS
DATA
VSS
X0
X2
X4
X6
RESET
Y7
Y6
Y5
Y4
Data Sheet
28 PIN PLCC
28 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
1
AY2
2
Description
AY2 Address Line (Input).
STROBE STROBE (Input): enables function selected by address and data. Address must be stable
before STROBE goes low and DATA must be stable on the rising edge of STROBE. Active
Low.
3
CS
4
DATA
5
VSS
6-9
X0, X2,
X4, X6
X0, X2, X4 and X6 Analog (Inputs/Outputs): these are connected to the X0, X2, X4 and
X6 rows of the switch array.
10
RESET
Master RESET (Input): this is used to turn off all switches regardless of the condition of
CS. A 100 kΩ internal pull-up resistor is also provided. This can be used in conjunction
with a 0.1 µF capacitor (connected to the RESET pin) to perform power-on reset of the
device. Active Low.
11-18
Y7 - Y0
Y7 - Y0 Analog (Inputs/Outputs): these are connected to the Y0 - Y7 columns of the
switch array.
19
VDD
20-23
X7, X5,
X3, X1
Chip Select (Input): this is used to select the device. Active Low.
DATA (Input): a logic high input will turn on the selected switch and a logic low will turn off
the selected switch. Active High.
Ground Reference.
Positive Power Supply.
X7, X5, X3 and X1 Analog (Inputs/Outputs): these are connected to the X7, X5, X3 and
X1 rows of the switch array.
24-26
AX0-AX2 AX0 - AX2 Address Lines (Inputs).
27, 28
AY0, AY1 AY0 and AY1 Address Lines (Inputs).
2
Zarlink Semiconductor Inc.
MT8809
Data Sheet
Functional Description
The MT8809 is an analog switch matrix with an array size of 8 x 8. The switch array is arranged such that there are
8 columns by 8 rows. The columns are referred to as the Y inputs/outputs and the rows are the X inputs/outputs.
The crosspoint analog switch array will interconnect any X I/O with any Y I/O when turned on and provide a high
degree of isolation when turned off. The control memory consists of a 64 bit write only RAM in which the bits are
selected by the address inputs (AY0-AY2, AX0-AX2). Data is presented to the memory on the DATA input. Data is
asynchronously written into memory whenever both the CS (Chip Select) and STROBE inputs are low and are
latched on the rising edge of STROBE. A logical “1” written into a memory cell turns the corresponding crosspoint
switch on and a logical “0” turns the crosspoint off. Only the crosspoint switches corresponding to the addressed
memory location are altered when data is written into memory. The remaining switches retain their previous states.
Any combination of X and Y inputs/outputs can be interconnected by establishing appropriate patterns in the
control memory. A logical “0” on the RESET input will asynchronously return all memory locations to logical “0”
turning off all crosspoint switches regardless of whether CS is high or low.
Address Decode
The six address inputs along with the STROBE and CS (Chip Select) are logically ANDed to form an enable signal
for the resettable transparent latches. The DATA input is buffered and is used as the input to all latches. To write to
a location, RESET must be high and CS must go low while the address and data are set up. Then the STROBE
input is set low and then high causing the data to be latched. The data can be changed while STROBE is low,
however, the corresponding switch will turn on and off in accordance with the DATA input. DATA must be stable on
the rising edge of STROBE in order for correct data to be written to the latch.
3
Zarlink Semiconductor Inc.
MT8809
Data Sheet
Absolute Maximum Ratings*- Voltages are with respect to VSS unless otherwise stated.
Parameter
Symbol
Min.
Max.
Units
1
Supply Voltage
VDD
VSS
-0.3
-0.3
15.0
VDD+0.3
V
V
2
Analog Input Voltage
VINA
-0.3
VDD+0.3
V
3
Digital Input Voltage
VIN
VSS-0.3
VDD+0.3
V
4
Current on any I/O Pin
±15
mA
5
Storage Temperature
+150
°C
0.6
W
I
-65
TS
6 Package Power Dissipation
PLASTIC DIP
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to VSS unless otherwise stated.
Characteristics
Sym.
Min.
Typ.
Max.
Units
TO
-40
25
85
°C
1
Operating Temperature
2
Supply Voltage
VDD
4.5
13.2
V
3
Analog Input Voltage
VINA
VSS
VDD
V
4
Digital Input Voltage
VIN
VSS
VDD
V
DC Electrical Characteristics†Characteristics
1
Quiescent Supply Current
Test Conditions
Voltages are with respect to VSS = 0 V, VDD = 12 V unless otherwise stated.
Sym.
Min.
Typ.‡
Max.
Units
1
100
µA
All digital inputs at VIN = VSS
VDD except RESET = VDD.
120
400
µA
All digital inputs at VIN = VSS
or VDD except RESET = VSS.
0.5
1.6
mA
All digital inputs at VIN = 2.4 V,
VDD = 5.0 V
5
15
mA
All digital inputs at VIN = 3.4 V
±1
±500
nA
IVXi - VYjI = VDD - VSS
See Appendix, Fig. A.1
0.8
V
IDD
2
Off-state Leakage Current
(See G.9 in Appendix)
IOFF
3
Input Logic “0” level
VIL
4
Input Logic “1” level
VIH
6
Input Leakage (digital pins)
ILEAK
3.0
Test Conditions
V
0.1
10
µA
All digital inputs at VIN = VSS
or VDD; RESET = VDD
† DC Electrical Characteristics are over recommended temperature range.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
4
Zarlink Semiconductor Inc.
MT8809
Data Sheet
DC Electrical Characteristics- Switch Resistance - VDC is the external DC offset applied at the analog I/O pins.
Characteristics
Sym.
25°C
70°C
Typ.
Max.
Typ.
85°C
Max.
Typ.
Units
Test Conditions
Max.
1
On-state VDD =12 V
ResistanceVDD=10V
VDD= 5V
(See G.1, G.2, G.3 in
Appendix)
RON
45
55
120
65
75
185
75
85
215
80
90
225
Ω
Ω
Ω
VSS = 0 V,VDC = VDD/2,
IVXi-VYjI = 0.4 V
See Appendix, Fig. A.2
2
Difference in on-state
resistance between
two switches
(See G.4 in Appendix)
∆RO
5
10
10
10
Ω
VDD = 12 V, VSS = 0,
VDC = VDD/2,
IVXi-VYjI = 0.4 V
See Appendix, Fig. A.2
N
AC Electrical Characteristics† - Crosspoint Performance- VDC is the external DC offset at the analog I/O pins. Voltages are
with respect to VDD = 5 V, VDC = 0 V, VSS = -7 V, unless otherwise stated.
Characteristics
Sym.
Typ.‡
Min.
Max.
Units
Test Conditions
1
Switch I/O Capacitance
CS
20
pF
f = 1 MHz
2
Feedthrough Capacitance
CF
0.2
pF
f = 1 MHz
3
Frequency Response
Channel “ON”
20LOG(VOUT/VXi)=-3 dB
F3dB
45
MHz
Switch is “ON”; VINA = 2 Vpp
sinewave; RL = 1 kΩ
See Appendix, Fig. A.3
4
Total Harmonic Distortion
(See G.5, G.6 in Appendix)
THD
0.01
%
Switch is “ON”; VINA = 2 Vpp
sinewave f = 1 kHz; RL= 1 kΩ
5
Feedthrough
Channel “OFF”
Feed.=20LOG (VOUT/VXi)
(See G.8 in Appendix)
FDT
-95
dB
All Switches “OFF”; VINA=
2Vpp sinewave f = 1 kHz;
RL = 1 kΩ.
See Appendix, Fig. A.4
6
Crosstalk between any two
channels for switches Xi-Yi and
Xj-Yj.
Xtalk
-45
dB
VINA = 2Vpp sinewave
f = 10 MHz; RL = 75 Ω.
-90
dB
VINA = 2Vpp sinewave
f = 10kHz; RL = 600 Ω.
-85
dB
VINA=2Vpp sinewave
f = 10 kHz; RL = 1 kΩ.
-80
dB
VINA = 2Vpp sinewave
f = 1 kHz; RL = 10 kΩ.
Refer to Appendix, Fig. A.5
for test circuit.
ns
RL = 1 kΩ; CL = 50 pF
Xtalk=20LOG (VYj/VXi).
(See G.7 in Appendix).
7
Propagation delay through
switch
tPS
30
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Crosstalk measurements are for Plastic DIPS only, crosstalk values for PLCC packages are approximately 5 dB better.
5
Zarlink Semiconductor Inc.
MT8809
Data Sheet
AC Electrical Characteristics† - Control and I/O Timings- VDC is the external DC offset applied at the analog I/O pins.
Voltages are with respect to VDD = 5 V, VDC = 0 V, VSS = -7 V, unless otherwise stated.
Min.
Typ.‡
Characteristics
Sym.
Max.
Units
Test Conditions
1
Control Input crosstalk to switch
(for CS, DATA, STROBE,
Address)
CXtalk
30
mVpp
VIN=3V+VDC squarewave;
RIN=1 kΩ, RL=1 kΩ.
See Appendix, Fig. A.6
2
Digital Input Capacitance
CDI
10
pF
3
Switching Frequency
FO
4
Setup Time DATA to STROBE
tDS
10
ns
RL= 1 kΩ,
CL= 50 pF ¿ Å
5
Hold Time DATA to STROBE
tDH
10
ns
RL= 1 kΩ,
CL= 50 pF Å¿
6
Setup Time Address to STROBE
tAS
10
ns
RL= 1 kΩ,
CL= 50 pF Å¿
7
Hold Time Address to STROBE
tAH
10
ns
RL= 1 kΩ,
CL= 50 pF Å¿
8
Setup Time CS to STROBE
tCSS
10
ns
RL= 1 kΩ,
CL= 50 pF Å¿
9
Hold Time CS to STROBE
tCSH
10
ns
RL= 1 kΩ,
CL= 50 pF ¿Å
10
STROBE Pulse Width
tSPW
20
ns
RL= 1 kΩ,
CL= 50 pF ¿Å
11
RESET Pulse Width
tRPW
40
ns
RL= 1 kΩ,
CL= 50 pF Å¿
12
STROBE to Switch Status Delay
tS
40
100
ns
RL= 1 kΩ,
CL=50 pF Å¿
13
DATA to Switch Status Delay
tD
50
100
ns
RL= 1 kΩ,
CL= 50 pF Å¿
14
RESET to Switch Status Delay
tR
35
100
ns
RL= 1 kΩ,
CL= 50 pF ¿Å
20
f = 1 MHz
MHz
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5 ns.
‡ Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Å¿Refer to Appendix, Fig. A.7 for test circuit.
tCSS
CS
tCSH
50%
50%
tRPW
RESET
tSPW
STROBE
50%
ADDRESS
50%
50%
tR
tR
50%
50%
50%
tAS
DATA
50%
tAH
50%
50%
tDS
tDH
ON
SWITCH*
OFF
tS
tD
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
6
Zarlink Semiconductor Inc.
MT8809
AY2
AY1
AY0
AX2
AX1
AX0
Connection
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Data Sheet
AY2
AY1
AY0
AX2
AX1
AX0
Y0
Y0
Y0
Y0
Y0
Y0
Y0
Y0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y4
X0
X1
X2
X3
X4
X5
X6
X7
Y1
Y1
Y1
Y1
Y1
Y1
Y1
Y1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y5
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Y6
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y3
Y3
Y3
Y3
Y3
Y3
Y3
Y3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X0
X1
X2
X3
X4
X5
X6
X7
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Table 1 - Address Decode Truth Table
7
Zarlink Semiconductor Inc.
Connection
Package Code
c Zarlink Semiconductor 2005. All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
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