PI3755-01

Cool-Power®
PI3755-01
38 V to 60 Vin, 160 W Cool-Power ZVS Buck-Boost
Product Description
Features
The PI3755-01 is a high efficiency, wide input range DC-DC
ZVS-Buck-Boost regulator. This high density module
integrates controller, power switches, and support
components. The integration of a high performance ZeroVoltage Switching (ZVS) topology, within the PI3755-01,
increases point of load performance providing best in class
power efficiency.
• 98% efficiency at 1.5 MHz FSW
The PI3755-01 requires an externally applied 5 V bias to the
VDR input, an external inductor, resistive divider and
minimal capacitors to form a complete DC-DC switching
mode buck-boost regulator.
• Light load mode < 200 mW no load power dissipation
• Wide input voltage range of 38 V to 60 V
• Wide output voltage range of 28 V to 54 V
• 160 W continuous output power
• Power density exceeding 6,400 W/in3
• Fast transient response in VRM 12.X applications
• VTM compatibility mode
• User configurable differential amplifier
• Input / Output Over / Under Voltage Protection
The ZVS architecture also enables high frequency
operation while minimizing switching losses and
maximizing efficiency. The high switching frequency
operation reduces the size of the external filtering
components, improves power density, and enables
very fast dynamic response to line and load
transients. The PI3755-01 sustains high switching
frequency up to the rated input voltage without
sacrificing efficiency and supports large conversion
ratios.
• Over temperature protection
• Fast and slow current limits
• -40°C to 125°C operating range (TJ)
Applications
• VR12.X Factorized Power Solution
(when coupled with a VTM® device)
• Computing, Communications, DDR Memory
• 48 V to POL Power Solutions
Package Information
• 10 mm x 10 mm x 2.56 mm Land Grid Array Module
Typical Application
5V
LEXT
VDR
VS1
+
5V
VCC
VS2
Vin 38 V - 60 V
Vout
VTM
PI3755
5V
EAO
VDIFF ENABLE FLT
ENABLE TM
10 k
10 k
ENABLE
IMON
SVID
EA Controller
SYSTEM ENABLE
Applications Diagram for use within a Factorized Power, VR12.5 Design
Cool-Power®
Rev 1.0
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Memory
PI3755-01
Contents
Contents
Page
Contents
Applications Information
Page
14
Order Information
3
Absolute Maximum Ratings
3
Buck Boost Configuration of EAIN Pin
14
Pin Description
4
Buck Boost Configuration of EAO Pin
14
Package Pin-Out
5
Buck Boost Configuration of COMP Pin
14
Large Pin Blocks
5
Stability Considerations
14
Storage and Handling Information
6
Midband Gain Design (R1,R3)
16
Block Diagram
6
Compensation Zero Design (C1)
16
Electrical Characteristics
7
High Frequency Pole Design
16
Typical Characteristics
10
Verifying Stability
16
Functional Description
12
Input Filter Stability
17
Inductor Pairing
12
Design and Performance
18
External 5V Bias Supply
12
Package Drawings
24
Enable
12
Receiving PCB Pattern Design Recommendations
25
Switching Frequency Synchronization
12
Revision History
26
Soft-Start and Tracking
12
Warranty
27
Remote Sensing Differential Amplifier
12
Bidirectional Fault Pin
12
Output Current Limit Protection
12
Input Under-Voltage Lockout
13
Input Over-Voltage Lockout
13
Output Over-Voltage Protection
13
Over Temperature Protection
13
Pulse Skip Mode (PSM)
13
Variable Frequency Operation
13
Cool-Power®
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PI3755-01
Order Information
Part Number
Input Range
Package
Transport Media
PI3755-01-LGIZ
PI3755-01-LGIZ
10 mm x 10 mm 71-pin Land Grid Array
TRAY
Absolute Maximum Ratings
Note: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the
Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted.
[1]
[2]
Location
Name
F1-2, G1-2, H1-2
VIN[2]
K1-5
VMAX
VMIN
ISOURCE
75 V
-0.3 V
A[1]
20 A[1]
VS1
75 V
-0.7 V DC
20 A[1]
20 A[1]
K7-10
VS2
75 V
-0.7 V DC
20 A[1]
20 A[1]
F9-10, G9-10, H9-10
VOUT
75 V
-0.7 V DC
20 A[1]
20 A[1]
1A
FLT
5.5 V
-0.3 V
20 mA
20 mA
2A
SYNC IN
5.5 V
-0.3 V
5 mA
5 mA
3A
SYNC OUT
5.5 V
-0.3 V
5 mA
5 mA
4A
ENABLE
5.5 V
-0.3 V
5 mA
5 mA
5A
LGH
5.5 V
-0.3 V
5 mA
5 mA
6A
COMP
5.5 V
-0.3 V
5 mA
5 mA
7A
VSN
5.5 V
-1.5 V
5 mA
5 mA
8A
VSP
5.5 V
-1.5 V
5 mA
5 mA
9A
VDIFF
5.5 V
-0.5 V
5 mA
5 mA
10A
EAIN
5.5 V
-0.3 V
5 mA
5 mA
1B
VDR
5.5 V
-0.3 V
30 mA
200 mA
2B
FT1
5.5 V
-0.3 V
5 mA
5 mA
3B
FT2
5.5 V
-0.3 V
10 mA
10 mA
4B
FT3
5.5 V
-0.3 V
5 mA
5 mA
5B
FT4
5.5 V
-0.3 V
5 mA
5 mA
10B
EAO
5.5 V
-0.3 V
5 mA
5 mA
10C
SS/TRK
5.5 V
-0.3 V
50 mA
50 mA
1D
FT5
75 V
-0.3 V
500 mA
500 mA
B6-9, C6-9, D4-10
SGND
0.3 V
-0.3 V
200 mA
200 mA
D3, E4-7, F4-7,
G4-7, H4-7
PGND
N/A
N/A
20 A[1]
20 A[1]
Non-Operating Test Mode Limits.
VIN has a minimum limit of VDR – 0.3 VDC. VDR has an internal diode to VIN.
Cool-Power®
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20
ISINK
PI3755-01
Pin Description
Pin Number
Pin Name
Description
F1-2, G1-2, H1-2
VIN
Input voltage and sense node for UVLO, OVLO and feed forward compensation.
K1-5
VS1
Input side switching node and ZVS sense node for power switches.
K7-10
VS2
Output side switching node and ZVS sense node for power switches.
F9-10, G9-10, H9-10
VOUT
Output voltage and sense node for power switches, VOUT feed forward compensation, VOUT_OV and internal
VBUS_HI signals.
1A
FLT
Regulator Fault input / output signal. Connect to the TM pin of the VTM to synchronize system control and
soft-start. If used in a non-VTM application, pull up to VDR with a 10k ohm resistor to enable the PI3755.
2A
SYNC IN
3A
SYNC OUT
4A
ENABLE
5A
LGH
6A
COMP
7A
VSN
General purpose amplifier inverting input.
8A
VSP
General purpose amplifier non-inverting input.
9A
VDIFF
General purpose amplifier output.
10A
EAIN
Error amplifier inverting input. Connect by resistive divider to the output.
1B
VDR
5V input for gate driver and internal logic. Connect to 5V power supply (5.1V recommended).
2B
FT1
For factory use only. Connect to SGND in application.
3B
FT2
For factory use only. Connect to SGND in application.
4B
FT3
For factory use only. Connect to SGND in application.
5B
FT4
For factory use only. Connect to SGND in application.
10B
EAO
Transconductance error amplifier output, PWM input and external connection for load sharing. Connect a
capacitor between EAO and SGND to set the control loop high frequency pole.
10C
SS/TRK
Soft-start and track input. If used in a non-VTM application an external capacitor is required between TRK
and SGND to decrease the rate of output rise during soft-start.
1D
FT5
B6-9, C6-9, D4-10
SGND
Signal ground. Internal logic and analog ground for the regulator. SGND and PGND are star connected
within the regulator package.
PGND
Power ground. VIN, VOUT, VS1 and VS2 power returns. SGND and PGND are star connected within the
regulator package.
D3, E4-7, F4-7,
G4-7, H4-7
Synchronization input. The PI3755 will synchronize the start of its switching cycles to the falling edge of a
clock signal received on the SYNC IN pin. A clock frequency less than 50% or greater than 110% of the
PI3755’s programed FSW will be ignored. Connect to SGND when not in use.
Synchronization output. Outputs a high signal for ½ of the programmed switching period at the beginning
of each switching cycle, for synchronization of other converters.
Regulator Enable control. Asserted high or left floating = regulator enabled;
Asserted low, regulator output disabled.
For factory use only. Connect to SGND in application.
Error amp compensation dominant pole. Connect a capacitor between COMP and SGND to set the control
loop dominant pole.
For factory use only. Leave floating in application.
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PI3755-01
Package Pin-Out
VS1
VS1
VS1
VS1
VS1
VS1
VS2
VS2
VS2
VS2
K
VS2
J
VIN
H
VOUT
VIN
G
VOUT
VIN
F
VOUT
E
D
SGND
C
SS/TRK
VDR
B
EAO
FLT
A
EAIN
FT5
1
2
3
4
5
6
7
8
9
10
FLT
SYNC IN
SYNC OUT
EN
LGH
COMP
VSN
VSP
VDIFF
EAIN
PACKAGE TOP VIEW
Exposed Copper
Solder Mask Over Copper
Large Pin Blocks
Pin Block Name
Group of pins
VIN
F1-2, G1-2, H1-2
VS1
K1-5
PGND
D3, E4-7, F4-7, G4-7, H4-7
VS2
K7-10
VOUT
F9-10, G9-10, H9-10
SGND
B6-9, C6-9, D4-10
Cool-Power®
Rev 1.0
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Solder Mask Over Board
PI3755-01
Storage and Handling Information
Maximum Storage Temperature Range
-65°C to 150°C
Maximum Operating Junction Temperature Range
-40°C to 125°C
Soldering Temperature for 20 seconds
245°C
MSL Rating
3
[3]
ESD Rating
[3]
1.5 kV HBM; 1.0 kV CDM
JESD22-C101F, JESD22-A114F
Block Diagram
LEX T
VOUT
VIN
Q1
Q3
VS1
VS2
Q2
Q4
VSN
+
VSP
VDIFF
LDO
LGH
VDR
EAIN
-
ZVS Buck Boost Control
+ 1.7V
EAO
SYNC OUT
SYNC IN
and
FLT
ENABLE
COMP
Digital Parametric Trim
CLAMP
PGND
0Ω
FT5
FT1 -FT4
SGND
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Rev 1.0
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SS/TRK
PI3755-01
Electrical Characteristics
Specifications apply for the conditions -40°C < TJ < 125°C, external VDR = 5.1 V, VIN = 54 V, VOUT = 44 V, LEXT = 1.5 µH, external CIN = 6 µF, COUT = 6 µF
as shown in the Applications Diagram or Figure 4, unless otherwise noted. All voltage nodes are referenced to PGND unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
38
54
60
V
Input Specifications
Input Voltage
VIN_DC
Input Current
IIN_DC
VIN = 54 V VOUT = 44 V IOUT = 2.3 A
1.91
A
Input Current During Output Short
(fault condition duty cycle)
IIN_SHORT
[5]
6
mA
Input Quiescent Current
IQ_VIN_EN
Enabled (no load)
1
mA
Input Quiescent Current
IQ_VIN
0.1
mA
Input Voltage Slew Rate
VIN_SR
Internal Input Capacitance
CIN
VIN UVLO threshold rising
VIN_UVLO_START
VIN UVLO hysteresis
VIN OVLO threshold rising
VIN OVLO hysteresis
Disabled, VDR; Powered Externally
1
100 V, X7R type, 25°C, VIN = 0 V
0.5
34
VIN_UVLO_HYS
35.8
µF
37.6
1.8
VIN_OVLO_START
61
VIN_OVLO_HYS
64.5
V/µs
V
V
68
1.3
V
V
Output Specifications
Output Voltage Range
Output Current Steady State
Output Current Steady State
VOUT_DC
28
IOUT_DC
VOUT = 28 V
4[7]
A
VOUT = 44 V
3.2[7]
A
VOUT = 54 V
3[7]
A
IOUT_DC
Output Current Steady State
IOUT_DC
Internal Output Capacitance
COUT
VOUT Over Voltage Threshold
VOUT_OVT
VOUT Over Voltage Hysteresis
VOUT_OVH
100 V, X7R type, 25°C, VOUT = 0 V
Rising VOUT threshold to detect open loop
54
0.5
54.7
57.6
V
µF
60.0
2.7
V
V
VDR Input
VDR Supply Voltage
VDR_SP
Supply Externally
VDR Quiescent Current
VDR_IQ
Enabled, IOUT = 1.5 A
VDR Quiescent Current
VDR_IQ
Disabled
VDR Internal LDO output set point
VDR_LDO
VDR Internal LDO output current
VDR UVLO Start Threshold
VDR UVLO Hysteresis
VDR UVLO Start - VDR LDO set point
4.9
60 V >VIN >8 V
VDR_UVLO_START Rising VDR threshold to clear UVLO
5.1
5.36
V
45
55
mA
3
5
10
mA
4.25
4.4
4.7
V
13
20
25
mA
4.5
4.7
4.9
V
VDR_UVLO_HYS
200
VDR_LDO
150
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Rev 1.0
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400
mV
600
mV
PI3755-01
Electrical Characteristics (Cont.)
Specifications apply for the conditions -40°C < TJ < 125°C, external VDR = 5.1 V, VIN = 54 V, VOUT = 44 V, LEXT = 1.5 µH, external CIN = 6 µF, COUT = 6 µF
as shown in the Applications Diagram or Figure 4, unless otherwise noted. All voltage nodes are referenced to PGND unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
General Purpose Amplifier
Open Loop Gain
[4]
96
120
140
dB
Small Signal Gain-Bandwidth
[4]
5
7
12
MHz
-1
1
mV
-0.1
2.5
V
2
V
VDR - 0.2 V
V
20
mV
100
pF
Offset
Common Mode Input Range
Differential Mode Input Range
Common mode voltage = 1 V, inverting gain = -1
Maximum Output Voltage
IDIFF = -1 mA [6]
Minimum Output Voltage
No Load
Capacitive Load for Stable
Operation
[4]
0
Slew Rate
10
[6]
Guaranteed Output Current
-1
V/µs
1
mA
1.734
V
VDR
V
3.6
4.0
V
0.15
V
Transconductance Error Amplifier
Reference
Input Range
EAIN = EAO
VEAIN
1.667
EAIN > VEAIN_OV will trip an Output OVP Fault
1.7
0
Maximum Output Voltage
VEAMAX
GM = 1 ms
Minimum Output Voltage
VEAMIN
GM = 1 ms
0.05
Transconductance
GM
Factory Set
3.4
mS
Zero Resistor
RZEA
Factory Set
5
kΩ
VEAO = 50 mV, VEAIN = 0 V, GM = 17.1 mS
400
µA
VEAO = 2 V, VEAIN = 5 V, GM = 17.1 mS
400
µA
-8
°
80
dB
56
pF
EAO Output Current Sourcing
IEA_SOURCE
EAO Output Current Sinking
IEA_SINK
Output Current Phase Shift
at 1 MHz
GM = 17.1mS [4]
Open Loop Gain
ROUT > 1 MΩ [4]
Input Capacitance [4]
3.35
70
CEAIN
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PI3755-01
Electrical Characteristics (Cont.)
Specifications apply for the conditions -40°C < TJ < 125°C, external VDR = 5.1 V, VIN = 54 V, VOUT = 44 V, LEXT = 1.5 µH, external CIN = 6 µF, COUT = 6 µF
as shown in the Applications Diagram or Figure 4, unless otherwise noted. All voltage nodes are referenced to PGND unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.4
1.5
1.6
MHz
Control and Protection
Switching Frequency
FSW
25°C
VEAO Pulse Skip Threshold
VEAO_PST
VEAO to SGND
0.365
0.4
0.45
V
VEAO Overload Threshold
VEAO_OL
VEAO to SGND
3.175
3.3
3.425
V
TOL
VEAO > VEAO_OL
Overload Timeout
Vout Slow Current Limit
VOUT_SCL
10 µs time constant
VEAIN Output Over Voltage
Threshold
VEAIN_OV
VEAIN > VEAIN_OV
Over Temperature Fault Threshold
Over Temperature Restart Hysteresis
VBUS Rising Threshold
1.94
1.0
ms
6
A
2.04
2.14
V
TOTP
[4]
135
°C
TOTP_HYS
[4]
30
°C
VBUS
VBUS Fall Threshold
VBUS Discharge Current
VBUS >5 V discharge current = CC; else 500 Ohms resistive
VOUT Negative Fault Threshold
0.95
1.05
1.1
V
0.85
0.95
1.05
V
8
10
15
mA
-0.35
-0.25
-0.15
V
1.7
V
70
mV
Soft Start and Tracking Function
[4]
TRK Active Range
0
TRK Disable Threshold
20
45
[4]
TRK Internal Capacitance
56
Soft Start Charge Current
30
Soft Start Discharge Current
VTRK = 0.5 V
Soft Start Time
Ext CSS = 0.22 µF, 0 A < IOUT ≤ 4.4 A
50
pF
70
µA
9
mA
8.0
ms
Enable
Enable High Threshold
ENIH
0.9
1
1.1
V
Enable Low Threshold
ENIL
0.7
0.8
0.9
V
ENHYS
100
200
300
mV
Enable Threshold Hysteresis
Enable Pin Bias Current
VEN = 0 V or VEN = 2 V
±50
µA
Enable Pull-up Voltage
Floating
2.0
V
30
ms
½ VDR
V
Fault Restart Delay Time
tFR_DLY
Digital Signals
SYNCIN High Threshold
SYNCINIH
SYNCOUT High
SYNCOUTOH
ISYNCOUT = 1 mA
SYNCOUT Low
SYNCOUTOL
VDR - 0.5
VDR
V
ISYNCOUT = 1 mA
0.5
V
FLT High Leakage
FLTILH
VFLT =VDR
10
µA
FLT Output Low
FLTOL
IFLT = 4 mA
0.4
V
[4]
[5]
[6]
[7]
Guaranteed by design but not tested in production.
Input current during an output short circuit is a function of the fault restart duty cycle.
The general purpose amplifier is disabled when the regulator is disabled, and VDIFF pin is internally grounded when disabled.
Steady state output current may be limited by the module temperature.
Refer to figures 27, 28 and 29 for thermal derating and the Over Temperature Protection section.
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PI3755-01
Typical Characteristics[4]
1.75
Switching Frequency (MHz)
100
99
Efficiency (%)
98
97
96
95
94
93
92
91
1.5
1.25
1
0.75
0.5
90
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
VIN = 38 V
4.5
100
4
99
2.5
3
3.5
VIN = 54 V
VIN = 48 V
VIN = 60 V
98
Efficiency (%)
3.5
3
2.5
2
1.5
1
97
96
95
94
93
92
0.5
91
0
90
0
0.5
1
1.5
2
2.5
3
0
3.5
0.5
1
VIN = 38 V
VIN = 54 V
VIN = 48 V
1.5
2
2.5
3
3.5
4
Load Current (A)
Load Current (A)
VIN = 38 V
VIN = 60 V
VIN = 54 V
VIN = 48 V
VIN = 60 V
Figure 4 — Efficiency vs. Output Current @ VOUT = 28 V
Figure 3 — Total Power Loss (includes inductor) vs. Output Current
@ VOUT 44 V
5
Power Dissipation (W)
1.75
Switching Frequency (MHz)
2
Figure 2 — Switching Frequency vs. Output Current @ VOUT 44 V
Figure 1 — Efficiency @ VOUT = 44 V vs. Output Current
Power Dissipation (W)
VIN = 38 V
VIN = 60 V
VIN = 54 V
VIN = 48 V
1.5
Load Current (A)
Load Current (A)
1.5
1.25
1
0.75
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
VIN = 38 V
VIN = 48 V
1
1.5
2
2.5
3
3.5
4
Load Current (A)
Load Current (A)
VIN = 54 V
VIN = 38 V
VIN = 60 V
Figure 5 — Switching Frequency vs. Output Current @ VOUT = 28 V
VIN = 48 V
VIN = 54 V
VIN = 60 V
Figure 6 — Total Power Loss (includes inductor) vs. Output Current
@ VOUT = 28 V
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PI3755-01
Typical Characteristics (Cont.)
1.75
Switching Frequency (MHz)
100
99
Efficiency
98
97
96
95
94
93
92
91
1.5
1.25
1
0.75
0.5
90
0
0.5
1
1.5
2
2.5
3
0
0.5
Load Current (A)
VIN = 38 V
VIN = 48 V
VIN = 60 V
VIN = 54 V
VIN = 38 V
Power Dissipation (W)
5
4
3.5
3
2.5
2
1.5
1
0.5
0
1
1.5
2
2.5
3
Load Current (A)
VIN = 38 V
VIN = 48 V
2
2.5
3
VIN = 48 V
VIN = 54 V
VIN = 60 V
Figure 8 — Switching Frequency vs. Output Current @ VOUT = 54 V
4.5
0.5
1.5
Load Current (A)
Figure 7 — Efficiency vs. Output Current @ VOUT = 54 V
0
1
VIN = 54 V
VIN = 60 V
Figure 9 — Total Power Loss (includes inductor) vs. Output Current
@ VOUT = 54 V
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PI3755-01
Functional Description
The PI3755-01 is part of a family of highly integrated ZVS-BuckBoost regulators. The PI3755-01 output voltage is set with a resistive
divider. Performance and maximum output current are
characterized with a specific external power inductor as defined in
the electrical specifications.
LEX T_PW R
Vin
VIN
VS1
VS2
VOUT
Cin
PGND
5.1V
Rflt
Ccomp
FT5
PI3755-01
VDR
FLT
10x10
ENABLE
COMP
SYNC OUT
SYNC IN
SGND
FT1 – FT4
PGND
Vout
Cout
Rtop
Rbot
LGH
VSN
VSP
VDIFF
EAIN
SS/TRK
EAO
Ceao
Figure 10 — ZVS-Buck-Boost with required components.
For basic operation, Figure 10 shows the minimum connections and
components required.
Inductor Pairing
Operation and characterization of the PI3755-01 was performed
using a 1.5uH inductor, Eaton part # HCV1206-1R5-R , manufactured
by Eaton. This inductor has a form factor of 12.7 mm x 10.15 mm x
5.1 mm. No other inductor is recommended for use with the
PI3755-01. For additional inductor information and sourcing please
contact Eaton directly.
External 5V Bias Supply
The VDR pin of the PI3755-01 requires an external voltage of 5.0 VDC
(5.1 VDC recommended) to power the gate drive and logic circuits.
During startup the external VDR regulator must be disabled or track
VIN, until VIN exceeds the expected VDR voltage. The VDR pin is precharged through an internal linear regulator which is set to 4.5 VDC
nominal and is sourced from VIN. The externally applied VDR must
not exceed VIN by more than 0.3 VDC at any time or damage to the
device may result.
Enable
The ENABLE pin of the regulator is referenced to SGND and permits
the user to turn the regulator on or off. The ENABLE polarity is a
positive logic assertion. If the ENABLE pin is left floating or asserted
high, the regulator output is enabled. When the ENABLE pin is
asserted low the regulator will complete the current switching cycle,
discharge the SS/TRK pin and enter a low power state until the
ENABLE pin is released. The FLT pin also requires an external pull-up
to enable regulator operation.
Switching Frequency Synchronization
The SYNCIN input allows the user to synchronize the controller
switching frequency to the falling edge of an external clock
referenced to SGND. The external clock can synchronize the unit
between 50% and 110% of the preset switching frequency (FSW). The
SYNCIN pin should be connected to SGND when not in use, and
should never be left floating.
Soft-Start and Tracking
The PI3755-01 provides a soft start and tracking feature using the
SS/TRK pin. Programmable Soft Start requires an external capacitor
from the SS/TRK pin to SGND in addition to the internal 56pF softstart capacitor to set the start-up ramp period. The PI3755-01 output
will proportionately follow the TRK pin when it is below 1.7 VDC. If
the TRK pin is asserted below the disable threshold, the regulator will
finish the active switching cycle and then stop switching until the
TRK pin voltage is above the disable threshold.
Remote Sensing Differential Amplifier
A general purpose operational amplifier is provided to assist with
differential remote sensing and or level shifting of the output
voltage. This amplifier is enabled or disabled with the regulator
ENABLE pin and the VDIFF pin is internally grounded when
disabled, ensuring a defined output state. The VDIFF pin can be
connected to the transconductance error amplifier input EAIN pin,
or with proper configuration can also be connected to the EAO pin to
drive the modulator directly.
Bidirectional Fault Pin
The PI3755-01 FLT pin functions as a bidirectional fault indicator and
startup control pin for a VTM3 device. The FLT pin is configured as
an open drain and is active low during a fault or VBUS_HI condition.
The FLT pin is also an input and a low value on this pin will disable
the regulator. The FLT pin should have a 10K pull-up to VDR or to the
TM pin of a VTM3 series device.
Output Current Limit Protection
PI3755-01 has three methods implemented to protect from output
short circuit or over current condition.
Slow Current Limit protection: prevents the output from sourcing
current higher than the regulator’s maximum rated current. If the
output current exceeds the Vout Slow Current Limit (VOUT_SCL) the
FLT pin is asserted immediately, the regulator will complete the
current switching cycle and stop, eliminating output current flow.
After Fault Restart Delay (tFR_DLY), a soft-start cycle is initiated. This
restart cycle will be repeated indefinitely until the excessive
load is removed.
Fast Current Limit protection: monitors the inductor current pulseby-pulse to prevent the regulator from supplying very high output
current. If the inductor current exceeds the Fast Current Limit
threshold, the FLT pin is asserted immediately, the regulator will
complete the current switching cycle and stop, eliminating output
current flow. After Fault Restart Delay (tFR_DLY), a soft-start cycle is
initiated. This restart cycle will be repeated indefinitely until the
fault condition is removed.
Overload Timeout protection: If the regulator is providing excessive
output power for longer than the Overload Timeout delay (TOL), the
FLT pin is asserted immediately, the regulator will complete the
current switching cycle and stop, eliminating output current flow.
After Fault Restart Delay (tFR_DLY), a soft-start cycle is initiated. This
restart cycle will be repeated indefinitely until the overload
is removed.
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PI3755-01
Input Under-Voltage Lockout
If VIN falls below the input Under Voltage Lockout (UVLO) threshold
the PI3755-01 will complete the current switching cycle, and stop.
The regulator will restart once the input voltage is reestablished and
after a Fault Restart Delay.
Input Over-Voltage Lockout
If VIN rises above the input Over Voltage Lockout (OVLO) threshold,
the FLT pin is asserted immediately, the regulator will complete the
current switching cycle and stop. The regulator will restart once the
input voltage is reestablished and after a Fault Restart Delay (tFR_DLY).
Variable Frequency Operation
The PI3755-01 is preprogrammed to a fixed, maximum base
operating frequency. The frequency is selected with respect to the
required power stage inductor to operate at peak efficiency across
line and load variations. The switching frequency period will stretch
as needed during each cycle to accommodate low line and or high
load conditions. By stretching the switching frequency period, thus
decreasing the effective switching frequency, the ZVS operation is
preserved throughout the input line voltage range maintaining
optimum efficiency.
Output Over Voltage Protection
The PI3755-01 is equipped with two methods of detecting an output
over voltage condition. Output Over Voltage Protection (OVP) is
provided to prevent damage to downstream input voltage sensitive
devices. If the output voltage exceeds 20% of its set regulated value
as measured by the EAIN pin (VEAIN_OV), the FLT pin is asserted
immediately, the regulator will complete the current switching cycle
and stop. Also if the output voltage of the regulator exceeds the VOUT
Over Voltage Threshold (VOUT_OVT), indicating a possible open-loop
condition has occurred then the FLT pin is asserted immediately, the
regulator will complete the current switching cycle and stop. The
regulator will resume operation once the output voltage falls below
the OVP threshold and after a Fault Restart Delay (tFR_DLY).
Over Temperature Protection
The PI3755-01 has two modes of protection to prevent internal
components from exceeding their maximum temperature. The first
mode is based on controller temperature alone and if the Over
Temperature Protection threshold is exceeded (TOTP), the regulator
will complete the current switching cycle, enter a low power mode,
pull down on the FLT pin, and will soft-start when the internal
temperature decreases by more than the Over Temperature Restart
Hysteresis (TOTP_HYS). A second mode of protection is based on a
combination of controller temperature and output power. Operation
outside of the published thermal derating curves for more than a few
msec may trip this mode of protection. In this mode, the regulator
will complete the current switching cycle, enter a low power mode,
pull down on the FLT pin and stop. The regulator will soft-start after
a 30 msec Fault Restart Delay.
Pulse Skip Mode (PSM)
PI3755-01 features a hysteretic Pulse Skip Mode to achieve high
efficiency at light loads. The regulator is setup to skip pulses if VEAO
falls below the Pulse Skip Threshold (VEAO_PST). Depending on
conditions and component values, this may result in single pulses or
several consecutive pulses followed by skipped pulses. Skipping
cycles significantly reduces gate drive power and improves light load
efficiency. The regulator will leave Pulse Skip Mode once the control
node rises above the Pulse Skip Mode threshold (VEAO_PST).
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PI3755-01
Applications Information
The PI3755-01 is intended for use as a regulation stage in a
Factorized Power Architecture™ (FPA) system. The PI3755-01 is
optimized for high voltage CPU & DDR applications. As such, the
internal error amplifier is optimized for low noise rather than speed
since these type of applications typically use a VR controller that
overrides the internal error amplifier output through a special level
shifting circuit.
Buck Boost Configuration of EAIN Pin
When using the PI3755-01 a resistive divider is required to define the
output voltage and should be connected between the output voltage
regulation point and the EAIN pin of the PI3755-01 and the SGND
terminal. The PI3755-01 will regulate the output voltage in order to
maintain the EAIN pin at 1.7 V. Typically a small capacitor of 56 pF is
recommended from EAIN to SGND to filter out high frequencies
from the control loop. The components connecting to EAIN and
SGND should be placed close to the regulator, and the EAIN signal
should not be routed long distances or near noise coupling sources.
Buck Boost Configuration of EAO Pin
The PI3755-01 contains a high performance transconductance
amplifier for control loop compensation. A 56 pF capacitor from EAO
to SGND is required to set the high frequency pole. The components
connecting to EAO and SGND should be placed close to the regulator,
and the EAO signal must not be routed long distances or near noise
coupling sources.
Stability Considerations
The PI3755-01 powertrain small signal (plant) response consists of a
single pole determined by the load resistance, the powertrain
equivalent output resistance, and the total output capacitance
(internal and external to the module). Both the modulator gain and
the equivalent output resistance vary as a function of line, load,
output voltage and mode of operation. When the load increases
within a given mode of operation (discontinuous or critical
conduction mode), the power train pole moves to a higher frequency
relative to where it was at the previous load. As a result, the closed
loop crossover frequency will increase with higher load and decrease
with lower load within each mode of operation, with the highest
crossover frequency occurring at the boundary between
discontinuous and critical conduction mode. Figure 5 shows a
reference AC small-signal model. The output voltage set point is a
function of the voltage reference and the output voltage sense ratio.
With reference to Figure 6, R1 and R2 form the output voltage
sensing divider which provides the scaled output voltage to the
negative input of the error amplifier; a dedicated reference IC
provides the reference voltage to the positive input of the
error amplifier.
Under normal operation, the error amplifier will keep the voltages at
the inverting and non-inverting inputs equal, and therefore the
output voltage is defined by:
VOUT = VVID •
R1 + R2
R2
Buck Boost Configuration of COMP Pin
The PI3755-01 contains a high performance transconductance
amplifier for control loop compensation. A 4.7 nF capacitor from
COMP to SGND is required to set the compensation mid band zero
and pole pair. The components connecting to COMP and SGND
should be placed close to the regulator, and the COMP signal must
not be routed long distances or near noise coupling sources.
Note that the component R1 will also factor into the compensation as
described in a later section.
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PI3755-01
VIN
rEQ_IN
CIN_INT
gIN*VEAO
VOUT
gMOD*VEAO
rEQ_OUT
COUT_INT
Figure 11 — PI3755-01 AC Small Signal Model
C2
COMP
R3
Vout
FB
R1
R2
C1
Level Shift
A(s)
VID +
+
A(s)
-
EAO
Error Amplifier
3V Reference
PRM_VOUT
ZVS_BB
G_PRM
COUT_EXT
3V
Figure 12 — PI3755-01 Using External Error Amplifier And Level Shift Circuit
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PI3755-01
In order to properly compensate the control loop, all components
which contribute to the closed loop frequency response should be
identified and understood. Figure 5 shows the AC small signal model
for the module. Modulator DC gain Gmod and powertrain equivalent
resistance rEQ_OUT are shown. These modeling parameters will
support a design cut-off frequency up to 50 kHz. Standard Bode
analysis should be used for calculating the error amplifier
compensation and analyzing the closed loop stability. The
recommended stability criteria are as follows:
1. Phase Margin > 45º : for the closed loop response, the phase
should be greater than 45º where the gain crosses 0 dB.
n Compensation Pole:
1
FP2 =
R3 • C1• C2
2π•
C1+ C2
and for FP2 >>FZ1 (C1 + C2 ≈ C1 ):
FP2 =
1
(3)
2 π • R3 • C2
2. Gain Margin > 10 dB : The closed loop gain should be lower than 10 dB where the phase crosses 0º.
Midband Gain Design (R1,R3):
With reference to Figure 7: curve ABC is the:
3. Gain Slope = -20 dB / decade : The closed loop gain should have a
slope of -20 dB / decade at the crossover frequency.
n minimum output voltage in the application
The compensation characteristics must be selected to meet these
stability criteria. Refer to Figure 7 for a local sense, voltage-mode
control example based on the configuration in Figure 6. In this
example, it is assumed that the maximum crossover frequency
(FCMAX ) has been selected to occur between B and C. Type-2
compensation (Curve IJKL) is sufficient in this case.
The following data must be gathered in order to proceed:
n Modulator Gain Gmod
n maximum load
PRM open loop response, and is where the maximum crossover
frequency occurs. In order for the maximum crossover frequency to
occur at the design choice FCMAX, the compensation gain must be
equal and opposite of the powertrain gain at this frequency. For
stability purposes, the compensation should be in the Mid-band
(J-K) at the crossover. Using Equation (1), the mid-band gain can be
selected appropriately.
Compensation Zero Design (C1):
With reference to Figure 7: curve EFG is the:
n Powertrain equivalent resistance rEQ
n Internal output capacitance
n maximum output voltage in the application
n External output capacitance value
In the case of ceramic capacitors, the ESR can be considered low
enough to push the associated zero well above the frequency of
interest. Applications with high ESR capacitor may require a
different type of compensation (Type-3), or cascade control.
The system poles and zeros of the closed loop can then be defined
as follows:
n minimum input voltage expected in the application
n minimum load in the application PRM open loop response, and is
where the minimum crossover frequency FCMIN occurs. Based on
stability criteria, the compensation must be in the mid-band at the
minimum crossover frequency, therefore FCMIN will occur where
EFG is equal and opposite of GMB . C1 can be selected using
Equation (2) so that FZ1 occurs prior to FCMIN .
High Frequency Pole Design (C2):
Using Equation (3), C2 should be selected so that FP2 is at least one
decade above FCMAX and prior to the gain bandwidth product of the
operational amplifier (10 MHz for this example). For applications
with a higher desired crossover frequency the use of a high gain
bandwidth product amplifier may be necessary to ensure that the
real pole can be set at least one decade above the maximum
crossover frequency.
n Powertrain pole, assuming the external capacitor ESR
can be neglected:
rEQ_OUT • RLOAD
RCOUT_EXT <<
n maximum input voltage expected in the application
rEQ_OUT + RLOAD
n Main pole frequency:
1
FP ~
~
2π•
rEQ_OUT • RLOAD
rEQ_OUT + RLOAD
(
)
• COUT_INT + COUT_EXT
n Compensation Mid-Band Gain:
GMB = 20 log
R3
(1)
R1
Verifying Stability:
The preferred method for verifying stability is to use a network
analyzer, measuring the closed loop response across various lines
and load conditions. In the absence of a network analyzer, a load step
transient response can be used in order to estimate stability. Figure 8
illustrates an example of a load step response. Equation (4) can be
used to predict the phase margin based on the ratio of the “kick” to
“droop” (as defined in Figure 8).
n Compensation Zero:
FZ1 =
( )
( )
1n
1
(2)
2 π • R3• C1
Φm ~
~ 100
k
1n
d
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k
d
2
(4)
2
+π
2
PI3755-01
Open Loop Gain vs. Frequency
80
10MHz GBW
60
I
Compensation Gain
40
Gain (dB)
F
E
PRM Open Loop
PR
op
p Min Load
20
B
A
PRM Open Loop Max Load
J
K
L
FCMIN
0
FCMAX
-20
C
G
-40
Frequency (Hz)
Figure 13 — Reference asymptotic Bode plot for the considered system
Rline >
Lline
(C
IN_INT
k
+ CIN_EXT
)• r
(5)
EQ_IN
Vout
(6)
Rline << rEQ_IN
d
time
Iout
time
Figure 14 — Load step response example and “droop” vs. “kick” definition
Input filter stability:
The PI3755-01 PRM can provide very high dynamic transients. It is
therefore very important to verify that the voltage supply source as
well as the interconnecting line are stable and do not oscillate. For
this purpose, the converter dynamic input impedance magnitude
rEQ_IN is provided in the performance section. It is recommended to
provide adequate design margin with respect to the stability
conditions illustrated in the previous section.
Inductive source and local, external input decoupling capacitance
with negligible ESR (i.e.: ceramic type)
The voltage source impedance can be modeled as a series R (line) L
(line) circuit. The high performance ceramic decoupling capacitors
will not significantly damp the network because of their low ESR;
therefore in order to guarantee stability the following conditions
must be verified:
It is critical that the line source impedance be at least an octave
lower than the converter’s dynamic input resistance, Equation (6).
However, Rline cannot be made arbitrarily low otherwise
Equation (5) is violated and the system will show instability, due to
under-damped RLC input network.
Inductive source and local, external input decoupling capacitance
with significant RCIN_EXT ESR (i.e.:electrolytic type)
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor Lline . Notice that,
the high performance ceramic capacitors CIN_INT within the PI375501 PRM should be included in the external electrolytic capacitance
value for this purpose. The stability criteria will be:
(7)
rEQ_IN > RCIN_EXT
Lline
CIN_INT • RCIN_EXT
< rEQ_IN
(8)
Equation (8) shows that if the aggregate ESR is too small – for
example by using very high quality input capacitors (CIN_EXT) – the
system will be under-damped and may even become destabilized.
Again, an octave of design margin in satisfying Equation (7) should
be considered the minimum.
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PI3755-01
Design and Performance Section[4]
Low Power State
Low Power State
Ready
Fault Steering
Restart Delay
Latched Fault
STATE
. 0
STATE
. 1
STATE
. 2
STATE
. 3
STATE
. 4
STATE 5
OPERATE
BUS _DSCH
4.0V
VTM Fault–
FLTB Low
StepLoad
PRM Delayed
Restart Fault
PRM UVLO Fault
PRM OVLO
Latched Fault
Toggle EN to
Restart
2.0V
0V
-2.0V
-4.0V
V( VIN)/10
V ( VLOAD)
V( PRM_EAO )
V( PRM_ FLT ) - 4
V( PRM_ EN ) - 4
Time
Figure 15 — PRM-VTM Mode Fault Logic Using PI3755-01
gin vs. Output Current vs. V(EAO) VOUT = 28 V
gmod vs. Output Current vs. V(EAO) VOUT = 28 V
6.00
8.00
7.00
4.00
6.00
3.00
5.00
4.00
2.00
3.00
2.00
1.00
1.00
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0.00
3.50
2.00
5.00
1.50
4.00
1.00
3.00
2.00
0.50
1.00
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
V(EAO) Volts
V(EAO) Volts
IOUT @ VIN = 38 V
gIN @ VIN = 38 V
IOUT @ VIN = 38 V
gIN @ VIN = 38 V
IOUT @ VIN = 44 V
gIN @ VIN = 44 V
IOUT @ VIN = 44 V
gIN @ VIN = 44 V
IOUT @ VIN = 48 V
gIN @ VIN = 48 V
IOUT @ VIN = 48 V
gIN @ VIN = 48 V
IOUT @ VIN = 54 V
gIN @ VIN = 54 V
IOUT @ VIN = 54 V
gIN @ VIN = 54 V
IOUT @ VIN = 60 V
gIN @ VIN = 60 V
IOUT @ VIN = 60 V
gIN @ VIN = 60 V
Figure 16 — AC Small Signal Modulator Gain VOUT = 28 V
Figure 17 — AC Small Signal GIN @ VOUT = 28 V
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0.00
3.50
gIN S
9.00
5.00
Output Current DC Amps
10.00
gmod dBS
Output Current DC Amps
6.00
PI3755-01
Design and Performance Section (Cont.)
gmod vs. Output Current vs. V(EAO) VOUT = 44 V
Output Current DC Amps
250
rEQ_IN (OHMS)
8.00
5.00
200
150
100
50
7.00
4.00
6.00
5.00
3.00
4.00
3.00
2.00
2.00
1.00
1.00
0.00
0.00
-1.00
0.00
0
0.0
0.5
1.0
1.5
2.0
2.5
req_VIN = 54 V
req_VIN = 44 V
req_VIN = 60 V
Figure 18 — rEQ_IN @ VOUT = 28 V
1.50
2.00
2.50
3.00
3.50
IOUT @ VIN = 38 V
gmod @ VIN = 38 V
IOUT @ VIN = 44 V
gmod @ VIN = 44 V
IOUT @ VIN = 48 V
gmod @ VIN = 48 V
IOUT @ VIN = 54 V
gmod @ VIN = 54 V
IOUT @ VIN = 60 V
gmod @ VIN = 60 V
Figure 19 — AC Small Signal Modulator Gain VOUT = 44 V
gin Output Current vs. V(EAO) VOUT = 44 V
5.00
2.50
4.00
2.00
3.00
1.50
2.00
1.00
1.00
0.50
rEQ_IN vs. Output Current VOUT = 44 V
180
160
rEQ_IN (OHMS)
140
gIN S
120
100
80
60
40
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0.00
3.50
20
0
V(EAO) Volts
0.0
IOUT @ VIN = 38 V
gIN @ VIN = 38 V
IOUT @ VIN = 44 V
gIN @ VIN = 44 V
IOUT @ VIN = 48 V
gIN @ VIN = 48 V
IOUT @ VIN = 54 V
gIN @ VIN = 54 V
IOUT @ VIN = 60 V
gIN @ VIN = 60 V
6.00
3.00
4.00
3.00
2.00
2.00
1.00
0.00
1.00
-1.00
-2.00
3.00
3.50
gmod dBS
5.00
Output Current DC Amps
4.00
2.50
3.0
req_VIN = 38 V
req_VIN = 54 V
req_VIN = 44 V
req_VIN = 60 V
gin Output Current vs. V(EAO) VOUT = 54 V
7.00
2.00
2.5
4.00
8.00
1.50
2.0
Figure 21 — rEQ_IN @ VOUT = 44 V
gmod Output Current vs. V(EAO) VOUT = 54 V
1.00
1.5
req_VIN = 48 V
5.00
0.50
1.0
Output Current (Amps)
Figure 20 — AC Small Signal GIN @ VOUT = 44 V
0.00
0.00
0.5
3.00
3.50
2.50
3.00
2.00
2.50
1.50
2.00
1.50
1.00
1.00
0.50
0.50
0.00
0.00
0.50
V(EAO) Volts
1.00
1.50
2.00
2.50
3.00
V(EAO) Volts
IOUT @ VIN = 38 V
gmod @ VIN = 38 V
IOUT @ VIN = 38 V
gIN @ VIN = 38 V
IOUT @ VIN = 44 V
gmod @ VIN = 44 V
IOUT @ VIN = 44 V
gIN @ VIN = 44 V
IOUT @ VIN = 48 V
gmod @ VIN = 48 V
IOUT @ VIN = 48 V
gIN @ VIN = 48 V
IOUT @ VIN = 54 V
gmod @ VIN = 54 V
IOUT @ VIN = 54 V
gIN @ VIN = 54 V
IOUT @ VIN = 60 V
gmod @ VIN = 60 V
IOUT @ VIN = 60 V
gIN @ VIN = 60 V
Figure 22 — AC Small Signal Modulator Gain VOUT = 54 V
Figure 23 — AC Small Signal GIN @ VOUT = 54 V
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0.00
3.50
gin S
Output Current DC Amps
1.00
V(EAO) Volts
req_VIN = 48 V
Output Current DC Amps
0.50
3.0
Output Current (Amps)
req_VIN = 38 V
gmod dBS
rEQ_IN vs. Output Current VOUT = 28 V
300
PI3755-01
Design and Performance Section (Cont.)
rEQ_IN vs. Output Current VOUT = 54 V
VDR Bias vs. Output Current - VOUT = 44 V
140
0.05
0.045
VDR Bias Current (A)
rEQ_IN (OHMS)
120
100
80
60
40
20
0.04
0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
0
0.0
0.5
1.0
1.5
2.0
2.5
0
3.0
0.5
1
3.5
4
I_VDR @ VIN = 38 V
I_VDR @ VIN = 54 V
req_VIN = 60 V
I_VDR @ VIN = 44 V
I_VDR @ VIN = 60 V
I_VDR @ VIN = 48 V
Figure 25 — VDR Bias Current @ VOUT = 44 V
Thermal De-rating @ 28 VOUT,
0 LFM on Picor Eval Board
0.3
Output Load Current (A)
No Load Power Dissipation (W)
3
req_VIN = 54 V
No Load Power Dissipation - VOUT = 44 V
0.25
0.2
0.15
0.1
0.05
0
10
20
30
40
50
60
70
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
25
Input Voltage (V)
50
75
100
125
Ambient Temperature (°C)
Pd @ VOUT = 44 V
VIN = 38 V
VIN = 54 V
VIN = 48 V
VIN = 60 V
Figure 27 — Thermal De-Rating @ VOUT = 28 V [8]
Figure 26 — No Load Power Dissipation @ VOUT = 44 V
Thermal De-rating @ 54 VOUT,
0 LFM on Picor Eval Board
Thermal De-rating @ 44 VOUT,
0 LFM on Picor Eval Board
3.5
3.5
Output Load Current (A)
Output Load Current (A)
2.5
req_VIN = 44 V
Figure 24 — rEQ_IN @ VOUT = 54 V
3
2.5
2
1.5
1
0.5
0
3
2.5
2
1.5
1
0.5
0
25
50
75
100
125
25
50
VIN = 38 V
VIN = 48 V
VIN = 54 V
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
VIN = 38 V
VIN = 60 V
Figure 28 — Thermal De-Rating @ VOUT = 44 V [8]
[8]
2
req_VIN = 38 V
req_VIN = 48 V
0
1.5
Load Current (A)
Output Current (Amps)
VIN = 48 V
VIN = 54 V
Figure 29 — Thermal De-Rating @ VOUT = 54 V [8]
Testing was performed on a 3"x 3" 4 layer PCB with 2oz copper layers.
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VIN = 60 V
PI3755-01
Design and Performance Section (Cont.)
Figure 30 — PI3755-01 Input Ripple 44 VOUT 2.2 A Load Steady State.
Figure 31 — PI3755-01 Output Ripple 44 VOUT 2.2 A Load Steady State
Figure 32 — PI3755-01 Input Ripple 28 VOUT 4 A Load Steady State
Figure 33 — PI3755-01 Output Ripple 28 VOUT 4 A Load Steady State
Figure 34 — PI3755-01 input Ripple 54 VOUT 3 A Load Steady State
Figure 35 — PI3755-01 Output Ripple 54 VOUT 3 A Load Steady State
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PI3755-01
Design and Performance Section (Cont.)
60
Gain (dB)
40
20
0
-20
-40
-60
1000
10000
100000
Frequency (Hz)
Total Loop Gain
Error Amp Gain
PWM Gain
Figure 36 — PI3755-01 Measured AC Gain = 44 VOUT 2 A Load Steady State; RTOP = 42.2 kΩ , RBOT = 1.7 kΩ, CCOMP = 4.7 nF, CEAO = 56 pF, COUT = 6 µF;
See Figure 10
200
Phase (Degrees)
150
100
50
0
-50
-100
-150
-200
1000
10000
100000
Frequency (Hz)
Total Loop Phase
Error Amp Phase
PWM Phase
Figure 37 — PI3755-01 Measured AC Phase = 44 VOUT 2 A Load Steady State; RTOP = 42.2 kΩ , RBOT = 1.7 kΩ, CCOMP = 4.7 nF, CEAO = 56 pF, COUT = 6 µF;
See Figure 10
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PI3755-01
Design and Performance Section (Cont.)
MTBF (Mhrs)
10000
1000
100
10
1
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
MTBF Calculations Over Temperature Using Telcordia SR-332
Figure 38 — PI3755-01 Calculated MTBF Telcordia SR-332 GB
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120
140
PI3755-01
Package Drawings
B
/
bbb C
/
aaa C
4x
3
A2
A
C
E
PIN 1
INDEX
aaa C
SEATING
PLANE
A1
SOLDER MASK
PAD OPENING
DETAIL A
A
D
PACKAGE TOP VIEW
ddd M
eee M
L
DETAIL A
C A B
C
MOLD CAP
2
SEE NOTES
b
ddd M
eee M
C A B
C
L
SUBSTRATE
PACKAGE SIDE VIEW
PAD OPENING
L1
b
DETAIL B
1 SEE NOTES
DATUM A
e
1
DATUM B
e
E1
DETAIL B
SEE NOTES
D1
PIN 1 INDEX
SYMBOL
MIN
NOM
MAX
A
2.49
2.56
2.63
A1
–
–
0.04
A2
–
–
2.59
b
0.50
0.55
0.60
L
0.50
0.55
0.60
D
10.00 BSC
E
10.00 BSC
D1
9.00 BSC
E1
9.00 BSC
e
1.00 BSC
PACKAGE BOTTOM VIEW
L1
NOTES
0.175
0.225
0.275
aaa
0.10
1
‘e’ REPRESENTS THE BASIC TERMINAL PITCH. SPECIFIES THE TRUE
GEOMETRIC POSITION OF THE TERMINAL AXIS.
bbb
0.10
2
DIMENSION ‘b’ APPLIES TO METALLIZED PAD OPENING.
ccc
0.08
3
DIMENSION ‘A’ INCLUDES PACKAGE WARPAGE.
ddd
0.10
4
EXPOSED METALLIZED PADS ARE CU PADS WITH SURFACE FINISH
PROTECTION.
eee
0.08
5
ALL DIMENSIONS IN MILLIMETERS.
DIMENSIONS
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PI3755-01
PI3755-01
Receiving PCB Pattern Design Recommendations
DATUM A
1mm
DATUM B
1mm
E1
DETAIL A
DETAIL B
D1
PIN 1A INDEX
PACKAGE PCB FOOTPRINT TOP VIEW
Exposed
Copper
Package
Outline
Solder Mask
Over Copper
Solder Mask
Over Board
SMD = Soldermask Defined Pads
0.35mm
0.55mm
(SMD)
0.55mm
(SMD)
≥0.5mm
≥0.5mm
0.55mm
(SMD)
0.35mm
≥0.5mm
≥0.5mm
0.35mm
0.65mm
(Cu Pad)
0.55mm
(SMD)
0.55mm
(SMD)
≥0.5mm
0.35mm
0.55mm
(SMD)
≥0.5mm
0.65mm
(Cu Pad)
0.55mm
(SMD)
0.65mm
(Cu Pad)
0.65mm
(Cu Pad)
DETAIL B
DETAIL A
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Package
Outline
PI3755-01
Revision History
Revision
Date
1.0
04/13/15
Description
Initial Release
Page Number(s)
n/a
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PI3755-01
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make
changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and
is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are
used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS
ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH
RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR
PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable
for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes
no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and
operating safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be
returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the
product was defective within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support
devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform
when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the
user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products
and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is
granted by this document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
RE40,072; 6,788,033; 7,154,250; 6,421,262; 8,669,744; and for use under: 6,984,965; 6,975,098.
Vicor Corporation
25 Frontage Road
Andover, MA 01810 USA
Picor Corporation
51 Industrial Drive
North Smithfield, RI 02896 USA
email
Customer Service: [email protected]
Technical Support: [email protected]
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