PRM® Regulator PRM48DH480T250B03 DC to DC Regulator FEATURES DESCRIPTION Optimized for VR12.0 48V (38 to 60 VIN), non-isolated ZVS buck-boost regulator 5 to 55 V adjustable output range Building block for high efficiency DC-DC systems 145W Output Power in 0.57 in2 footprint 97% typical efficiency, at full load 1,342 W/in3 (82 W/cm3) Power Density Enables a 48 V to 1.2 V, 130 A isolated, regulated solution with total footprint of 1.7in2 (11cm2) Flexible “Remote Sense” architecture optimizes regulation / feedback loop design to fit application requirements Current Feedback signal allows dynamic adjustment of current limit setpoint 9.32 MHrs MTBF (MIL-HDBK-217Plus Parts Count) The VI Chip PRM® Regulator is a high efficiency converter, operating from a 38 to 60 Vdc input to generate a regulated 5 to 55 Vdc output. The ZVS Buck – Boost topology enables high switching frequency (~1.5 MHz) operation with high conversion efficiency. High switching frequency reduces the size of reactive components enabling power density up to 1,342 W/in3. TYPICAL APPLICATIONS High Efficiency Server Processor and Memory Power High Density ATE system DC-DC power Telecom NPU and ASIC core power LED drivers High Density Power Supply DC-DC rail outputs Non-isolated power converters The half VI Chip package is compatible with standard pickand-place and surface mount assembly processes with a planar thermal interface area and superior thermal conductivity. In a Factorized Power Architecture™ system, the PRM48DH480T250B03 and downstream VTM™ transformer minimize distribution and conversion losses in a high power solution. An external control loop and current sensor maintain regulation and enable flexibility both in the design of voltage and current compensation loops to control of output voltages and currents. 48 V to 1.2 V, 130A Voltage Regulator PRM® Regulator Rev 1.2 Page 1 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 1.0 ABSOLUTE MAXIMUM RATINGS The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin. 2.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and output voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of 0 ºC < TJ < 125 ºC. PRM® Regulator Rev 1.2 Page 2 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 3.0 SIGNAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of 0 ºC < TJ < 125 ºC. PRM® Regulator Rev 1.2 Page 3 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 PRM® Regulator Rev 1.2 Page 4 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 4.0 FUNCTIONAL BLOCK DIAGRAM +Vin +Vout Vcc PC PR Vout Cin Vcc 3.3V Linear Regulator Internal Vcc Regulator -Vin Cout 3.3V Q3 Q1 uC 8051 RE L -Vout 16V +Vout 9V Q4 Q2 Output Discharge (OD) 8.2V PR Modulator PR 93.3k Enable Var. Vclamp 2.5mA Min VTM Vc Start up pulse 0.5mA 14V VC 10ms Vcc 100uA Q Q SET CLR Fault Logic TOFF delay S Instant latch R R Vout (OV) 5V 2mA max 3V RE Latch after 120us RE 3.3V Vin (OV, UV) Vs 9V 0.01uF Enable PC 10uA PC VPC_EN SG Current Limit Overtemperature Protection TM 3 V @ 27°C VIF_IL Overcurrent Protection Temperature dependent voltage source IF 2130 Vref (130°C) VIF_OC PRM® Regulator Rev 1.2 Page 5 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 HIGH LEVEL FUNCTIONAL STATE DIAGRAM Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles. PRM® Regulator Rev 1.2 Page 6 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 5.0 TIMING DIAGRAMS Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following: Single PRM® (no array) VS powers error amplifier RE powers voltage reference and output current transducer IOUT is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load 2 1 Start up with 1.2V/ms < dVIN/dt < maximum VIN OV TOFF 3 4 Quick OC Input OV (t<TBLNK) Input OV recovery 5 6 PC disable PC release 7 8 Full load Load release and applied Output OV (slow f/b) TON UV 18 V Vpr_max TBLNK Input PR Vpr_min t < TBLNK VIF_OC IFVIF_IL Input / Output TOFF PC TON TOFF TPROT TBLNK Vpc Vpc_en VC Vvc TVC VOUT TPROT OV 1V Output RE TVS_RE TPC_RE TPC_RE Vre_amb TBLNK Vvs_amb VS TM OT Vtm_amb PRM® Regulator Rev 1.2 Page 7 of 23 7/2015 vicorpower.com 800 735.6200 TPC_RE PRM48DH480T250B03 Input Output Input / Output PRM® Regulator Rev 1.2 Page 8 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 6.0 APPLICATIONS CHARACTERISTICS The following figures present typical performance at TC = 25ºC, unless otherwise noted. See associated figures for general trend data. No Load Power Dissipation vs. Line Module Enabled - Nominal VOUT Power Dissipation vs. Line Module Disabled, PC=Low 0.4 Power Dissipation [W] 3.0 2.0 1.0 38 40 42 44 46 48 50 52 54 56 58 0.3 0.2 0.1 60 38 40 42 44 Input Voltage [V] -40 ºC TCASE: 25 ºC 100 ºC 10 8 6 4 2 Efficiency [%] 12 Power Dissipation [W] Efficiency [%] 14 2 2.5 3 38 48 60 3.5 38 4 Rev 1.2 Page 9 of 23 7/2015 58 60 100 ºC 12 10 8 6 4 2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Load Current [A] VIN: 48 25 ºC 14 4.5 60 Figure 3 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 20V, TCASE = -40ºC PRM® Regulator 56 16 0 Load Current [A] VIN: 54 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 0 1.5 52 Efficiency & Power Dissipation TCASE = -40 ºC VOUT = 48 V 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 1 50 Figure 2 - Power dissipation vs. VIN, module disabled Efficiency & Power Dissipation TCASE = -40 ºC VOUT = 20 V 0.5 48 -40 ºC TCASE: Figure 1 - No load power dissipation vs. VIN, module enabled 0 46 Input Voltage [V] Power Dissipation [W] Power Dissipation [W] 4.0 38 48 60 38 48 60 Figure 4 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 48V, TCASE = -40ºC vicorpower.com 800 735.6200 PRM48DH480T250B03 Efficiency & Power Dissipation TCASE = 25 ºC VOUT = 20 V 16 12 10 8 6 4 Efficiency [%] 14 2 1 1.5 2 2.5 3 3.5 14 12 10 8 6 4 2 0 0.5 1 1.5 38 48 60 38 48 VIN: 60 Figure 5 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 55V, TCASE = -40ºC 38 12 10 8 6 4 Efficiency [%] 14 Power Dissipation [W] Efficiency [%] 16 2 1 1.5 2 2.5 3 3.5 4 48 48 60 4.5 48 10 8 6 4 2 0.5 1 8 6 4 Efficiency [%] 10 Power Dissipation [W] Efficiency [%] 12 2 3 38 3.5 4 48 38 48 60 2 2.5 3 3.5 38 Rev 1.2 Page 10 of 23 7/2015 38 48 60 16 14 12 10 8 6 4 2 0 4.5 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Load Current [A] 48 60 Figure 9 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 20V, TCASE = 100ºC PRM® Regulator 60 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Load Current [A] VIN: 1.5 Efficiency & Power Dissipation TCASE = 100 ºC VOUT = 48 V 14 2.5 60 Figure 8 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 55V, TCASE = 25ºC 16 2 48 12 VIN: 60 18 1.5 38 Load Current [A] 38 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 1 60 14 Efficiency & Power Dissipation TCASE = 100 ºC VOUT = 20 V 0.5 4.5 16 0 Figure 7 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 48V, TCASE = 25ºC 0 4 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Load Current [A] 38 VIN: 3.5 Efficiency & Power Dissipation TCASE = 25 ºC VOUT = 55 V 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 0.5 3 Figure 6 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 20V, TCASE = 25ºC Efficiency & Power Dissipation TCASE = 25 ºC VOUT = 48 V 0 2.5 Load Current [A] Load Current [A] VIN: 2 Power Dissipation [W] 0.5 16 Power Dissipation [W] 0 18 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 Power Dissipation [W] 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Power Dissipation [W] Efficiency [%] Efficiency & Power Dissipation TCASE = -40 ºC VOUT = 55 V VIN: 38 48 60 38 48 60 Figure 10 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 48V, TCASE = 100ºC vicorpower.com 800 735.6200 PRM48DH480T250B03 VPR vs. Case Temperature VIN = 48 V; VOUT = 48 V 5.0 16 14 12 10 8 6 4 4.5 0.5 1 1.5 2 2.5 3 4.41 3.15 3.18 2.86 2.5 2.0 -40 3.5 -20 0 Load Current [A] 38 VIN: 48 60 4.08 3.5 3.0 2 0 4.32 4.0 VPR [V] 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 Power Dissipation [W] Efficiency [%] Efficiency & Power Dissipation TCASE = 100 ºC VOUT = 55 V 20 40 60 80 100 Temperature [ºC] 38 48 2.0827 IOUT: 60 Figure 11 – Total efficiency and power dissipation vs. VIN and IOUT, VOUT = 55V, TCASE = 100ºC 4.1673 Figure 12 – Typical control node voltage vs. TCASE, and IOUT; VIN = 48V, VOUT = 48V Powertrain switching frequency and periodic output charge vs. input voltage - Full load 12 fsw 1400 10 1200 8 1000 6 800 4 C 2 600 Total output charge per switching cycle [C] fSW [kHz] 1600 0 400 38 40 42 44 46 48 50 52 54 56 58 60 Input Voltage [V] 20 VOUT: Figure 13 – Typical output voltage ripple waveform, 200 mV/div, 500 ns/div TCASE = 30ºC, VIN = 48V, VOUT = 48V, IOUT = 3.2 A, no external output capacitance. 55 20 48 55 Figure 14 – Powertrain switching frequency and periodic output charge vs. VIN, VOUT; IOUT = 3.2 A Powertrain switching frequency and periodic input charge vs. input voltage - Full load 210 1400 10 5.50 180 1200 8 5.00 150 4.50 120 1000 6 4.00 90 3.50 60 3.00 30 800 4 C 2 600 Output Current [A] fsw Total input charge per switching cycle [C] 6.00 0 400 38 40 42 44 46 48 50 52 54 56 58 2.50 60 VOUT: 48 55 10 15 20 25 30 35 40 45 50 55 Output Voltage [V] Input Voltage [V] 20 0 5 20 48 Figure 15 – Powertrain switching frequency and periodic input charge vs. VIN, VOUT; IOUT = 3.2 A PRM® Regulator Rev 1.2 Page 11 of 23 7/2015 IOUT Continuous POUT Continuous 55 IOUT 5 s POUT 5 s Figure 16 – DC Output Safe Operating Area vicorpower.com 800 735.6200 60 Output Power [W] DC Safe Operating Area 12 1600 fSW [kHz] 48 PRM48DH480T250B03 350 10 89 6 300 8 76 250 6 gPR [dBS] gpr req_out [] 8 4 gPR [dBS] DC modulator gain and powertrain equivalent output resistance vs. output current, VOUT = 20V 2 200 0 150 -2 100 0 50 -2 0 -4 req_out -4 -6 0 0.5 1 1.5 2 2.5 3 gpr 4 50 2 37 3.5 45 11 -2 0 0.5 1 1.5 38 45 60 Figure 17 – Powertrain characteristics vs. IOUT; Resistive load, VOUT = 55V, various VIN 300 4 250 gpr 2 200 0 150 -2 100 req_out 50 Effective capacitance [F] 6 0 -6 1.5 2 2.5 3 3.5 45 38 45 4 4 4.5 60 38 45 60 4 3.5 3 2.5 2 1.5 1 0.5 0 4.5 0 5 10 15 20 25 30 35 40 45 50 55 Voltage [V] 60 38 45 60 Figure 19 – Powertrain characteristics vs. IOUT; Resistive load, VOUT = 48V, various VIN Figure 20 – Effective internal input and output capacitance vs. voltage – ceramic type Powertrain equivalent input resistance vs. output current, VOUT = 55V Output Power vs. VPR VIN = 48V, VOUT = 48V, TC=25ºC 36 200 32 180 Typical min 160 Nominal 28 140 Typical max 24 req_in [ ] Output Power [W] 3.5 4.5 Output Current [A] VIN: 3 Effective internal capacitance vs. applied voltage, Input (CIN_INT) and output (COUT_INT) req_out [] gPR [dBS] 350 1 2.5 Figure 18 – Powertrain characteristics vs. IOUT; Resistive load, VOUT = 20V, various VIN 8 0.5 38 VIN: DC modulator gain and powertrain equivalent output resistance vs. output current, VOUT = 48V 0 2 Output Current [A] 60 -4 24 req_out Output Current [A] 38 VIN: 63 req_out [ ] DC modulator gain and powertrain equivalent output resistance vs. output current, VOUT = 55V 120 100 80 60 20 16 12 8 40 4 20 0 0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0.5 1 VIN: PRM® Regulator Rev 1.2 Page 12 of 23 7/2015 2 2.5 3 3.5 Output Current [A] PR Voltage [V] Figure 21 – Output Power vs. VPR; VIN = 48V, VOUT = 48V, TCASE = 25ºC 1.5 38 45 60 Figure 22 – Magnitude of powertrain dynamic input impedance vs. VIN, IOUT; VOUT = 55V vicorpower.com 800 735.6200 PRM48DH480T250B03 Powertrain equivalent input resistance vs. output current, VOUT = 48V 400 45 350 40 300 35 30 250 req_in [ ] req_in [ ] Powertrain equivalent input resistance vs. output current, VOUT = 20V 200 150 25 20 15 100 10 50 5 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 0 4.5 0.5 1 Output Current [A] VIN: 38 45 1.5 2 2.5 3 3.5 4 4.5 Output Current [A] 60 VIN: Figure 23 – Magnitude of powertrain dynamic input impedance vs. VIN, IOUT; VOUT = 20V 38 45 60 Figure 24 – Magnitude of powertrain dynamic input impedance vs. VIN, IOUT; VOUT = 48V 7.0 GENERAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of 0 ºC < TJ < 125 ºC. GENERAL CHARACTERISTICS Specifications apply over all line and load conditions, and output Voltage from 20V to 55V unless otherwise noted; Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-Grade); All Other specifications are at TJ = 25 ºC unless otherwise noted. Conditions / Notes Attribute Symbol Min MECHANICAL Typ Max Unit Length L 21.8 / [0.86] 22.0 / [0.87] 22.3 / [0.88] mm / [in] Width W 16.3 / [0.64] 16.5 / [0.65] 16.8 / [0.66] mm / [in] Height H Volume Weight Vol W [0.255] No Heatsink Nickel Palladium Gold Lead Finish [0.265] [0.275] mm / [in] cm 3 / [in3] 2.44 / [0.15] 7 g 0.51 0.02 0.003 2.03 0.15 0.050 0 0 125 100 m THERMAL Operating Temperature Operating Case Temperature Thermal Capacity ASSEMBLY Peak Compressive Force Applied to Case (Z-axis) Storage Temperature ESD Rating TJ TC Any operating condition 5 3 5.33 125 Supported by J-Lead only TST ESDHBM ESDCDM Human Body Model, "JEDEC JESD 22-A114C.01" Charged Device Model, "JEDEC JESD 22-C101D" -40 1000 400 ºC ºC Ws/ºC lbs lbs / in 2 ºC V SOLDERING Peak Temperature During Reflow MSL 4 (Datecode 1528 and later) 245 Maximum Time Above [217] ºC Peak Heating Rate During Reflow Peak Cooling Rate Post Reflow 1.5 2.5 150 2 3 ºC ºC s ºC / s ºC / s SAFETY and RELIABILITY MTBF Agency Approvals / Standards Telcordia Issue 2 - Method I Case 1; Ground Benign, Controlled MIL-HDBK-217Plus Parts Count - 25C Ground Benign, Stationary, Indoors / Computer Profile C TUV US CE Mark CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable PRM® Regulator Rev 1.2 Page 13 of 23 7/2015 vicorpower.com 800 735.6200 5.41 6.22 MHrs MHrs PRM48DH480T250B03 PRODUCT OUTLINE DRAWING AND RECOMMENDED PCB FOOTPRINT PRM® Regulator Rev 1.2 Page 14 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 highest at full load and lowest at minimum load. Figure 25 shows a reference AC small-signal model. 8.0 PRODUCT DETAILS AND DESIGN GUIDELINES 8.1 Control pins description and characteristics Current feedback (IF) is the input for the module output overcurrent protection and current limit features (see functional block diagram in section 4.0). A voltage proportional to the powertrain output current must be applied to IF in order for overcurrent protection to operate properly. If the IF voltage exceeds the IF pin’s overcurrent protection threshold, the powertrain will stop switching. If the IF voltage falls below the overcurrent protection threshold within TBLANK time, then the powertrain will immediately resumes switching. Otherwise a fault is latched. The current limit threshold for the IF pin is set lower than the protection threshold. When the IF pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amplifier which overrides the modulator input maximum level. This causes the powertrain to maintain a constant output current. The bandwidth of this current limit integrator is significantly slower than that of the PR control node input. Therefore this current limit can not be used in lieu of properly compensating the (external) PR control loop to avoid exceeding maximum current or power ratings for the device. If the IF pin is not driven, it must be resistively terminated to SG. A 1k resistor to SG is recommended in this case. Control node (PR) is the input to the control node which determines the powertrain timing and ultimately the module output power (Figure 21). An internal 0.5mA current sink is always active. The bi-directional buffer between PR and the control node has two states. In normal operation, PR will be above the 0.79V switching threshold, and will drive the control node through the buffer. An internal 7.4V clamp determines the maximum output power that can be requested of the modulator. When PR falls below 0.79 V, the converter will stop switching. An internal circuit clamps the modulator input control node to 0.79 V, and a buffer will source up to 2.5 mA out of the pin at that clamp level. For this reason, the output impedance of the amplifier driving PR must be taken into account. A rail-to-rail operational amplifier with low output impedance is always recommended. The powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). Both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage, as shown in Figures 17, 18 and 19. As the load increases, the powertrain pole moves to higher frequency. As a result, the closed loop crossover frequency will be the + PRM48DH480T250B03 CIN_INT VIN rEQ_IN VPR · GIN + + VPR + RPR IPR_Low - VPR · GPR COUT_INT rEQ_OUT VOUT - Figure 25 – PRM48DH480T250B03 AC small signal model PRM® Regulator Rev 1.2 Page 15 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 VTM Control (VC) pin supplies an initial VCC voltage to downstream VTMs, enabling them and synchronizing their startup with the PRM®. The VCC voltage is a pulse, typically 10 ms duration at 14 V. If VC is not loaded by a VTM, it must be terminated with a 1 kresistor to –VOut. Primary Control (PC) is both an input and an output. It can provide the following features: • Delayed start: upon application of voltage (>UVLO) to the module power input and after TOFF, the PC pin will source a constant 90 μA current. • Output disable: PC may be pulled down externally in order to disable the module. Pull down resistance should be less than 300 μ to SG. • Fault detection flag: The PC 5 V voltage source is internally turned off when a fault condition is latched. Note that aside from the Short Circuit fault condition, PC does not have significant current sinking capability. Therefore in the case of an array of PRMs with interconnected PC pins, PC does not in general reflect the fault state of all PRMs. The common PC line will not disable neighboring modules when a fault is detected except for a latched Output Short Circuit fault. Conversely any unit in the array latching a Short Circuit fault will disable the array for TSCR. Signal Ground (SG) pin provides a Kelvin connection to the PRM’s internal signal ground. It should be used as the reference for PR, TM, IF, and should return all PC, VS and RE pin currents. In array configurations with common ground control circuits, a series resistor (~1 ) is recommended in order to decouple power and signal current returns. 8.2 Control circuit requirements and design procedure The PRM48DH480T250B03 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. These two external circuits are illustrated in Figure 26, which shows an example of the PRM in a standalone application with local voltage feedback and high side current sensing. In general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense IC. The following design procedures refer to the circuit shown in Figure 26. 8.2.1 Setting the output voltage level Temperature Monitor (TM) pin outputs a voltage proportional to the absolute temperature of the converter analog control IC. It can be used to accomplish the following functions: • Monitor the control IC temperature: The gain and setpoint of TM are such that the temperature, in Kelvin, of the PRM controller IC is equal to the voltage on the TM pin scaled by 100. (i.e. 3.0 V = 300 K = 27 ºC). • Closed loop thermal management at the system level (e.g. variable speed fans or coolant flow) • Fault detection flag: The TM voltage source is turned off as soon as a fault is detected. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of TM. The output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. With reference to Fig. 26, R1 and R2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference IC provides the reference voltage to the positive input of the error amplifier. Under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by: Reference Enable (RE) pin outputs a regulated 3.3 V, 8 mA voltage source. It is enabled only after successful startup of the PRM powertrain (see chapters 5.0 and 6.0.) RE is intended to power the output current transducer and also the voltage reference for the control loop. Powering the reference generator with RE helps provide a controlled startup, since the output voltage of the system is able to track the reference level as it comes up. Note that the component R1 will also factor into the compensation as described in a later section. Voltage Source (VS) pin outputs a gated (e.g. mirrors PC status), non-isolated, regulated 9 V, 5 mA voltage source. It can be used to power external control circuitry; it always leads RE. PRM® Regulator Rev 1.2 Page 16 of 23 7/2015 VOUT Vref R1 R 2 R2 It is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. The recommended range for reference rise time is 1 ms to 9 ms. The lower rise time limit will ensure optimized modulator timing performance during startup, and to allow the current limit feature (through IF pin) to fully protect the device during power-up. The upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream VTM input before the end of the VC pulse. vicorpower.com 800 735.6200 PRM48DH480T250B03 8.2.2 Setting the output current limit and overcurrent protection level The current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense amplifier. The output of the current sense IC provides the IF voltage which has VIF_IL and VIF_OC thresholds for the two functions respectively. The set points are therefore defined by: I IL VIF _ IL RS GCS Powertrain equivalent resistance rEQ: See Figures 17, 18, 19 Internal output capacitance: see Figure 20 External output capacitance value In the case of ceramic capacitors, the ESR can be considered low enough to push the associated zero well above the frequency of interest. Applications with high ESR capacitor may require a different type of compensation, or cascade control. The system poles and zeros of the closed loop can then be defined as follows: Powertrain pole, assuming the external capacitor ESR can be neglected: and I OC VIF _ OC RCOUT _ EXT RS GCS where GCS is the gain of the current sense amplifier. 8.2.3 Control loop compensation requirements 1) Phase Margin > 45º : for the closed loop response, the phase should be greater than 45º where the gain crosses 0dB. 2) Gain Margin > 10dB : The closed loop gain should be lower than -10dB where the phase crosses 0º. 3) Gain Slope = -20dB / decade : The closed loop gain should have a slope of -20dB / decade at the crossover frequency. The compensation characteristics must be selected to meet these stability criteria. Refer to Figure 27 for a local sense, voltage-mode control example based on the configuration in Figure 26. In this example, it is assumed that the maximum crossover frequency (FCMAX) has been selected to occur between B and C. Type-2 compensation (Curve IJKL) is sufficient in this case. The following data must be gathered in order to proceed: Modulator Gain GPR: See Figures 17, 18, 19 PRM® Regulator Rev 1.2 Page 17 of 23 7/2015 rEQ _ OUT RLOAD Main pole frequency: FP In order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. Figure 25 shows the AC small signal model for the module. Modulator DC gain GPR and powertrain equivalent resistance rEQ_OUT are shown. These modeling parameters will support a design cut-off frequency up to 50 kHz. Standard Bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. The recommended stability criteria are as follows: rEQ _ OUT RLOAD 1 2 π rEQ _ OUT RLOAD rEQ _ OUT RLOAD Compensation Mid-Band Gain: G MB 20 log R3 R1 [1] Compensation Zero: FZ1 COUT _ INT COUT _ EXT 1 2 π R 3 C1 [2] Compensation Pole: FP 2 1 R C C 2 π 3 1 2 C1 C2 and for FP2>>FZ1 (C1 + C2 ≈ C1): FP 2 vicorpower.com 800 735.6200 1 2 R3 C2 [3] PRM48DH480T250B03 8.2.4 8.2.5 Midband Gain Design (R1,R3): Compensation Zero Design (C1): With reference to Figure 27: curve EFG is the: maximum output voltage in the application minimum input voltage expected in the application minimum load in the application PRM open loop response, and is where the minimum crossover frequency FCMIN occurs. Based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore FCMIN will occur where EFG is equal and opposite of GMB. C1 can be selected using Equation [2] so that FZ1 occurs prior to FCMIN. With reference to Figure 27: curve ABC is the: minimum output voltage in the application maximum input voltage expected in the application maximum load PRM® open loop response, and is where the maximum crossover frequency occurs. In order for the maximum crossover frequency to occur at the design choice FCMAX, the compensation gain must be equal and opposite of the powertrain gain at this frequency. For stability purposes, the compensation should be in the Mid-band (J-K) at the crossover. Using Equation [1], the mid-band gain can be selected appropriately. C2 C1 R3 + Vref R2 R1 F1 +IN CIN_EXT CIN_INT -IN Vref Vref IC VS IF RE PR RS +OUT PRM COUT_EXT COUT_INT SG -OUT I sense IC Figure 26 – Control circuit example PRM® Regulator Rev 1.2 Page 18 of 23 7/2015 vicorpower.com 800 735.6200 PRM48DH480T250B03 Open Loop Gain vs. Frequency 80 60 Gain (dB) 40 20 10MHz GBW I Compensation Gain F E PRM Open Loop Min Load B A PRM Open Loop Max Load J K L FCMIN 0 FCMAX -20 C G -40 Frequency (Hz) Figure 27 – reference asymptotic Bode plot for the considered system 8.2.6 based on the ratio of the “kick” to “droop” (as defined in Fig. 28). High Frequency Pole Design (C2): Using Equation [3], C2 should be selected so that FP2 is at least one decade above FCMAX and prior to the gain bandwidth product of the operational amplifier (10MHz for this example). For applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. 8.2.7 Verifying Stability: The preferred method for verifying stability is to use a network analyzer, measuring the closed loop response across various lines and load conditions. In the absence of a network analyzer, a load step transient response can be used in order to estimate stability. Figure 28 illustrates an example of a load step response. Equation [4] can be used to predict the phase margin PRM® Regulator Rev 1.2 Page 19 of 23 7/2015 vicorpower.com 800 735.6200 Figure 28 – load step response example and “droop” vs. “kick” definition PRM48DH480T250B03 Figure 20 provides the effective internal capacitance of the module. A conservative estimate of input and output peakpeak voltage ripple at nominal line and trim is provided by equation [5]: 2 k ln d m 100 2 k 2 ln d [4] QTOT V 8.3 Burst Mode Operation: At light loads, the PRM® will operate in a burst mode due to minimum timing constraints. An example burst operation waveform is illustrated in Figure 29. For very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. In this case the external error amplifier will periodically drive PR below the switching threshold in order to maintain regulation. Switching will cease momentarily until the error amplifier once again drives PR voltage above the threshold. CINT I FL 0.4 f SW C EXT [5] QTOT is the total input (Fig. 15) or output (Fig. 14) charge per switching cycle at full load, while CINT is the module internal effective capacitance at the considered voltage (Fig. 20) and CEXT is the external effective capacitance at the considered voltage. 8.5 Input filter stability The PRM can provide very high dynamic transients. It is therefore very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. For this purpose, the converter dynamic input impedance magnitude rEQ _ IN is provided in Figures 22, 23, 24. It is recommended to provide adequate design margin with respect to the stability conditions illustrated in 10.5.1 and 10.5.2. 8.5.1 Inductive source and local, external input decoupling capacitance with negligible ESR (i.e.: ceramic type) Figure 29 – light load burst mode of operation Note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. The variability depends on many factors including input voltage, output voltages, load impedance, and external error amplifier output impedance. In burst mode, the gain of the PR input to the plant which is modeled in the previous sections is time varying. Therefore the small signal analysis can not be directly applied to burst mode operation. 8.4 Input and Output filter design Figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the PRM at full load under various input and output voltages conditions. PRM® Regulator Rev 1.2 Page 20 of 23 7/2015 The voltage source impedance can be modeled as a series RlineLline circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified: Rline (C IN _ INT Rline rEQ _ IN Lline C IN _ EXT ) rEQ _ IN [6] [7] It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, [7]. However, Rline cannot be made arbitrarily low otherwise equation [6] is violated and the system will show instability, due to under-damped RLC input network. vicorpower.com 800 735.6200 PRM48DH480T250B03 8.5.2 Inductive source and local, external input decoupling capacitance with significant RCIN_EXT ESR (i.e.: electrolytic type) In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor Lline. Notice that, the high performance ceramic capacitors CIN_INT within the PRM should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be array. Imbalances in sharing are not only due to current sharing accuracy specifications, but also temperature differences among PRMs, Vin variations, and error terms in the buffering of the error amplifier output to the PR pins. Control loop compensation procedures above will hold for an array, in general, although many parameters must be scaled against the number of PRMs in the system. Please contact Vicor Applications for assistance. rEQ _ IN RC IN _ EXT [8] Lline rEQ _ IN C IN _ EXT RC IN _ EXT [9] 8.7 Equation [9] shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT) – the system will be under-damped and may even become destabilized. Again, an octave of design margin in satisfying [8] should be considered the minimum. 8.6 Arrays Up to ten PRMs of the same type may be placed in parallel to expand the power capacity of the system. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. –IN pins of all PRMs must be connected together. Both inductance and resistance from the common power source to each PRM should be minimized, and matched. Input voltage to all PRMs must be the same. Independent fuses for each PRM are recommended. PC pins must be connected together for synchronization and proper fault response. Reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules’ RE pins have reached their operational voltage levels. There must be one single external voltage control loop. The control loop must drive each PR pin relative to each module’s SG pin, and the local PR voltage must be the same across all modules. Each PRM must have its own local current shunt and current sense circuitry to drive its IF pin. The number of PRMs required to achieve a given array capacity must consider all sources of mismatch to avoid overstress of any PRM in the PRM® Regulator Rev 1.2 Page 21 of 23 7/2015 Input Fuse Recommendations A fuse should be incorporated at the input to each PRM, in series with the +IN pin. A 10 A or smaller input fuse (Littelfuse® NANO2® 451/453 Series, or equivalent) is required to safety agency conditions of acceptability. Always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. 8.8 Layout considerations Application Note AN:005 details board layout using V•I Chip components. Additional consideration must be given to the external control circuit components. The current sense shunt signal voltage is highly sensitive to noise. As such, current sensing circuitry should be located close to the shunt to minimize the length of the sense signals. A Kelvined connection at the shunt is recommended for best results. The control signal from a remote voltage sense circuit to the PRM should be shielded. Avoid routing this, or other control signals directly underneath the PRM, if possible. Components that tie directly to the PRM should be located close to their respective pins. It is also critical that all control components be referenced to SG, and that SG not be tied to any other ground in the system, including –IN or –OUT of the PRM. vicorpower.com 800 735.6200 PRM48DH480T250B03 Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. Specifications are subject to change without notice. Vicor’s Standard Terms and Conditions All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request. Product Warranty In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the “Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment and is not transferable. UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER. This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating safeguards. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Life Support Policy VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages. Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: [email protected] Technical Support: [email protected] PRM® Regulator Rev 1.2 Page 22 of 23 7/2015 vicorpower.com 800 735.6200