INTERSIL ISL85410

Wide VIN 1A Synchronous Buck Regulator
ISL85410
Features
The ISL85410 is a 1A Synchronous buck regulator with an
input range of 3V to 36V. It provides an easy to use, high
efficiency low BOM count solution for a variety of applications.
• Wide input voltage range 3V to 36V
• Synchronous Operation for high efficiency
• No compensation required
The ISL85410 integrates both high-side and low-side NMOS
FET's and features a PFM mode for improved efficiency at light
loads. This feature can be disabled if forced PWM mode is
desired. The part switches at a default frequency of 500kHz
but may also be programmed using an external resistor from
300kHz to 2MHz. The ISL85410 has the ability to utilize
internal or external compensation. By integrating both NMOS
devices and providing internal configuration options, minimal
external components are required, reducing BOM count and
complexity of design.
• Integrated High-side and Low-side NMOS devices
• Selectable PFM or forced PWM mode at light loads
• Internal fixed (500kHz) or adjustable Switching frequency
300kHz to 2MHz
• Continuous output current up to 1A
• Internal or external Soft-start
• Minimal external components required
• Power-good and enable functions available.
With the wide VIN range and reduced BOM the part provides an
easy to implement design solution for a variety of applications
while giving superior performance. It will provide a very robust
design for high voltage Industrial applications as well as an
efficient solution for battery powered applications.
Applications
• Industrial control
• Medical devices
• Portable instrumentation
The part is available in a small Pb free 4mmx3mm DFN plastic
package with an operation temperature range of -40°C to
+125°C
• Distributed Power supplies
• Cloud Infrastructure
Related Literature
• See AN1905, “ISL85410EVAL1Z, ISL85410AEVAL1Z,
ISL85418EVAL1Z Wide VIN 1A, 800mA Synchronous Buck
Regulator”
• See AN1908, “ISL85410DEMO1Z, ISL85418DEMO1Z Wide
VIN 1A, 800mA Synchronous Buck Regulator”
100
VIN = 5V
95
VIN = 12V
1
2
3
CBOOT
100nF
CVIN
10µF
5
VOUT
COUT
10µF
4
L1
22µH
6
SS
FS
COMP
SYNC
12
11
R2
10
BOOT
FB
GND
VIN
9
VCC
PHASE
PG
PGND
EN
R3
CVCC
1µF
CFB
EFFICIENCY (%)
90
85
VIN = 15V
80
75
70
VIN = 24V
65
VIN = 33V
60
55
INTERNAL DEFAULT PARAMETER SELECTION
FIGURE 1. TYPICAL APPLICATION
November 22, 2013
FN8375.2
1
50
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
1.0
FIGURE 2. EFFICIENCY vs LOAD, PFM, VOUT = 3.3V
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL85410
Table of Contents
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Efficiency Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
14
14
15
15
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
16
16
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
16
16
17
17
18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
FN8375.2
November 22, 2013
ISL85410
Pin Configuration
ISL85410
(12 LD 4X3 DFN)
TOP VIEW
12 FS
SS 1
SYNC 2
11 COMP
BOOT 3
10 FB
VIN 4
9
VCC
PHASE 5
8
PG
7
EN
PGND 6
GND
Pin Descriptions
PIN NUMBER
SYMBOL
PIN DESCRIPTION
1
SS
The SS pin controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground
determines the output ramp rate. See “Soft Start” on page 14 for soft-start details. If the SS pin is tied to
VCC, an internal soft-start of 2ms will be used.
2
SYNC
Synchronization and light load operational mode selection input. Connect to logic high or VCC for PWM
mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to automatically choose
PFM or PWM operation. Connect to an external clock source for synchronization with positive edge trigger.
Sync source must be higher than the programmed IC frequency. There is an internal 5MΩ pull-down resistor
to prevent an undefined logic state if SYNC is left floating.
3
BOOT
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor from this
pin to PHASE.
4
VIN
The input supply for the power stage of the regulator and the source for the internal linear bias regulator.
Place a minimum of 4.7µF ceramic capacitance from VIN to GND and close to the IC for decoupling.
5
PHASE
Switch node output. It connects the switching FET’s with the external output inductor.
6
PGND
Power ground connection. Connect directly to the system GND plane.
7
EN
Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the
voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not
connect EN pin to VCC since the LDO is controlled by EN voltage.
8
PG
Open drain power-good output that is pulled to ground when the output voltage is below regulation limits
or during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
9
VCC
Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin.
10
FB
Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In
addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage.
11
COMP
COMP is the output of the error amplifier. When it is tied to VCC, internal compensation is used. When only
an RC network is connected from COMP to GND, external compensation is used. See “Loop Compensation
Design” on page 17 for more details.
12
FS
EPAD
GND
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for
adjustable frequency from 300kHz to 2MHz.
Signal ground connections. Connect to application board GND plane with at least 5 vias. All voltage levels
are measured with respect to this pin. The EPAD MUST not float.
3
FN8375.2
November 22, 2013
ISL85410
Typical Application Schematics
1
2
3
CBOOT
100nF
4
CVIN
10µF
5
VOUT
L1
22µH
COUT
10µF
6
SS
FS
COMP
SYNC
12
11
R2
CFB
10
BOOT
FB
GND
9
VIN
R3
VCC
PHASE
CVCC
1µF
PG
PGND
EN
FIGURE 3. INTERNAL DEFAULT PARAMETER SELECTION
1
CSS
SS
FS
2
COMP
SYNC
3
CBOOT
100nF
4
CVIN
10µF
5
VOUT
COUT
10µF
L1
22µH
6
12
RFS
11
R2
CFB
10
BOOT
FB
GND
9
VIN
R3
VCC
PHASE
CVCC
1µF
PG
RCOMP
PGND
EN
CCOMP
FIGURE 4. USER PROGRAMMABLE PARAMETER SELECTION
TABLE 1. EXTERNAL COMPONENT SELECTION
VOUT
(V)
L1
(µH)
COUT
(µF)
R2
(kΩ)
R3
(kΩ)
CFB
(pF)
RFS
(kΩ)
RCOMP
(kΩ)
CCOMP
(pF)
12
22
2 x 22
90.9
4.75
22
115
150
470
5
22
47 + 22
90.9
12.4
27
DNP (Note 1)
100
470
3.3
22
47 + 22
90.9
20
27
DNP (Note 1)
100
470
2.5
22
47 + 22
90.9
28.7
27
DNP (Note 1)
100
470
1.8
12
47 + 22
90.9
45.5
27
DNP (Note 1)
70
470
NOTE:
1. Connect FS to Vcc
4
FN8375.2
November 22, 2013
ISL85410
VIN
PG
EN
SS
Functional Block Diagram
FB
POWER
GOOD
LOGIC
5M
VCC
BIAS
LDO
EN/SOFT
START
FB
FAULT
LOGIC
600mV VREF
FS
SYNC
600mV/Amp
Current Sense
OSCILLATOR
5M
PWM/PFM
SELECT LOGIC
PFM
CURRENT
SET
BOOT
FB
GATE
DRIVE
AND
PWM DEADTIME
PWM
s Q
R Q
Zero Current
Detection
PHASE
PGND
450mV/T Slope
Compensation
(PWM only)
gm
150k
Internal
54pF Compensation
GND
PACKAGE
PADDLE
COMP
Internal = 50µs
External = 230µs
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL85410FRZ
5410
ISL85410EVAL1Z
Evaluation Board
TEMP. RANGE
(°C)
-40 to +125
PACKAGE
(Pb-Free)
12 Ld DFN
PKG.
DWG. #
L12.4x3
NOTES:
1. Add “T” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85410. For more information on MSL please see techbrief TB363.
5
FN8375.2
November 22, 2013
ISL85410
Absolute Maximum Ratings
Thermal Information
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +42V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V (DC)
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 43V (20ns)
EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +42V
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
COMP, FS, PG, SYNC, SS, VCC to GND . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .1.5kV
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . 100mA
Thermal Resistance
θJA (°C/W) θJC (°C/W)
DFN Package (Notes 4, 5) . . . . . . . . . . . . . .
42
4.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Operating Junction Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 36V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications TA = -40°C to +125°C, VIN = 3V to 36V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply over the junction temperature range, -40°C to +125°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
36
V
SUPPLY VOLTAGE
VIN Voltage Range
VIN
3
VIN Quiescent Supply Current
IQ
VFB = 0.7V, SYNC = 0V, FS = VCC
80
VIN Shutdown Supply Current
ISD
EN = 0V, VIN=36V (Note 6)
2
4
µA
VCC Voltage
VCC
VIN = 6V, IOUT = 0 to 10mA
5.1
5.7
V
2.75
2.95
4.5
µA
POWER-ON RESET
VCC POR Threshold
Rising Edge
Falling Edge
2.35
2.6
FS = VCC
430
500
570
Resistor from FS to GND = 340kΩ
240
300
360
V
V
OSCILLATOR
Nominal Switching Frequency
FS
Resistor from FS to GND = 32.4kΩ
2000
kHz
kHz
kHz
Minimum Off-Time
tOFF
VIN = 3V
150
ns
Minimum On-Time
tON
(Note 9)
90
ns
VFS
FS = 100kΩ
FS Voltage
Synchronization Frequency
SYNC
0.39
0.4
300
SYNC Pulse Width
0.41
V
2000
kHz
100
ns
ERROR AMPLIFIER
Error Amplifier Transconductance Gain
gm
FB Leakage Current
Current Sense Amplifier Gain
External Compensation
6
230
295
µA/V
Internal Compensation
50
VFB = 0.6V
1
150
nA
0.46
0.5
0.54
V/A
TA = -40°C to +85°C
0.590
0.599
0.606
V
TA = -40°C to +125°C
0.590
0.599
0.607
V
RT
FB Voltage
165
µA/V
FN8375.2
November 22, 2013
ISL85410
Electrical Specifications TA = -40°C to +125°C, VIN = 3V to 36V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply over the junction temperature range, -40°C to +125°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
90
94
UNITS
POWER-GOOD
Lower PG Threshold - VFB Rising
Lower PG Threshold - VFB Falling
82.5
Upper PG Threshold - VFB Rising
86
116.5
Upper PG Threshold - VFB Falling
107
%
%
120
112
%
%
PG Propagation Delay
Percentage of the soft-start time
10
PG Low Voltage
ISINK = 3mA, EN = VCC, VFB = 0V
0.05
0.3
%
V
4.2
5.5
6.5
µA
1.5
2.4
3.4
ms
TRACKING AND SOFT-START
Soft-Start Charging Current
ISS
Internal Soft-Start Ramp Time
EN/SS = VCC
FAULT PROTECTION
Thermal Shutdown Temperature
Current Limit Blanking Time
TSD
Rising Threshold
150
°C
THYS
Hysteresis
20
°C
17
Clock
pulses
tOCON
Overcurrent and Auto Restart Period
tOCOFF
Positive Peak Current Limit
IPLIMIT
PFM Peak Current Limit
IPK_PFM
8
(Note 7)
SS cycle
1.3
1.5
1.7
0.34
0.4
0.5
Zero Cross Threshold
15
Negative Current Limit
INLIMIT
(Note 7)
-0.67
A
A
mA
-0.6
-0.53
A
POWER MOSFET
High-side
RHDS
IPHASE = 100mA, VCC = 5V
250
350
mΩ
Low-side
RLDS
IPHASE = 100mA, VCC = 5V
90
130
mΩ
300
nA
PHASE Leakage Current
EN = PHASE = 0V
PHASE Rise Time
tRISE
VIN = 36V
10
ns
EN/SYNC
Input Threshold
Falling Edge, Logic Low
0.4
Rising Edge, Logic High
1
V
1.2
1.4
V
EN Logic Input Leakage Current
EN = 0V/36V
0.5
µA
SYNC Logic Input Leakage Current
SYNC = 0V
-0.5
10
100
nA
SYNC = 5V
1.0
1.55
µA
NOTES:
6. Test Condition: VIN = 36V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included.
7. Established by both current sense amplifier gain test and current sense amplifier output test @ IL = 0A.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Minimum On-Time required to maintain loop stability.
7
FN8375.2
November 22, 2013
ISL85410
Efficiency Curves
FSW = 500kHz, TA = +25°C
100
100
95
95
90
VIN = 24V
85
VIN = 15V
EFFICIENCY (%)
EFFICIENCY (%)
90
80
VIN = 33V
75
70
65
75
70
55
55
0.1
0.2
0.3
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
50
1.0
VIN = 33V
65
60
0
0
FIGURE 5. EFFICIENCY vs LOAD, PFM, VOUT = 12V
100
90
85
85
VIN = 15V
VIN = 24V
75
70
65
0.3
0.4
0.5
0.6
0.7
0.8
0.9
50
1.0
VIN = 15V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT LOAD (A)
FIGURE 8. EFFICIENCY vs LOAD, PWM, VOUT = 5V, L1 = 30µH
FIGURE 7. EFFICIENCY vs LOAD, PFM, VOUT = 5V, L1 = 30µH
100
100
VIN = 5V
95
EFFICIENCY (%)
VIN = 15V
75
70
VIN = 24V
65
VIN = 33V
85
80
65
60
55
0.2
0.3
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
FIGURE 9. EFFICIENCY vs LOAD, PFM, VOUT = 3.3V
8
1.0
VIN = 33V
70
55
0.1
VIN = 15V
75
60
0
VIN = 5V
90
85
80
VIN = 12V
95
VIN = 12V
90
EFFICIENCY (%)
VIN = 6V
VIN = 24V
OUTPUT LOAD (A)
50
1.0
65
55
0.2
0.9
70
60
0.1
0.8
75
55
0
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
VIN = 12V
80
60
50
0.3
95
VIN = 6V
90
80
0.2
FIGURE 6. EFFICIENCY vs LOAD, PWM, VOUT = 12V
EFFICIENCY (%)
EFFICIENCY (%)
95
0.1
100
VIN = 12V
VIN = 15V
80
60
50
VIN = 24V
85
50
VIN = 24V
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
1.0
FIGURE 10. EFFICIENCY vs LOAD, PWM, VOUT = 3.3V
FN8375.2
November 22, 2013
ISL85410
Efficiency Curves
FSW = 500kHz, TA = +25°C (Continued)
100
100
95
VIN = 5V
90
85
EFFICIENCY (%)
EFFICIENCY (%)
90
80
VIN = 15V
75
70
VIN = 33V
65
VIN = 24V
60
VIN = 12V
95
VIN = 12V
VIN = 5V
85
80
75
70
VIN = 15V
65
60
VIN = 24V
55
55
50
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
50
1.0
0
0.1
0.2
0.3
5.004
0.6
0.7
0.8
0.9
1.0
5.030
5.003
5.025
VIN = 6V
VIN = 12V
5.001
OUTPUT VOLTAGE (V)
5.002
OUTPUT VOLTAGE (V)
0.5
FIGURE 12. EFFICIENCY vs LOAD, PWM, VOUT = 1.8V
FIGURE 11. EFFICIENCY vs LOAD, PFM, VOUT = 1.8V
5.000
4.999
4.998
4.997
VIN = 15V
4.996
VIN = 24V
4.995
4.993
0
0.1
0.2
0.3
VIN = 6V
5.020
VIN = 12V
5.015
5.010
5.005
VIN = 15V
5.000
4.995
4.994
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
4.990
1.0
VIN = 24V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT LOAD (A)
FIGURE 13. EFFICIENCY vs LOAD, PWM, VOUT = 5V, L1 = 30µH
FIGURE 14. VOUT REGULATION vs LOAD, PFM, VOUT = 5V, L1 = 30µH
3.345
3.326
VIN = 5V
VIN = 5V
3.325
3.340
3.324
OUTPUT VOLTAGE (V)
VIN = 12V
3.323
3.322
3.321
VIN = 15V
3.320
3.319
VIN = 24V
3.318
3.317
3.316
0.4
OUTPUT LOAD (A)
OUTPUT LOAD (A)
OUTPUT VOLTAGE (V)
VIN = 33V
VIN = 12V
3.335
3.330
VIN = 33V
3.320
VIN = 33V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
OUTPUT LOAD (A)
FIGURE 15. VOUT REGULATION vs LOAD, PWM, VOUT = 3.3V
9
VIN = 15V
3.325
1.0
3.315
VIN = 24V
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
1.0
FIGURE 16. VOUT REGULATION vs LOAD, PFM, VOUT = 3.3V
FN8375.2
November 22, 2013
ISL85410
Efficiency Curves
1.810
1.816
OUTPUT VOLTAGE (V)
VIN = 12V
1.808
OUTPUT VOLTAGE (V)
1.818
VIN = 5V
VIN = 15V
1.809
FSW = 500kHz, TA = +25°C (Continued)
1.807
1.806
1.805
1.804
VIN = 33V
1.803
VIN = 24V
1.802
1.812
VIN = 12V
1.810
VIN = 15V
1.808
1.806
1.804
VIN = 33V
1.802
1.801
1.800
VIN = 5V
1.814
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
FIGURE 17. VOUT REGULATION vs LOAD, PWM, VOUT = 1.8V
Measurements
1.0
1.800
0
0.1
0.2
0.3
VIN = 24V
0.4 0.5 0.6 0.7
OUTPUT LOAD (A)
0.8
0.9
1.0
FIGURE 18. VOUT REGULATION vs LOAD, PFM, VOUT = 1.8V
FSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
EN 20V/DIV
EN 20V/DIV
PG 2V/DIV
PG 2V/DIV
5ms/DIV
5ms/DIV
FIGURE 19. START-UP AT NO LOAD, PFM
FIGURE 20. START-UP AT NO LOAD, PWM
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
EN 20V/DIV
EN 20V/DIV
PG 2V/DIV
PG 2V/DIV
100ms/DIV
100ms/DIV
FIGURE 21. SHUTDOWN AT NO LOAD, PFM
FIGURE 22. SHUTDOWN AT NO LOAD, PWM
10
FN8375.2
November 22, 2013
ISL85410
Measurements
FSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 500mA/DIV
IL 500mA/DIV
PG 2V/DIV
PG 2V/DIV
5ms/DIV
200µs/DIV
FIGURE 23. START-UP AT 1A, PWM
FIGURE 24. SHUTDOWN AT 1A, PWM
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 500mA/DIV
IL 500mA/DIV
PG 2V/DIV
PG 2V/DIV
5ms/DIV
200µs/DIV
FIGURE 25. START-UP AT 1A, PFM
FIGURE 26. SHUTDOWN AT 1A, PFM
LX 5V/DIV
LX 5V/DIV
5ns/DIV
5ns/DIV
FIGURE 27. JITTER AT NO LOAD, PWM
FIGURE 28. JITTER AT 1A LOAD, PWM
11
FN8375.2
November 22, 2013
ISL85410
Measurements
FSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)
LX 20V/DIV
LX 20V/DIV
VOUT 20mV/DIV
VOUT 20mV/DIV
IL 20mA/DIV
IL 20mA/DIV
10ms/DIV
1µs/DIV
FIGURE 29. STEADY STATE AT NO LOAD, PFM
FIGURE 30. STEADY STATE AT NO LOAD, PWM
LX 20V/DIV
LX 20V/DIV
VOUT 20mV/DIV
VOUT 50mV/DIV
IL 1A/DIV
IL 200mA/DIV
1µs/DIV
10µs/DIV
FIGURE 31. STEADY STATE AT 1A, PWM
FIGURE 32. LIGHT LOAD OPERATION AT 20mA, PFM
LX 20V/DIV
VOUT 100mV/DIV
VOUT 10mV/DIV
IL 200mA/DIV
IL 1A/DIV
1µs/DIV
200µs/DIV
FIGURE 33. LIGHT LOAD OPERATION AT 20mA, PWM
FIGURE 34. LOAD TRANSIENT, PFM
12
FN8375.2
November 22, 2013
ISL85410
Measurements
FSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)
LX 20V/DIV
VOUT 100mV/DIV
VOUT 20mV/DIV
IL 1A/DIV
IL 1A/DIV
200µs/DIV
10µs/DIV
FIGURE 35. LOAD TRANSIENT, PWM
FIGURE 36. PFM TO PWM TRANSITION
LX 20V/DIV
LX 20V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IL 1A/DIV
IL 1A/DIV
PG 2V/DIV
PG 2V/DIV
10ms/DIV
50µs/DIV
FIGURE 37. OVERCURRENT PROTECTION, PWM
FIGURE 38. OVERCURRENT PROTECTION HICCUP, PWM
LX 20V/DIV
LX 20V/DIV
VOUT 5V/DIV
SYNC 2V/DIV
IL 1A/DIV
PG 2V/DIV
200ns/DIV
20µs/DIV
FIGURE 39. SYNC AT 1A LOAD, PWM
FIGURE 40. NEGATIVE CURRENT LIMIT, PWM
13
FN8375.2
November 22, 2013
ISL85410
Measurements
FSW = 500kHz, VIN = 24V, VOUT = 3.3V, TA = +25°C (Continued)
LX 20V/DIV
VOUT 5V/DIV
VOUT 2V/DIV
IL 500mA/DIV
PG 2V/DIV
PG 2V/DIV
200µs/DIV
500µs/DIV
FIGURE 42. OVER-TEMPERATURE PROTECTION, PWM
FIGURE 41. NEGATIVE CURRENT LIMIT RECOVERY, PWM
Detailed Description
Power-Good
The ISL85410 combines a synchronous buck PWM controller
with integrated power switches. The buck controller drives
internal high-side and low-side N-channel MOSFETs to deliver
load current up to 1A. The buck regulator can operate from an
unregulated DC source, such as a battery, with a voltage ranging
from +3V to +36V. An internal LDO provides bias to the low
voltage portions of the IC.
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage via the
FB pin. PG is actively held low when EN is low and during the
buck regulator soft-start period. After the soft-start period
completes, PG becomes high impedance provided the FB pin is
within the range specified in the “Electrical Specifications” on
page 3. Should FB exit the specified window, PG will be pulled
low until FB returns. Over-temperature faults also force PG low
until the fault condition is cleared by an attempt to soft-start.
There is an internal 5MΩ internal pull-up resistor.
Peak current mode control is utilized to simplify feedback loop
compensation and reject input voltage variation. User selectable
internal feedback loop compensation further simplifies design.
The ISL85410 switches at a default 500kHz.
The buck regulator is equipped with an internal current sensing
circuit and the peak current limit threshold is typically set at
0.9A.
Power-On Reset
The ISL85410 automatically initializes upon receipt of the input
power supply and continually monitors the EN pin state. If EN is
held below its logic rising threshold the IC is held in shutdown
and consumes typically 1µA from the VIN supply. If EN exceeds
its logic rising threshold, the regulator will enable the bias LDO
and begin to monitor the VCC pin voltage. When the VCC pin
voltage clears its rising POR threshold the controller will initialize
the switching regulator circuits. If VCC never clears the rising POR
threshold, the controller will not allow the switching regulator to
operate. If VCC falls below its falling POR threshold while the
switching regulator is operating, the switching regulator will be
shut down until VCC returns.
Soft Start
To avoid large in-rush current, VOUT is slowly increased at startup
to its final regulated value. Soft-start time is determined by the
SS pin connection. If SS is pulled to VCC, an internal 2ms timer is
selected for soft-start. For other soft-start times, simply connect
a capacitor from SS to GND. In this case, a 5.5µA current pulls up
the SS voltage and the FB pin will follow this ramp until it reaches
the 600mV reference level. Soft-start time for this case is
described by Equation 1:
Time ( ms ) = C ( nF )∗ 0.109
(EQ. 1)
14
PWM Control Scheme
The ISL85410 employs peak current-mode pulse-width
modulation (PWM) control for fast transient response and
pulse-by-pulse current limiting, as shown in the “Functional Block
Diagram” on page 5. The current loop consists of the current
sensing circuit, slope compensation ramp, PWM comparator,
oscillator and latch. Current sense trans-resistance is typically
600mV/A and slope compensation rate, Se, is typically 450mV/T
where T is the switching cycle period. The control reference for the
current loop comes from the error amplifier’s output (VCOMP).
A PWM cycle begins when a clock pulse sets the PWM latch and the
upper FET is turned on. Current begins to ramp up in the upper FET
and inductor. This current is sensed (VCSA), converted to a voltage
and summed with the slope compensation signal. This combined
signal is compared to VCOMP and when the signal is equal to VCOMP,
the latch is reset. Upon latch reset the upper FET is turned off and
the lower FET turned on allowing current to ramp down in the
inductor. The lower FET will remain on until the clock initiates
another PWM cycle. Figure 44 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate the
sum of the current sense and slope compensation signal.
Output voltage is regulated as the error amplifier varies VCOMP
and thus output inductor current. The error amplifier is a
trans-conductance type and its output (COMP) is terminated with
a series RC network to GND. This termination is internal
(150k/54pF) if the COMP pin is tied to VCC. Additionally, the
trans-conductance for COMP = VCC is 50µs vs 220µs for external
RC connection. Its non-inverting input is internally connected to a
600mV reference voltage and its inverting input is connected to
the output voltage via the FB pin and its associated divider
network.
FN8375.2
November 22, 2013
ISL85410
PWM
DCM
PULSE SKIP
PWM
DCM
CLOCK
8 CYCLES
IL
LOAD CURRENT
0
VOUT
FIGURE 43. DCM MODE OPERATION WAVEFORMS
comparator signals an FB voltage 1% lower than the 600mV
reference and forces the converter to return to PWM operation.
VCOMP
Output Voltage Selection
VCSA
The regulator output voltage is easily programmed using an
external resistor divider to scale VOUT relative to the internal
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier; refer to Figure 43.
DUTY
CYCLE
The output voltage programming resistor, R3, depends on the
value chosen for the feedback resistor, R2, and the desired
output voltage, VOUT, of the regulator. Equation 3 describes the
relationship between VOUT and resistor values.
IL
VOUT
R 2 x0.6V
R 3 = ---------------------------------V OUT – 0.6V
FIGURE 44. PWM OPERATION WAVEFORMS
If the desired output voltage is 0.6V, then R3 is left unpopulated
and R2 is 0Ω.
At light loads, converter efficiency may be improved by enabling
variable frequency operation (PFM). Connecting the SYNC pin to
GND will allow the controller to choose such operation
automatically when the load current is low. Figure 43 shows the
DCM operation. The IC enters the DCM mode of operation when 8
consecutive cycles of inductor current crossing zero are detected.
This corresponds to a load current equal to 1/2 the peak-to-peak
inductor ripple current and set by the following Equation 2:
(EQ. 2)
where D = duty cycle, FS = switching frequency, L = inductor
value, IOUT = output loading current, VOUT = output voltage.
While operating in PFM mode, the regulator controls the output
voltage with a simple comparator and pulsed FET current. A
comparator signals the point at which FB is equal to the 600mV
reference at which time the regulator begins providing pulses of
current until FB is moved above the 600mV reference by 1%. The
current pulses are approximately 300mA and are issued at a
frequency equal to the converters programmed PWM operating
frequency.
Due to the pulsed current nature of PFM mode, the converter can
supply limited current to the load. Should load current rise
beyond the limit, VOUT will begin to decline. A second
15
VOUT
FB
EA
R2
+
-
Light Load Operation
V OUT ( 1 – D )
I OUT = ----------------------------------2LF s
(EQ. 3)
R3
0.6V
REFERENCE
FIGURE 45. EXTERNAL RESISTOR DIVIDER
Protection Features
The ISL85410 is protected from overcurrent, negative
overcurrent and over-temperature. The protection circuits
operate automatically.
Overcurrent Protection
During PWM on-time, current through the upper FET is monitored
and compared to a nominal 0.9A peak overcurrent limit. In the
event that current reaches the limit, the upper FET will be turned
off until the next switching cycle. In this way, FET peak current is
always well limited.
FN8375.2
November 22, 2013
ISL85410
Should the output fault persist, the regulator will repeat the
hiccup sequence indefinitely. There is no danger even if the
output is shorted during soft-start.
If VOUT is shorted very quickly, FB may collapse below 5/8ths of
its target value before 17 cycles of overcurrent are detected. The
ISL85410 recognizes this condition and will begin to lower its
switching frequency proportional to the FB pin voltage. This
insures that under no circumstance (even with VOUT near 0V) will
the inductor current run away.
Negative Current Limit
Should an external source somehow drive current into VOUT, the
controller will attempt to regulate VOUT by reversing its inductor
current to absorb the externally sourced current. In the event that
the external source is low impedance, current may be reversed to
unacceptable levels and the controller will initiate its negative
current limit protection. Similar to normal overcurrent, the
negative current protection is realized by monitoring the current
through the lower FET. When the valley point of the inductor
current reaches negative current limit, the lower FET is turned off
and the upper FET is forced on until current reaches the POSITIVE
current limit or an internal clock signal is issued. At this point, the
lower FET is allowed to operate. Should the current again be pulled
to the negative limit on the next cycle, the upper FET will again be
forced on and current will be forced to 1/6th of the positive current
limit. At this point the controller will turn off both FET’s and wait for
COMP to indicate return to normal operation. During this time, the
controller will apply a 100Ω load from PHASE to PGND and
attempt to discharge the output. Negative current limit is a
pulse-by-pulse style operation and recovery is automatic.
Application Guidelines
Simplifying the Design
While the ISL85410 offers user programmed options for most
parameters, the easiest implementation with fewest
components involves selecting internal settings for SS, COMP
and FS. Table 1 on page 4 provides component value selections
for a variety of output voltages and will allow the designer to
implement solutions with a minimum of effort.
Operating Frequency
The ISL85410 operates at a default switching frequency of
500kHz if FS is tied to VCC. Tie a resistor from FS to GND to
program the switching frequency from 300kHz to 2MHz, as
shown in Equation 4.
R FS [ kΩ ] = 108.75kΩ∗ ( t – 0.2μs ) ⁄ 1μs
t is the switching period in µs.
300
200
100
0
500
Over-Temperature Protection
Over-temperature protection limits maximum junction
temperature in the ISL85410. When junction temperature (TJ)
exceeds +150°C, both FET’s are turned off and the controller
waits for temperature to decrease by approximately 20°C.
During this time PG is pulled low. When temperature is within an
acceptable range, the controller will initiate a normal soft-start
sequence. For continuous operation, the +125°C junction
temperature rating should not be exceeded.
(EQ. 4)
Where:
RFS (kΩ)
If the overcurrent condition persists for 17 sequential clock
cycles, the regulator will begin its hiccup sequence. In this case,
both FETS will be turned off and PG will be pulled low. This
condition will be maintained for 8 soft-start periods after which,
the regulator will attempt a normal soft-start.
750
1000
1250
1500
1750
2000
FS (kHz)
FIGURE 46. RFS SELECTION vs FS
Synchronization Control
The frequency of operation can be synchronized up to 2MHz by
an external signal applied to the SYNC pin. The rising edge on the
SYNC triggers the rising edge of PHASE. To properly sync, the
external source must be at least 10% greater than the
programmed free running IC frequency.
Boot Undervoltage Protection
Output Inductor Selection
If the Boot capacitor voltage falls below 1.8V, the Boot
undervoltage protection circuit will turn on the lower FET for
400ns to recharge the capacitor. This operation may arise during
long periods of no switching such as PFM no load situations. In
PWM operation near dropout (VIN near VOUT), the regulator may
hold the upper FET on for multiple clock cycles. To prevent the
boot capacitor from discharging, the lower FET is forced on for
approximately 200ns every 10 clock cycles.
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, ΔI. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 5:
L=
VIN - VOUT
FS x DI
x
VOUT
(EQ. 5)
VIN
Increasing the value of inductance reduces the ripple current and
thus, the ripple voltage. However, the larger inductance value
may reduce the converter’s response time to a load transient.
The inductor current rating should be such that it will not saturate
16
FN8375.2
November 22, 2013
ISL85410
in overcurrent conditions. For typical ISL85410 applications,
inductor values generally lies in the 10µH to 47µH range. In
general, higher VOUT will mean higher inductance.
^
Vin
Buck Regulator Output Capacitor Selection
While ceramic capacitors offer excellent overall performance
and reliability, the actual in-circuit capacitance must be
considered. Ceramic capacitors are rated using large
peak-to-peak voltage swings and with no DC bias. In the DC/DC
converter application, these conditions do not reflect reality. As a
result, the actual capacitance may be considerably lower than
the advertised value. Consult the manufacturers data sheet to
determine the actual in-application capacitance. Most
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, but an assumption of ~20% further
reduction will generally suffice. The result of these
considerations may mean an effective capacitance 50% lower
than nominal and this value should be used in all design
calculations. Nonetheless, ceramic capacitors are a very good
choice in many applications due to their reliability and extremely
low ESR.
ILd^ 1:D
^
iL
LP
vo^
RLP
Vind^
+
Rc
RT
GAIN (VLOOP (S(fi))
An output capacitor is required to filter the inductor current. The
current mode control loop allows the use of low ESR ceramic
capacitors and thus supports very small circuit implementations
on the PC board. Electrolytic and polymer capacitors may also be
used.
+
^
iin
Co
Ro
Ti(S)
d^
K
Fm
+
Tv(S)
He(S)
v^comp
-Av(S)
FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Vo
R2
C3
VFB
R3
VREF
-
VCOMP
GM
+
R6
C7
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
C6
For the ceramic capacitors (low ESR):
ΔI
V OUTripple = --------------------------------------8∗ F SW∗ C OUT
(EQ. 6)
where ΔI is the inductor’s peak-to-peak ripple current, FSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = ΔI*ESR
(EQ. 7)
FIGURE 48. TYPE II COMPENSATOR
Figure 48 shows the type II compensator and its transfer function
is expressed, as shown in Equation 8:
S
S ⎞⎛
⎛ 1 + ------------ 1 + -------------⎞
⎝
GM ⋅ R 3
ω cz2⎠
ω cz1⎠ ⎝
vˆ COMP
- = -------------------------------------------------------- --------------------------------------------------------------A v ( S ) = ------------------S
( C6 + C7 ) ⋅ ( R2 + R3 ) ⎛
S
vˆ FB
S 1 + -------------⎞ ⎛ 1 + -------------⎞
⎝
⎠⎝
⎠
ω
ω
cp1
(EQ. 8)
Loop Compensation Design
When COMP is not connected to VCC, the COMP pin is active for
external loop compensation. The ISL85410 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current sensing pilot
device in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant,
and the system becomes a single order system. It is much easier
to design a type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
line regulation. Figure 47 shows the small signal model of the
synchronous buck regulator.
cp2
where,
C6 + C7
R2 + R3
1
1
ω cz1 = --------------- , ω cz2 = ---------------, ω cp1 = -----------------------, ω cp2 = ----------------------R6 C6 C7
C3 R2 R3
R6 C6
R2 C3
Compensator design goal:
High DC gain
Choose Loop bandwidth fc less than 100kHz
Gain margin: >10dB
Phase margin: >40°
The compensator design procedure is as follows:
The loop gain at crossover frequency of fc has a unity gain.
Therefore, the compensator resistance R6 is determined by
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FN8375.2
November 22, 2013
ISL85410
Equation 9.
60
(EQ. 9)
Where GM is the trans-conductance, gm, of the voltage error
amplifier in each phase. Compensator capacitor C6 is then given
by Equation 10.
Ro Co Vo Co
Rc Co 1
C 6 = --------------- = --------------- ,C 7 = max (--------------,----------------)
R6
Io R6
R 6 πf s R 6
(EQ. 10)
45
30
GAIN (dB)
2πf c V o C o R t
3
R 6 = ---------------------------------- = 22.75 ×10 ⋅ f c V o C o
GM ⋅ V FB
15
0
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 10. An optional zero can boost the phase margin. ωCZ2
is a zero due to R2 and C3.
-15
Put compensator zero 2 to 5 times fc
180
1
C 3 = ---------------πf c R 2
-30
100
(EQ. 12)
It is acceptable to use 124kΩ as the closest standard value for
R6.
5V ⋅ 22 μF
C 6 = ------------------------------ = 0.88nF
1A ⋅ 124kΩ
(EQ. 13)
100k
1M
150
120
PHASE (°)
3
R 6 = 22.75 ×10 ⋅ 50kHz ⋅ 5V ⋅ 22μF = 125.12kΩ
10k
FREQUENCY (Hz)
(EQ. 11)
Example: VIN = 12V, VO = 5V, IO = 1A, fs = 500kHz, R2 = 90.9kΩ,
Co = 22µF/5mΩ, L = 39µH, fc = 50kHz, then compensator
resistance R6:
1k
90
60
30
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 49. SIMULATED LOOP GAIN
5mΩ ⋅ 22μF
1
C 7 = max (---------------------------------,----------------------------------------------------) = (0.88pF,5.1pF)
124kΩ
π ⋅ 500kHz ⋅ 124kΩ
(EQ. 14)
It is also acceptable to use the closest standard values for C6 and
C7. There is approximately 3pF parasitic capacitance from VCOMP to
GND; Therefore, C7 is optional. Use C6 = 1500pF and C7 = OPEN.
1
C 3 = -------------------------------------------------- = 70pF
π ⋅ 50kHz ⋅ 90.9kΩ
(EQ. 15)
Use C3 = 68pF. Note that C3 may increase the loop bandwidth
from previous estimated value. Figure 49 shows the simulated
voltage loop gain. It is shown that it has a 75kHz loop bandwidth
with a 61° phase margin and 6dB gain margin. It may be more
desirable to achieve an increased gain margin. This can be
accomplished by lowering R6 by 20% to 30%. In practice,
ceramic capacitors have significant derating on voltage and
temperature, depending on the type. Please refer to the ceramic
capacitor datasheet for more details.
Layout Considerations
Proper layout of the power converter will minimize EMI and noise
and insure first pass success of the design. PCB layouts are
provided in multiple formats on the Intersil web site. In addition,
Figure 50 will make clear the important points in PCB layout. In
reality, PCB layout of the ISL85410 is quite simple.
A multi-layer printed circuit board with GND plane is
recommended. Figure 50 shows the connections of the critical
components in the converter. Note that capacitors CIN and COUT
could each represent multiple physical capacitors. The most
critical connections are to tie the PGND pin to the package GND
pad and then use vias to directly connect the GND pad to the
system GND plane. This connection of the GND pad to system
plane insures a low impedance path for all return current, as well
as an excellent thermal path to dissipate heat. With this
connection made, place the high frequency MLCC input capacitor
near the VIN pin and use vias directly at the capacitor pad to tie
the capacitor to the system GND plane.
The boot capacitor is easily placed on the PCB side opposite the
controller IC and 2 vias directly connect the capacitor to BOOT
and PHASE.
Place a 1µF MLCC near the VCC pin and directly connect its
return with a via to the system GND plane.
Place the feedback divider close to the FB pin and do not route
any feedback components near PHASE or BOOT. If external
components are used for SS, COMP or FS the same advice
applies.
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FN8375.2
November 22, 2013
ISL85410
CSS
RFS
CVCC
CVIN
L1
COUT
FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
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FN8375.2
November 22, 2013
ISL85410
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
November 22, 2013
FN8375.2
CHANGE
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
20
FN8375.2
November 22, 2013
ISL85410
Package Outline Drawing
L12.4x3
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 7/10
3.30 +0.10/-0.15
4.00
6
PIN 1
INDEX AREA
2X 2.50
A
B
PIN #1 INDEX AREA
6
10X 0.50
1
12 X 0.40 ±0.10
6
1.70 +0.10/-0.15
3.00
(4X)
0.15
7
12
TOP VIEW
0.10M C A B
4 12 x 0.23 +0.07/-0.05
BOTTOM VIEW
SEE DETAIL "X"
( 3.30)
6
0.10 C
1
C
1.00 MAX
SEATING PLANE
0.08 C
SIDE VIEW
2.80
( 1.70 )
C
0.2 REF
5
12 X 0.60
7
12
0 . 00 MIN.
0 . 05 MAX.
( 12X 0.23 )
( 10X 0 . 5 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
21
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
Compliant to JEDEC MO-229 V4030D-4 issue E.
FN8375.2
November 22, 2013