512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Features DDR SDRAM SODIMM MT16VDDF6464H – 512MB MT16VDDF12864H – 1GB For component data sheets, refer to Micron’s Web site: www.micron.com Features Figure 2: • 200-pin, small-outline dual in-line memory module (SODIMM) • Fast data transfer rates: PC2100, PC2700, and PC3200 • 512MB (64 Meg x 64) and 1GB (128 Meg x 64) • VDD = VDDQ = +2.5V (-40B: VDD = VDDQ = +2.6V) • VDDSPD = +2.3V to +3.6V • 2.5V I/O (SSTL_2-compatible) • Internal, pipelined double data rate (DDR) 2n-prefetch architecture; two data accesses per clock cycle • Bidirectional data strobe (DQS) transmitted/received with data—that is, source-synchronous data capture • Differential clock inputs CK and CK# • Multiple internal device banks for concurrent operation • Dual rank • Programmable burst lengths (BL): 2, 4, or 8 • Auto precharge option • Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval • Serial presence-detect (SPD) with EEPROM • Selectable CAS latency (CL) for maximum compatibility • Gold edge contacts 512MB 200-Pin SODIMM Options Marking • Self refresh current – Standard None – Low power1 L • Operating temperature – Commercial (0°C ≤ TA ≤ +70°C) None – Industrial (–40°C ≤ TA ≤ +85°C) I • Package – 200-pin DIMM (standard) G – 200-pin DIMM (Pb-free)2 Y • Memory clock, speed, CAS latency – 5.0ns (200 MHz), 400 MT/s, CL = 3 -40B – 6.0ns (167 MHz), 333 MT/s, CL = 2.5 -335 – 7.5ns (133 MHz), 266 MT/s, CL = 2.52 -265 Notes: 1. See Table 9 on page 10 , Table 10 on page 11, or Table 11 on page 12 for low power values. 2. Contact Micron for product availability. (MO-244) PCB height: 31.75mm (1.25in) PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN (MO-244) PCB height: 31.75mm (1.25in) 200-Pin SODIMM Figures Figure 1: 1GB 200-Pin SODIMM 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Features Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 3 CL = 2.5 CL = 2 RCD (ns) t RP (ns) t RC (ns) -40B PC3200 400 333 266 15 15 55 -335 PC2700 – 333 266 18 18 60 -265 PC2100 – 266 200 20 20 65 Notes: Table 2: t Notes 1 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns. Addressing Parameter 512MB Refresh count 1GB 8K 8K Row address 8K (A0–A12) 8K (A0–A12) Device bank address 4 (BA0, BA1) 4 (BA0, BA1) Device configuration 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) Column address 1K (A0–A9) 2K (A0–A9, A11) Module rank address 2 (S0#, S1#) 2 (S0#, S1#) Table 3: Part Numbers and Timing Parameters – 512MB Base device: MT46V32M8,1 256Mb DDR SDRAM Module Density Part Number2 Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT16VDDF6464HG-40B__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16VDDF6464HY-40B__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16VDDF6464(L)HG-335__ 512MB 64 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDF6464HI-335 512MB 64 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDF6464HY-335__ 512MB 64 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDF6464(L)HG-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDF6464HY-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Notes: PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT16VDDF12864HY-335F2. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Features Table 4: Part Numbers and Timing Parameters – 1GB Base device: MT46V64M8,1 512Mb DDR SDRAM Part Number2 MT16VDDF12864HG-40B__ Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16VDDF12864HY-40B__ 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16VDDF12864(L)HG-335__ 1GB 128 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDF12864HI-335__ 1GB 128 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDF12864H(I)Y-335__ 1GB 128 Meg x 64 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT16VDDF12864HG-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDF12864HY-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Notes: PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT16VDDF12864HY-335F2. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 200-Pin SODIMM Front 200-Pin SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 Pin Symbol Pin Symbol Pin Symbol Pin Symbol VREF 51 VSS 101 A9 151 DQ42 2 VREF 52 VSS 102 A8 152 DQ46 54 DQ23 104 VSS 154 DQ47 3 VSS 53 DQ19 103 VSS 153 DQ43 4 VSS 5 DQ0 55 DQ24 105 A7 155 VDD 6 DQ4 56 DQ28 106 A6 156 VDD 7 DQ1 57 VDD 107 A5 157 VDD 8 DQ5 58 VDD 108 A4 158 CK1# CK1 9 VDD 59 DQ25 109 A3 159 VSS 10 VDD 60 DQ29 110 A2 160 11 DQS0 61 DQS3 111 A1 161 VSS 12 DM0 62 DM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VDD 163 DQ48 14 DQ6 64 VSS 114 VDD 164 DQ52 16 VSS 66 DQ30 116 BA1 166 DQ53 15 VSS 65 DQ26 115 A10 165 DQ49 17 DQ3 67 DQ27 117 BA0 167 VDD 18 DQ7 68 DQ31 118 RAS# 168 VDD 19 DQ8 69 VDD 119 WE# 169 DQS6 20 DQ12 70 VDD 120 CAS# 170 DM6 21 VDD 71 NC 121 S0# 171 DQ50 22 VDD 72 NC 122 S1# 172 DQ54 23 DQ9 73 NC 123 NC 173 VSS 24 DQ13 74 NC 124 NC 174 VSS 25 DQS1 75 VSS 125 VSS 175 DQ51 26 DM1 76 VSS 126 VSS 176 DQ55 28 VSS 78 NC 128 DQ36 178 DQ60 27 VSS 77 NC 127 DQ32 177 DQ56 29 DQ10 79 NC 129 DQ33 179 VDD 30 DQ14 80 NC 130 DQ37 180 VDD 31 DQ11 81 VDD 131 VDD 181 DQ57 32 DQ15 82 VDD 132 VDD 182 DQ61 DM7 33 VDD 83 NC 133 DQS4 183 DQS7 34 VDD 84 NC 134 DM4 184 35 CK0 85 NC 135 DQ34 185 VSS 36 VDD 86 NC 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 40 VSS 90 VSS 140 DQ39 190 DQ63 39 VSS 89 NF 139 DQ35 189 DQ59 41 DQ16 91 NF 141 DQ40 191 VDD 42 DQ20 92 VDD 142 DQ44 192 VDD 43 DQ17 93 VDD 143 VDD 193 SDA 44 DQ21 94 VDD 144 VDD 194 SA0 45 VDD 95 CKE1 145 DQ41 195 SCL 46 VDD 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VDDSPD 48 DM2 98 NC 148 DM5 198 SA2 49 DQ18 99 A12 149 VSS 199 NC 50 DQ22 100 A11 150 VSS 200 VSS PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Symbol Type Description A0–A12 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the opcode during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. BA0, BA1 Input Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. CK0, CK0#, CK1, CK1# Input Clock: CK, CK# are differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. CKE0, CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates the internal clock, input buffers, and output drivers. S0#, S1# Input Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. SDA Input/ Output WE#, CAS#, RAS# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. DM0–DM7 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although the DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. DQ0–DQ63 Input/ Output Data input/output: Data bus. DQS0–DQS7 Input/ Output Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Used to capture data. VDD Supply Power supply: +2.5V ±0.2V. VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V. VREF Supply SSTL_2 reference voltage (VDD/2). VSS Supply Ground. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Functional Block Diagrams Functional Block Diagrams Figure 3: Functional Block Diagram – 512MB S1# S0# DQS0 DQS1 DM0 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ U1 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ U5 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U10 DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ U6 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ U9 DQ DQ DQ DQ DQ DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ U2 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ DQS5 DQS4 DM5 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DQS7 DM7 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 A0–A12 DM CS# DQS DQ DQ DQ DQ U7 DQ DQ DQ DQ DQS3 DQS2 DM2 BA0, BA1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ U8 DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ BA0, BA1: DDR SDRAM A0–A12: DDR SDRAM RAS# CAS# RAS#: DDR SDRAM CKE0 CKE0: DDR SDRAM U1–U8 CKE1 CKE1: DDR SDRAM U9–U16 WE# WE#: DDR SDRAM CAS#: DDR SDRAM VDDSPD SPD EEPROM VDD DDR SDRAM VREF DDR SDRAM VSS DDR SDRAM SCL U17 SPD EEPROM WP A0 A1 A2 6 U1, U2, U3, U7 U12, U13, U14, U16 CK1 CK1# U4, U5, U6, U8 U9, U10, U11, U15 SDA VSS SA0 SA1 SA2 PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN CK0 CK0# CK2 CK2# Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Functional Block Diagrams Figure 4: Functional Block Diagram – 1GB S1# S0# DQS0 DQS1 DM0 DM1 DM CS# DQS DQ DQ DQ DQ U1 DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ DQ U12 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U16 DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U6 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U15 DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ U7 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U14 DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ U8 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U13 DQ DQ DQ DQ DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ DQ U2 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U11 DQ DQ DQ DQ DQS5 DQS4 DM5 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U10 DQ DQ DQ DQ DQS7 DM7 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 A0–A12 DM CS# DQS DQ DQ DQ DQ U5 DQ DQ DQ DQ DQS3 DQS2 DM2 BA0, BA1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ U9 DQ DQ DQ DQ BA0, BA1: DDR SDRAM A0–A12: DDR SDRAM RAS# CAS# RAS#: DDR SDRAM CKE0 CKE0: DDR SDRAM U1–U8 CKE1 CKE1: DDR SDRAM U9–U16 WE# WE#: DDR SDRAM CAS#: DDR SDRAM PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN CK0 CK0# DDR SDRAM U1, U2, U3, U7 U12, U13, U14, U16 CK1 CK1# DDR SDRAM SCL U4, U5, U6, U8 U9, U10, U11, U15 CK2 CK2# U17 SPD EEPROM WP A0 A1 A2 SDA VSS SA0 SA1 SA2 VDDSPD SPD EEPROM VDD DDR SDRAM VREF DDR SDRAM VSS DDR SDRAM 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM General Description General Description The MT16VDDF6464H and MT16VDDF12864H are high-speed, CMOS, dynamic random access 512MB and 1GB memory modules organized in a x64 configuration. These modules use DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bitwide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various DDR SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is connected to VSS, permanently disabling hardware write protect. PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VDD supply voltage relative to VSS –1.0 +3.6 V VIN, VOUT Voltage on any pin relative to VSS –0.5 +3.2 V Input leakage current; Any input 0V ≤ VIN ≤ VDD; Address inputs, VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under RAS#, CAS#, WE#, BA test = 0V) S#, CKE, CK, CK# –32 +32 µA II –16 +16 DM –4 +4 –10 +10 IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are disabled DQ, DQS TA DRAM ambient operating temperature1 Commercial Industrial Notes: µA 0 +70 °C –40 +85 °C 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. DRAM Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades DDR components may exceed the listed module speed grades Module Speed Grade Component Speed Grade -40B -5B -335 -6 -265 -75 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Electrical Specifications IDD Specifications Table 9: IDD Specifications and Conditions – 512MB (Die Revison K) Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Symbol -40B -335 Units Operating one bank active-precharge current: One device bank; Active-precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles 1 IDD0 832 752 mA Operating one bank active-read-precharge current: One device bank; Active-read-precharge; BL = 4; tRC = tRC (MIN); t CK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 992 952 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2P2 64 64 mA Idle standby current: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F2 800 800 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 560 480 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 960 880 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 1,472 1,132 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W1 1,472 1,312 mA IDD52 2,560 2,560 mA IDD5A2 96 96 mA IDD62, 3 64 64 mA IDD6A2, 3 IDD71 32 32 mA 2,352 2,192 mA Auto refresh burst current Self refresh current: CKE ≤ 0.2V tREFC = tRFC (MIN) tREFC = 7.8125µs Standard Low power Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; tRC = (MIN) tRC allowed; tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks are in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 3. The standard module guarantees IDD6 and the low-power module guarantees IDD6A. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Electrical Specifications Table 10: IDD Specifications and Conditions – 512MB (All Other Die Revisions) Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Symbol -40B -335 -265 Units Operating one bank active-precharge current: One device bank; Active-precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1 1,112 1,032 992 mA Operating one bank active-read-precharge current: One device bank; Active-read-precharge; BL = 4; tRC = tRC (MIN); t CK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 1,392 1,392 1,192 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2P2 64 64 64 mA Idle standby current: CS# = HIGH; All device banks are idle; = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F2 960 800 720 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 640 480 480 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 1,120 960 800 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 1,632 1,432 1,232 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W1 1,592 1,432 1,232 mA IDD52 4,160 4,080 3,920 mA IDD5A2 IDD62, 3 96 96 96 mA 64 64 64 mA IDD6A2, 3 32 32 32 mA IDD71 3,792 3,312 2,952 mA tCK Auto refresh burst current tREFC tREFC Self refresh current: CKE ≤ 0.2V = tRFC (MIN) = 7.8125µs Standard Low power Operating bank interleave read current: Four device bank interleaving READs (BL = 4) with auto precharge; t RC = (MIN) tRC allowed; tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks are in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 3. The standard module guarantees IDD6 and the low power module guarantees IDD6A. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Electrical Specifications Table 11: IDD Specifications and Conditions – 1GB Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter/Condition Symbol -40B -335 -265 Units Operating one bank active-precharge current: One device bank; Active-precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1 1,280 1,080 960 mA Operating one bank active-read-precharge current: One device bank; Active-read-precharge; BL = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD11 1,520 1,320 1,200 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2P2 80 80 90 mA Idle standby current: CS# = HIGH; All device banks are idle; = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F2 880 720 640 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P2 720 560 480 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N2 960 800 720 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R1 1,560 1,360 1,200 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W1 1,600 1,440 1,120 mA IDD52 5,520 4,640 4,480 mA IDD5A2 IDD62, 3 176 160 160 mA 80 80 80 mA IDD6A2, 3 48 48 48 mA IDD71 3,640 3,280 2,840 mA tCK Auto refresh burst current tREFC tREFC Self refresh current: CKE ≤ 0.2V = tRFC (MIN) = 7.8125µs Standard Low power Operating bank interleave read current: Four device bank interleaving READs (BL = 4) with auto precharge; tRC = (MIN) tRC allowed; tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands Notes: PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 1. Value calculated as one module rank in this operating condition; all other module ranks are in IDD2P (CKE LOW) mode. 2. Value calculated reflects all module ranks in this operating condition. 3. The standard module guarantees IDD6 and the low power module guarantees IDD6A. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Serial Presence-Detect Serial Presence-Detect Table 12: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Symbol Min Max Units VDDSPD 2.3 3.6 V Input high voltage: Logic 1; All inputs VIH Input low voltage: Logic 0; All inputs VIL VDDSPD × 0.7 VDDSPD + 0.5 –1.0 VDDSPD × 0.3 Output low voltage: IOUT = 3mA V V VOL – 0.4 V Input leakage current: VIN = GND to VDD ILI – 10 µA Output leakage current: VOUT = GND to VDD ILO – 10 µA Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS ISB – 30 µA Power supply current: SCL clock frequency = 100 kHz ICC – 2.0 mA Table 13: Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH 200 – ns Clock/data fall time tF – 300 ns 2 Clock/data rise time tR – 300 ns 2 Data-in hold time tHD:DAT 0 – µs Start condition hold time tHD:STA 0.6 – µs tHIGH 0.6 – µs tI – 50 ns tLOW 1.3 – µs fSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs Stop condition setup time tSU:STO 0.6 – µs tWRC – 10 ms Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SCL clock frequency WRITE cycle time Notes: 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron’s SPD page: www.micron.com/SPD. PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Module Dimensions Module Dimensions Figure 5: 200-Pin SODIMM – 512MB Front view 3.8 (0.15) MAX 67.75 (2.667) 67.45 (2.656) 2.0 (0.079) R (2X) U2 U1 U3 U4 U5 U6 31.9 (1.256) 31.6 (1.244) 1.8 (0.071) (2X) U8 U7 20.0 (0.787) TYP U17 6.0 (0.236) TYP 2.44 (0.096) TYP 1.1 (0.043) 0.9 (0.035) 2.0 (0.079) TYP 0.99 (0.039) TYP Pin 1 0.46 (0.018) TYP 0.61 (0.024) TYP Pin 199 63.6 (2.504) TYP Back view U10 U9 U11 U12 U13 U15 U16 Pin 200 Notes: PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN U14 Pin 2 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved 512MB, 1GB (x64, DR) 200-Pin DDR SODIMM Module Dimensions Figure 6: 200-Pin SODIMM – 1GB Front view 3.8 (0.15) MAX 67.75 (2.667) 67.45 (2.656) 2.0 (0.079) R (2X) U17 U1 U2 U3 U4 31.9 (1.256) 31.6 (1.244) 1.8 (0.071) (2X) U6 U5 U7 U8 20.0 (0.787) TYP 6.0 (0.236) TYP 2.44 (0.096) TYP 2.0 (0.079) TYP 1.1 (0.043) 0.9 (0.035) 0.99 (0.039) TYP Pin 1 0.46 (0.018) TYP 0.61 (0.024) TYP Pin 199 63.6 (2.504) TYP Back view U9 U10 U11 U12 U13 U14 U15 U16 Pin 200 Notes: Pin 2 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 [email protected] www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80a77a90/Source: 09005aef80a646bc DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.