TN-29-14: Increasing NAND Flash Performance Overview Technical Note NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE Command Overview NAND Flash devices are designed for applications requiring nonvolatile, high-density, solid state storage memory. Although NAND Flash may meet the speed requirements of traditional applications, many newer applications require faster data processing capabilities. For these applications, Micron® NAND Flash can deliver higher data throughput using the PROGRAM PAGE CACHE MODE operation. Cache programming works by pipelining data to the NAND Flash device. Pipelining involves sending a page (2KB) of data to the cache register and then transferring this data to the data register when the CACHE PROGRAMMING command is issued. When the transfer is complete, the cache register is available to receive new data while the data register simultaneously programs the NAND Flash array. Typical page programming time (tPROG) for Micron NAND Flash devices is approximately 300µs for a 2KB page of data. PROGRAM PAGE CACHE MODE operation can improve data throughput by as much as 35% for x8 devices and 17% for x16 devices. This technical note discusses the benefits of PROGRAM PAGE CACHE MODE operations over normal PROGRAM PAGE operations. It also provides specific timing examples and instructions for performing PROGRAM PAGE CACHE MODE operations. Functionality Normal PROGRAM PAGE Operation Micron NAND Flash devices have two command latch cycles and five address latch cycles, which are followed by up to 2112 bytes or 1056 words of data in a normal PROGRAM PAGE operation. Following the ADDRESS LATCH cycles, R/B# goes LOW for t PROG (a typical time of 300µs and a maximum time of 700µs). Timing details are provided in Tables 2 and 3 on page 5 for x8 devices and Tables 4 and 5 on page 6 for x16 devices. Data can be programmed sequentially, one byte or word per cycle, depending on the width configuration of the NAND Flash device. Assuming 50ns cycles, timing is shown in Figure 1 on page 2. PDF: 09005aef8239bba2/Source: 09005aef8239bb33 tn2914_prog_page_cache_mode_perf_increase.fm - Rev. C 2/10 EN 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All information discussed herein is provided on an “as is” basis, without warranties of any kind. TN-29-14: Increasing NAND Flash Performance Functionality Figure 1: Normal PROGRAM PAGE Timing x8 Configurations (2 x 50ns) commands + (5 x 50ns) address + (2112 x 50ns) data + 300µs tPROG = 405.95µs per page x16 Configurations (2 x 50ns) commands + (5 x 50ns) address + (1056 x 50ns) data + 300µs tPROG = 353.15µs per page Figure 2: NAND Flash Typical PROGRAM PAGE Operation Timing CLE CE# tWC tADL WE# tWB tPROG ALE RE# I/Ox 80h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 DIN N SERIAL DATA INPUT command DIN M 1 up to M serial input 10h 70h PROGRAM command READ STATUS command Status R/B# x8 device: M = 2111 bytes x16 device: M = 1055 bytes Don‘t Care PDF: 09005aef8239bba2/Source: 09005aef8239bb33 tn2914_prog_page_cache_mode_perf_increase.fm - Rev. C 2/10 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. TN-29-14: Increasing NAND Flash Performance Functionality PROGRAM PAGE CACHE MODE Operation PROGRAM PAGE CACHE MODE operation begins with a PROGRAM PAGE CACHE MODE (80h-15h) command. Initially, data is copied into the cache register. When the 15h command completes, the data is transferred to the data register. Assuming that a page 0 address is issued in the PROGRAM PAGE CACHE MODE command, page 0 programming from the data register into the NAND Flash array begins when R/B# returns HIGH. When R/B# returns HIGH, another PROGRAM PAGE CACHE MODE command sequence can be issued to write new data to the cache register. The time that R/B# stays LOW is determined by the actual programming time. On the first programming pass, R/B# stays LOW for the time it takes to transfer data from the cache register to the data register. On subsequent passes prior to the last page, the data in the data register must be programmed into the NAND Flash memory array before additional data can be transferred from the cache register. When R/B# is used to determine programming status during PROGRAM PAGE CACHE MODE, a PROGRAM PAGE (80h-10h) command is used to program the last page of data. For the last cache programming sequence, R/B# stays LOW for tLPROG. Table 1 and Figure 3 on page 4 provide signal and timing information required for PROGRAM PAGE CACHE MODE operations. For programming a single page, the PROGRAM PAGE CACHE MODE operation takes the same time as a regular PROGRAM PAGE operation (see technical note TN-29-01); however, for two or more pages, there is a significant performance gain using PROGRAM PAGE CACHE MODE. The following examples assume tCBSY is equal to tPROG (TYP) after the first tCBSY. Table 1: Timing Delays Parameter Description Typ Max Unit tPROG Data transfer from data register to NAND Flash array Busy time for PROGRAM PAGE CACHE MODE Last-page programming time for PROGRAM PAGE CACHE MODE (see 2Gb NAND Flash data sheet) 300 3 – 700 700 – µs µs – tCBSY tLPROG1 Notes: 1. tLPROG = tPROG (last page) + tPROG ((last - 1) page) - command load time (last page) address load time (last page) - data load time (last page). PDF: 09005aef8239bba2/Source: 09005aef8239bb33 tn2914_prog_page_cache_mode_perf_increase.fm - Rev. C 2/10 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. tADL CLE CE# WE# Last page Last page - 1 PROGRAM PROGRAM Serial input Serial data input tWB tPROG tWB tCBSY ALE PDF: 09005aef8239bba2/Source: 09005aef8239bb33 tn2914_prog_page_cache_mode_perf_increase.fm - Rev. C 2/10 EN tWC Status 70h 10h DIN M DIN N Col Col Row Row Row add 1 add 2 add 1 add 2 add 3 80h 15h DIN M DIN N Row add 3 Row add 2 Row add 1 Col add 2 Col add 1 80h I/Ox PROGRAM PAGE CACHE MODE Operation Timing Figure 3: RE# R/B# Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. TN-29-14: Increasing NAND Flash Performance Functionality 4 Don‘t Care TN-29-14: Increasing NAND Flash Performance Functionality Table 2: Single-Block PROGRAM PAGE Operation Timing (x8) 50ns Cycle Time Process Repetitions Time Total Time Unit 1 5 2112 50 50 50 50 250 1 1 50 300 64 0.40595 ns ns ns µs ns µs µs ms MB/s Command latch (80h) Address latch Program data cycles Program data cycles total page Command latch (10h) R/B# LOW (tPROG) typical Total time to program a page Total time to program a block Speed (programming 64 pages in a block) Table 3: 105.6 50 300 405.95 25.98 5.2 Single-Block PROGRAM PAGE CACHE MODE Operation Timing (x8) 50ns Cycle Time Process Repetitions Time Total Time Unit 1 5 2112 50 50 50 50 250 ns ns ns µs ns µs µs µs µs ms µs µs ms MB/s Command latch (80h) Address latch Program data cycles Program data cycles total page Command latch (15h) R/B# LOW (1st tCBSY) Time to program page 0 R/B# LOW (tCBSY) typical Time to program page 1 Time to program pages 2:62 R/B# LOW (tLPROG) Time to program page 63 Total time to program a block Speed (programming 64 pages in a block) PDF: 09005aef8239bba2/Source: 09005aef8239bb33 tn2914_prog_page_cache_mode_perf_increase.fm - Rev. C 2/10 EN 5 1 1 50 3 1 300 61 1 1 0.300 494.65 105.6 50 3 108.95 300 300 18.3 494.65 494.65 19.20 7.04 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. TN-29-14: Increasing NAND Flash Performance Functionality Table 4: Single-Block PROGRAM PAGE Operation Timing (x16) 50ns Cycle Time Process Repetitions Time Total Time Unit 1 5 1056 50 50 50 50 250 1 1 50 300 64 0.35315 ns ns ns µs ns µs µs ms MB/s Command latch (80h) Address latch Program data cycles Program data cycles total page Command latch (10h) R/B# LOW (tPROG) Total time to program a page Total time to program a block Speed (programming 64 pages in a block) 52.50 50 300 353.15 22.60 5.98 Table 5 shows timing calculations for 50ns PROGRAM CLOCK cycles with PROGRAM PAGE CACHE MODE. Table 5: Single-Block PROGRAM PAGE CACHE MODE Operation Timing (x16) Process 50ns Cycle Time Number of Cycles Time/Cycle Total Time Units 1 5 1056 50 50 50 50 250 1 1 50 3 1 300 61 1 0.300 543.85 ns ns ns µs ns µs µs µs µs ms µs µs ms MB/s Timing for page 0 programming Command latch (80h) Address latch Program data cycles Program data cycles total page Command latch (15h) R/B# LOW (1st tCBSY) Time to program page 0 R/B# LOW (tCBSY) Time to program page 1 Time to program pages 2:62 R/B# LOW (tLPROG) Time to program page 63 Total time to program a block Speed (programming 64 pages in a block) PDF: 09005aef8239bba2/Source: 09005aef8239bb33 tn2914_prog_page_cache_mode_perf_increase.fm - Rev. C 2/10 EN 6 52.50 50 3 56.15 300 300 18.3 543.85 543.85 19.2 7.04 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. TN-29-14: Increasing NAND Flash Performance Conclusion Figure 4 shows the time savings associated with using PROGRAM PAGE CACHE MODE. Figure 4: PROGRAM PAGE CACHE MODE Time Savings Program Page 80h 80h 10h 10h Data In, up to 2112 bytes for Page 1 Data In, up to 2112 bytes for Page 0 R/B# tPROG tPROG (300µs) (300µs) Program Page Cache Mode 80h 15h 80h Data In, up to 2112 bytes for Page 0 15h 80h Data In, up to 2112 bytes for Page 1 15h 80h Data In, up to 2112 bytes for Page 2 R/B# tCBSY tCBSY tCBSY Time 0µs 100µs 200µs 300µs 400µs 500µs 600µs Commands 700µs Address Data Conclusion By using the PROGRAM PAGE CACHE MODE operation available in Micron NAND Flash devices, customers can experience programming performance gains and increased data throughput in their systems. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef8239bba2/Source: 09005aef8239bb33 tn2914_prog_page_cache_mode_perf_increase.fm - Rev. C 2/10 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved.