Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www.analog.com www.hittite.com Report Title: Qualification Test Report Report Type: See Attached Date: See Attached QTR: 2013-00500 Wafer Process: PHEMT-K HMC637A HMC6981 HMC7144 HMC7150 HMC7229 Rev: 04 QTR: 2013-00500 Wafer Process: PHEMT-K Rev: 04 Introduction The testing performed for this report is designed to accelerate the predominant failure mode, electro-migration (EM), for the devices under test. The devices are stressed at high temperature and DC biased to simulate a lifetime of use at typical operating temperatures. Using the Arrhenius equation, the acceleration factor (AF) is calculated for the stress testing based on the stress temperature and the typical use operating temperature. This report is intended to summarize all of the High Temperature Operating Life Test (HTOL) data for the PHEMT-K process. The FIT/MTTF data contained in this report includes all the stress testing performed on this process to date and will be updated periodically as additional data becomes available. Data sheets for the tested devices can be found at www.hittite.com. Glossary of Terms & Definitions: 1. CDM: Charged Device Model. A specified ESD testing circuit characterizing an event that occurs when a device acquires charge through some triboelectric (frictional) or electrostatic induction processes and then abruptly touches a grounded object or surface. This test was performed in accordance with JEDEC 22-C101. 2. ESD: Electro-Static Discharge. A sudden transfer of electrostatic charge between bodies or surfaces at different electrostatic potentials. 3. HBM: Human Body Model. A specified ESD testing circuit characterizing an event that occurs when a device is subjected to an electro-static charge stored in the human body and discharged through handling of the electronic device. This test was performed in accordance with JEDEC 22-A114. 4. HTOL: High Temperature Operating Life. This test is used to determine the effects of bias conditions and temperature on semiconductor devices over time. It simulates the devices’ operating condition in an accelerated way, through high temperature and/or bias voltage, and is primarily for device qualification and reliability monitoring. This test was performed in accordance with JEDEC JESD22-A108. 5. HTSL: High Temperature Storage Life. Devices are subjected to 1000 hours at 150oC per JESD22-A103. 6. MSL: Moisture sensitivity level pre-conditioning is performed per JESD22-A113. 7. Operating Junction Temp (Toj): Temperature of the die active circuitry during typical operation. 8. Stress Junction Temp (Tsj): Temperature of the die active circuitry during stress testing. 9. UHAST: Unbiased Highly Accelerated Stress Test. Devices are subjected to 96 hours of 85% relative humidity at a temperature of 130°C and pressure (15 PSIG). This test is performed in accordance with JESD22-A118. QTR: 2013-00500 Wafer Process: PHEMT-K Rev: 04 Qualification Sample Selection: All qualification devices used were manufactured and tested on standard production processes and met pre-stress acceptance test requirements. Summary of Qualification Tests: HMC7150 (QTR2013-00338) QTY IN QTY OUT PASS/FAIL Initial Electrical Test 356 356 Pass MSL-1 Preconditioning 160 160 Pass Post MSL-1 Electrical Test 160 160 Pass UHAST (Preconditioned) 80 80 Pass Post UHAST Electrical Test 80 80 Pass Temp. Cycle (Preconditioned) 80 80 Pass Post Temp Cycle Electrical Test 80 80 Pass HTSL 80 80 Pass Post HTSL Electrical Test 80 80 Pass HTOL 80 80 Pass Post HTOL Electrical test 80 80 Pass ESD Exposure 36 36 Pass Post ESD Electrical Test 36 36 Pass TEST NOTES HBM = Class 1A CDM = Passed 1500V MM = Passed 75V QTR: 2013-00500 Wafer Process: PHEMT-K Rev: 04 HMC7144 (QTR2013-00361) QTY IN 351 QTY OUT 351 MSL-1 Preconditioning 156 156 Pass Post MSL-1 Electrical Test 156 156 Pass UHAST (Preconditioned) 78 78 Pass Post UHAST Electrical Test 78 78 Pass Temp. Cycle (Preconditioned) 78 78 Pass Post Temp Cycle Electrical Test 78 78 Pass HTSL 78 78 Pass Post HTSL Electrical Test 78 78 Pass HTOL 81 81 Pass Post HTOL Electrical test 81 81 Pass ESD Exposure 36 36 Pass TEST Initial Electrical Test Post ESD Electrical Test 36 36 PASS/FAIL NOTES Pass Pass HBM = Class 1A CDM = Passed 1500V MM = Passed 75V QTR: 2013-00500 Wafer Process: PHEMT-K Rev: 04 HMC6981 (QTR2012-00517) QTY IN 267 QTY OUT 267 MSL-3 Preconditioning 80 80 Pass Post MSL-3 Electrical Test 80 80 Pass Temp. Cycle (Preconditioned) 80 80 Pass Post Temp Cycle Electrical Test 80 80 Pass HTSL 80 80 Pass Post HTSL Electrical Test 80 80 Pass HTOL 80 80 Pass Post HTOL Electrical test 80 80 Pass ESD Exposure 27 27 Pass Post ESD Electrical Test 27 27 Pass Physical Dimensions 15 15 Pass Solderability 6 6 Pass X-ray Analysis 6 6 Pass TEST Initial Electrical Test PASS/FAIL NOTES Pass HBM = Passed, 125V CDM = Passed 2000V QTR: 2013-00500 Wafer Process: PHEMT-K Rev: 04 PHEMT-K Failure Rate Estimate Based on the HTOL test results, a failure rate estimation was determined using the following parameters: With device ambient case temp, Tc = 85°C HMC7150 (QTR2013-00338) Operating Junction Temp (Toj) = 96°C(369°K) Stress Junction Temp (Tsj) = 175°C(448°K) HMC7144 (QTR2013-00361) Operating Junction Temp (Toj) = 96°C(369°K) Stress Junction Temp (Tsj) = 175°C(448°K) HMC6981 (QTR2012-00517) Operating Junction Temp (Toj) = 136°C(409°K) Stress Junction Temp (Tsj) = 160°C(433°K) Device hours: HMC7150 (QTR2013-00338) = (80 X 1000hrs) = 80,000 hours HMC7144 (QTR2013-00361) = (81 X 1000hrs) = 81,000 hours HMC6981 (QTR2012-00517) = (80 X 1000hrs) = 80,000 hours For PHEMT-K MMIC, Activation Energy = 1.43 eV Acceleration Factor (AF): QTR: 2013-00500 Wafer Process: PHEMT-K Rev: 04 HMC7150 (QTR2013-00338) Acceleration Factor = exp[1.43/8.6 e-5(1/369-1/448)] = 2824.9 HMC7144 (QTR2013-00361) Acceleration Factor = exp[1.43/8.6 e-5(1/369-1/448)] = 2824.9 HMC6981 (QTR2012-00517) Acceleration Factor = exp[1.43/8.6 e-5(1/409-1/433)] = 9.5 Equivalent hours = Device hours x Acceleration Factor Equivalent hours = (80,000x2824.9)+(81,000x2824.9)+(80,000x9.5) = 4.63x108 hours Since there was no failures and we used a time terminated test, F=0, and R = 2F+2 = 2 The failure rate was calculated using Chi Square Statistic: at 60% and 90% Confidence Level (CL), with 0 units out of spec and a 85°C device junction temp; Failure Rate 60 = [(2)60,2]/(2X 4.63x108 )] = 1.8/ 9.26x108 = 1.98x10-9 failures/hour or 2.0 FIT or MTTF = 5.06x108 Hours 90 = [(2)90,2]/(2X 4.63x108 )] = 4.6/ 9.26x108 = 4.99x10-9 failures/hour or 5.0 FIT or MTTF = 2.01x108 Hours