Semiconductor Qualification Test Report: PHEMT-L (QTR: 2013-00266)

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Report Title:
Qualification Test Report
Report Type:
See Attached
Date:
See Attached
QTR: 2013- 00266
Wafer Process: PHEMT-L
HMC1040
HMC1049
HMC1065
Rev: 02
QTR: 2013- 00266
Wafer Process: PHEMT-L
Rev: 02
Introduction
The testing performed for this report is designed to accelerate the predominant failure mode, electro-migration
(EM), for the devices under test. The devices are stressed at high temperature and DC biased to simulate a lifetime
of use at typical operating temperatures. Using the Arrhenius equation, the acceleration factor (AF) is calculated for
the stress testing based on the stress temperature and the typical use operating temperature.
This report is intended to summarize all of the High Temperature Operating Life Test (HTOL) data for the
PHEMT-L process. The FIT/MTTF data contained in this report includes all the stress testing performed on this
process to date and will be updated periodically as additional data becomes available. Data sheets for the tested
devices can be found at www.hittite.com.
Glossary of Terms & Definitions:
1. CDM: Charged Device Model. A specified ESD testing circuit characterizing an event that occurs when a device
acquires charge through some triboelectric (frictional) or electrostatic induction processes and then abruptly
touches a grounded object or surface. This test was performed in accordance with JEDEC 22-C101.
2. ESD: Electro-Static Discharge. A sudden transfer of electrostatic charge between bodies or surfaces at different
electrostatic potentials.
3. HAST: Highly Accelerated Stress Test (biased). Devices are subjected to 96 hours of 85% relative humidity at a
temperature of 130°C and pressure (15 PSIG), while DC biased. This test is performed in accordance with
JESD22-A110.
4. HBM: Human Body Model. A specified ESD testing circuit characterizing an event that occurs when a device is
subjected to an electro-static charge stored in the human body and discharged through handling of the electronic
device. This test was performed in accordance with JEDEC 22-A114.
5. HTOL: High Temperature Operating Life. This test is used to determine the effects of bias conditions and
temperature on semiconductor devices over time. It simulates the devices’ operating condition in an accelerated
way, through high temperature and/or bias voltage, and is primarily for device qualification and reliability
monitoring. This test was performed in accordance with JEDEC JESD22-A108.
6. HTSL: High Temperature Storage Life. Devices are subjected to 1000 hours at 150oC per JESD22-A103.
7. MSL: Moisture sensitivity level pre-conditioning is performed per JESD22-A113.
8. Operating Junction Temp (Toj): Temperature of the die active circuitry during typical operation.
9. Stress Junction Temp (Tsj): Temperature of the die active circuitry during stress testing.
QTR: 2013- 00266
Wafer Process: PHEMT-L
Rev: 02
10. UHAST: Unbiased Highly Accelerated Stress Test. Devices are subjected to 96 hours of 85% relative humidity at
a temperature of 130°C and pressure (15 PSIG). This test is performed in accordance with JESD22-A118.
Qualification Sample Selection:
All qualification devices used were manufactured and tested on standard production processes and met pre-stress
acceptance test requirements.
Summary of Qualification Tests:
HMC1040 (QTR2012-00327)
Initial electrical Test
QTY
IN
344
QTY
OUT
344
MSL-3 Precondition
154
154
Complete
Post MSL3 Electrical Test
154
154
Pass
UHAST (preconditioned)
77
77
Complete
Post UHAST electrical Test
77
77
Pass
Temp. Cycle (preconditioned)
77
77
Complete
Post Temp Cycle electrical Test
77
77
Pass
HTSL
77
77
Complete
Post HTSL Electrical Test
77
77
Pass
HTOL
81
81
Complete
Post HTOL Electrical test
81
81
Pass
Physical Dimensions
15
15
Pass
Solderability
6
6
Pass
ESD Exposure
27
27
Complete
Post ESD Electrical Test
27
27
Complete
TEST
PASS/FAIL
NOTES
Pass
HBM Class 0
CDM Class IV
QTR: 2013- 00266
Wafer Process: PHEMT-L
Rev: 02
QTR: 2013- 00266
Wafer Process: PHEMT-L
Rev: 02
HMC1065 (QTR2013-00194)
Initial electrical Test
QTY
IN
302
QTY
OUT
302
MSL-1 Precondition
105
105
Complete
Post MSL1 Electrical Test
105
105
Pass
HAST (preconditioned)
25
25
Complete
Post HAST electrical Test
25
25
Pass
Temp. Cycle (preconditioned)
80
80
Complete
Post Temp Cycle electrical Test
80
80
Pass
HTSL
80
80
Complete
Post HTSL Electrical Test
80
80
Pass
HTOL
78
78
Complete
Post HTOL Electrical test
78
78
Pass
Physical Dimensions
15
15
Pass
Solderability
6
6
Pass
ESD Exposure
39
39
Complete
Post ESD Electrical Test
39
39
Complete
TEST
PASS/FAIL
NOTES
Pass
HBM Class 1A
CDM Class IV
QTR: 2013- 00266
Wafer Process: PHEMT-L
Rev: 02
PHEMT-L Failure Rate Estimate
Based on the HTOL test results, a failure rate estimation was determined using the following
parameters:
With device case temp, Tc = 85°C
HMC1040 (QTR2012-00327)
Operating Junction Temp (Toj) =117°C(390°K)
Stress Junction Temp (Tsj) = 175°C(448°K)
HMC1065 (QTR2013-00194)
Operating Junction Temp (Toj) =125°C(398°K)
Stress Junction Temp (Tsj) = 175°C(448°K)
Device hours:
HMC1040 (QTR2012-00327) = (81 X 1000hrs) = 81,000 hours
HMC1065 (QTR2013-00194) = (78 X 1000hrs) = 78,000 hours
For PHEMT-L MMIC, Activation Energy = 1.16 eV
Acceleration Factor (AF):
HMC1040 (QTR2012-00327) Acceleration Factor = exp[1.16/8.6 e-5(1/390-1/448)] = 88.0
HMC1065 (QTR2013-00194) Acceleration Factor = exp[1.16/8.6 e-5(1/398-1/448)] = 43.9
QTR: 2013- 00266
Wafer Process: PHEMT-L
Rev: 02
Equivalent hours = Device hours x Acceleration Factor
Equivalent hours = (81,000x88.0)+(78,000x43.9) = 1.06x107 hours
Since there were no failures and we used a time terminated test, F=0, and R = 2F+2 = 2
The failure rate was calculated using Chi Square Statistic:
at 60% and 90% Confidence Level (CL), with 0 units out of spec
and a 85°C package backside temp;
Failure Rate
λ60 = [(χ2)60,2]/(2X 1.06x107 )] = 1.8/ 2.11x107 = 8.67x10-8 failures/hour or 86.7 FIT or MTTF = 1.15x107 Hours
λ90 = [(χ2)90,2]/(2X 1.06x107 )] = 4.6/ 2.11x107 = 2.18x10-7 failures/hour or 218
FIT or MTTF = 4.58x106 Hours