Analog Devices Welcomes Hittite Microwave Corporation NO CONTENT ON THE ATTACHED DOCUMENT HAS CHANGED www.analog.com www.hittite.com Report Title: Qualification Test Report Report Type: See Attached Date: See Attached Wafer Process: PHEMT-B QTR: 07001 Rev: 02 HMC154 HMC356 HMC372 HMC373 HMC374 HMC375 HMC376 HMC382 HMC484 HMC486 HMC487 HMC489 HMC536 HMC546 HMC549 HMC590 HMC591 HMC592 HMC646 Note: This qualification was designed to evaluate the pHEMT-B process. The package type is only specific to the MS8G which was tested by HMC484MS8G. Other package qualifications are available at www.Hittite.com. 1.0 Introduction The definition of a qualification family, as defined by EIA/JESD47 Stress-Test-Driven Qualification of integrated Circuits, is all devices that use the same wafer fabrication technology, wafer fabrication process and wafer fabrication site. This qualification procedure is designed to satisfy the reliability requirements for Hittite Microwave Corporation’s GaAs MMIC Switches using the pHEMT-B wafer process. The HMC484MS8G was chosen as the qualification vehicle to qualify the pHEMT-B Power process. A complete data sheet for the HMC484MS8G can be found at www.hittite.com. 1.1 General Description The pHEMT-B GaAs wafer process uses optical gate stepper lithography and is ideal for switches, amplifiers & LNAs. The entire die, with the exception of bridge metal and bonding areas, is fully passivated to help protect the device from environmental conditions. The HMC484MS8G is a low cost SPDT switch in 8-lead MSOPG package for use in transmitreceive applications which require very low distortion at high input signal power levels, through 10 watts (+40 dBm). The device can control signals from DC to 3.0 GHz. The design provides exceptional intermodulation performance; > +70 dBm third order intercept at +5 volt bias. RF1 and RF2 are reflective shorts when “OFF”. On-chip circuitry allows single positive supply operation from +3 Vdc to +10 Vdc at very low DC current with control inputs compatible with CMOS and most TTL logic families. Applications include wireless infrastructure, ISM/Cellular portables/handsets, automotive telematics, mobile radio, test equipment. 2.0 Summary of Results All testing has been completed. Activation energy for pHEMT-B process is 1.4 eV. Using 85 °C as the normal operating temperature of the device, the equivalent device hours for 74,000 hours at 125 °C is calculated to be 7.18 X 106 hours. Using a Chi-Square 90% confidence interval, the failure rate is calculated to be better than 3.23 x10-7 failures per hour or 323 FIT. PAR A TEST QTY IN QTY OUT 4.1.1 Initial Electrical 231 231 Complete IR Reflow 231 231 Complete HTOL, 1000 hours 77 77 Complete Post HTOL Electrical Test 77 74 Autoclave 77 77 PASS/FAIL NOTES 3 failures due to mechanical damage during electrical testing. Complete 2 failures due to mechanical damage during electrical testing. Post Autoclave Electrical Test 77 75 THB, 1000 hours 77 77 Complete Post THB Electrical Test 77 77 Pass/No Failures pHEMT-B Failure Rate Estimate Based on the HTOL results, a failure rate estimation was determined using the following parameters: To=85 °C(358 °K) Ta=125 °C(398 °K) Device hours = (74 X 1000hrs) = 74,000 hours For 0.5µm pHEMT-B GaAs MMIC, Activation Energy = 1.4 eV Acceleration Factor = exp[1.4/8.6 e-5(1/358-1/398)] = 97 (Arrhenius Equation) Equivalent hours = 74,000 hours X 97 = 7.18 e6 hours Since there were no relevant failures, C=0. Since we used a time terminated test R = C+1 = 1 The GaAs failure rate was calculated using Chi Square Statistic: λα = [(χ2)α,2r]/2t λ60 = [(χ2)60,2]/(2X 7.18 e6)] = 1.8/1.44 e7 = 1.25 e-7 failures/hour or 125 FIT λ70 = [(χ2)70,2]/(2X 7.18 e6)] = 2.4/1.44 e7 = 1.67 e-7 failures/hour or 167 FIT λ90 = [(χ2)90,2]/(2X 7.18 e6)] = 4.6/1.44 e7 = 3.190 e-7 failures/hour or 319 FIT 3.0 Qualification Flow Chart Physical Attributes Process Tests Physical Attribute Testing n=20 Initial Electrical Parameters n=231 IR Reflow Simulation n=231 Autoclave n=77 High Temp. Operating Life n=77 Final Electrical Parameters n=231 Bond Pull n=10 (30 wires) Temperature Humidity Bias n=77 Die Shear n=10 SEM Inspection n=5 CrossSection Inspection n=5 4.0 Test Procedures 4.1 MMIC related tests - These tests are designed to demonstrate that the GaAs MMIC devices produced with the 0.5µm PHEMT process are capable of maintaining the specified parameters throughout their useful life under rated operating conditions. The HMC484MS8G die was chosen to qualify the pHEMT-B process. The results of these tests qualify by similarity all other products using the same wafer process. A complete data sheet for the HMC484MS8G can be found on our catalog website. 4.1.1 Initial Characteristics - 231 HMC484MS8G devices were electrically tested for DC and critical RF parameters. at ambient temperature (+25 °C). There were no failures in this test. 4.1.2 IR Reflow Simulation - 231 devices from 4.1.1 are subjected to the following temperature profile in air: This test was performed at Hittite. 4.1.2.1 Autoclave - 77 devices from 4.1.2 were subjected to 96 hours of un-biased Autoclave (121°C/100% RH, 14.7 psig). This test was performed at Hittite. 4.1.2.2 High Temperature Operating Life - 77 devices from 4.1.2 were subjected to 1000 hours of accelerated burn-in at Tj=125 °C with a 5 volt constant bias applied to Vdd (pin 4) and pins 1,2,7,8, and paddle backside grounded to force both paths of the switch into the off state. This test is performed at Hittite. 4.1.2.3 Temperature Humidity Bias (THB) - 77 devices from 4.1. were subjected to 1000 hours of temperature humidity bias (THB) with a 5 volt constant bias applied to Vdd (pin 4) and pins 1,2,7,8, and paddle backside grounded to force both paths of the switch into the off state. This test is performed at Hittite. 4.1.6 Final Characteristics - All devices from 4.1.2 were electrically tested to DC and critical RF parameters at ambient temperature (+25 °C). Any out of specification parameter is considered a failure. This test was performed at Hittite. There were no failures in this test. 5.0 Physical Attributes 5.1 Bond Pull -10 die from the wafer (4 quadrants and center) were selected. The die were mounted to test coupons with conductive epoxy. Wires were thermosonic bonded from the die to the coupon. 3 wires on each of the ten samples (30 total) were pulled to destruction to the requirements of MIL-STD-883 Method 2011, condition D. Variables data was recorded. This test was performed at Hittite. There were no failures in this test. 5.2 Die Shear – The 10 die from 5.1 were sheared to destruction to the requirements of MIL-STD-883 Method 2019. Variables data was recorded. This test was performed at Hittite. There were no failures in this test. 5.3 Metal and Dielectric Thickness – 5 die from each wafer lot (4 quadrants and center) were selected. The die were mounted, cross-sectioned and polished. Metal and dielectric thickness was recorded for each layer and compared to expected values. There were no anomalies. This test was performed at Oneida Research Services in Whitesboro, NY. (Reference Photo 1) 5.4 SEM Inspection – 5 die from each wafer lot (4 quadrants and center) were selected. The die were mounted and sequentially delayered to perform a comprehensive inspection to the requirements of MIL-STD-883 Method 2018. There were no anomalies. This test was performed at Oneida Research Services in Whitesboro, NY. (Reference Photos 2-4) Photo 1 SEM micrograph of structure, Wafer Lot FPA63816M, Wafer 089, Die 38401, 2500X, 20 kV Photo 2 SEM micrograph of typical ohmic metallization, Wafer Lot FPA63816M, Wafer 089, Die 38401, 5000X, 20 kV \ Photo 3 SEM image of typical gate metallization, Wafer Lot FPA63816M, Wafer 089, Die 38401, 10000X Photo 4 SEM image of metal to metal layer contacts, Wafer Lot FPA63816M, Wafer 089, Die 38401, 1000X Photo 5 SEM micrograph of airbridge, Wafer Lot FPA63816M, Wafer 089, Die 38401, 2000X, 20 kV