FEATURES Low noise preamplifier Ultrasound amplifiers PLL loop filters High performance ADC drivers DAC buffers NC 1 8 DISABLE –IN 2 7 +VS +IN 3 6 OUT –VS 4 5 NC Figure 1. 8-Lead SOIC (ADA4897-1) 8 VS = ±5V 7 6 5 4 3 2 1 0 1 10 100 1k 10k 100k 1M 5M FREQUENCY (Hz) Figure 2. Voltage Noise vs. Frequency GENERAL DESCRIPTION The ADA4896-2/ADA4897-1/ADA4897-2 are unity-gain stable, low noise, rail-to-rail output, high speed voltage feedback amplifiers that have a quiescent current of 3 mA. With a 1/f noise of 2.4 nV/√Hz at 10 Hz and a spurious-free dynamic range of −80 dBc at 2 MHz, the ADA4896-2/ADA4897-1/ADA4897-2 are ideal solutions in a variety of applications, including ultrasound, low noise preamplifiers, and drivers of high performance ADCs. The Analog Devices, Inc., proprietary next-generation SiGe bipolar process and innovative architecture enable such high performance amplifiers. The ADA4896-2/ADA4897-1/ADA4897-2 have 230 MHz bandwidth, 120 V/μs slew rate, and settle to 0.1% in 45 ns. With a wide supply voltage range of 3 V to 10 V, the ADA4896-2/ ADA4897-1/ADA4897-2 are ideal candidates for systems that require high dynamic range, precision, low power, and high speed. The ADA4896-2 is available in 8-lead LFCSP and 8-lead MSOP packages. The ADA4897-1 is available in 8-lead SOIC and 6-lead SOT-23 packages. The ADA4897-2 is available in a 10-lead MSOP package. The ADA4896-2/ADA4897-1/ADA4897-2 operate over the extended industrial temperature range of −40°C to +125°C. 09447-102 APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VOLTAGE NOISE (nV/√Hz) Low wideband noise 1 nV/√Hz 2.8 pA/√Hz Low 1/f noise: 2.4 nV/√Hz at 10 Hz Low distortion: −115 dBc at 100 kHz, VOUT = 2 V p-p Low power: 3 mA per amplifier Low input offset voltage: 0.5 mV maximum High speed −3 dB bandwidth: 230 MHz (G = +1) Slew rate: 120 V/μs Settling time to 0.1%: 45 ns Rail-to-rail output Wide supply range: 3 V to 10 V Disable feature (ADA4897-1/ADA4897-2) 09447-101 Data Sheet 1 nV/√Hz, Low Power, Rail-to-Rail Output Amplifiers ADA4896-2/ADA4897-1/ADA4897-2 Table 1. Other Low Noise Amplifiers Part No. AD797 AD8021 AD8099 AD8045 ADA4899-1 ADA4898-1/ ADA4898-2 VN (nV/√Hz) At 1 kHz At 100 kHz 0.9 0.9 5 2.1 3 0.95 6 3 1.4 1 0.9 0.9 BW (MHz) 8 490 510 1000 600 65 Supply Voltage (V) 10 to 30 5 to 24 5 to 12 3.3 to 12 5 to 12 10 to 32 Table 2. Complementary ADCs Part No. AD7944 AD7985 AD7986 Bits 14 16 18 Speed (MSPS) 2.5 2.5 2 Power (mW) 15.5 15.5 15 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. Powered by TCPDF (www.tcpdf.org) IMPORTANT LINKS for the ADA4896-2_4897-1_4897-2* Last content update 07/24/2013 06:07 pm PARAMETRIC SELECTION TABLES DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE Find Similar Products By Operating Parameters Analog Filter Wizard 2.0 ADA44896/7 SPICE Macro Model, Ver. 2.1 DOCUMENTATION AN-0991: Active Filter Evaluation Board for Standard SOIC Op Amps AN-581: Biasing and Decoupling Op Amps in Single Supply Applications AN-402: Replacing Output Clamping Op Amps with Input Clamping Amps ADA4895 / 6 / 7 Fastest, Low Noise, Low Power, Rail-to-Rail Amps Op Amp Applications Handbook MT-032: Ideal Voltage Feedback (VFB) Op Amp MT-033: Voltage Feedback Op Amp Gain and Bandwidth MT-047: Op Amp Noise MT-048: Op Amp Noise Relationships: 1/f Noise, RMS Noise, and Equivalent Noise Bandwidth MT-049: Op Amp Total Output Noise Calculations for Single-Pole System MT-050: Op Amp Total Output Noise Calculations for Second-Order System MT-052: Op Amp Noise Figure: Don't Be Mislead MT-053: Op Amp Distortion: HD, THD, THD + N, IMD, SFDR, MTPR MT-056: High Speed Voltage Feedback Op Amps MT-058: Effects of Feedback Capacitance on VFB and CFB Op Amps MT-059: Compensating for the Effects of Input Capacitance on VFB and CFB Op Amps Used in Current-to-Voltage Converters MT-060: Choosing Between Voltage Feedback and Current Feedback Op Amps (For the ADA4897-1 & ADA4897-2) ADA4897-1-EP/ADA4897-2-EP: 1 nV/√Hz, Low Power, Rail-to-Rail Output Amplifiers Data Sheet (For the ADA4897-1 & ADA4897-2) CN-0307 A 16-Bit, 6 MSPS SAR ADC System with Low Power Input Drivers and Reference Optimized for Multiplexed Applications (For the ADA4896-2) UG-267: Evaluation Board User Guide (For the ADA4896-2) UG-129: Evaluation Board User Guide (For the ADA4897-1) UG-127: Universal Evaluation Board for High Speed Op Amps in SOT-23-5/SOT-23-6 Packages (For the ADA4897-1) UG-101: Evaluation Board User Guide EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for the ADA4896-2 View the Evaluation Boards and Kits page for the ADA4897-1 View the Evaluation Boards and Kits page for the ADA4897-2 Symbols and Footprints for the ADA4896-2 Symbols and Footprints for the ADA4897-1 Symbols and Footprints for the ADA4897-2 DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: Americas: Europe: China: India: Russia: 1-800-262-5643 00800-266-822-82 4006-100-006 1800-419-0108 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY PRODUCT RECOMMENDATIONS & REFERENCE DESIGNS (For the ADA4897-1 & ADA4897-2) CN-0307: A 16-Bit, 6 MSPS SAR ADC System with Low Power Input Drivers and Reference Optimized for Multiplexed Applications ADA4896-2 ADA4897-1 ADA4897-2 Find Local Distributors * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 17 Applications ....................................................................................... 1 Amplifier Description................................................................ 17 General Description ......................................................................... 1 Input Protection ......................................................................... 17 Functional Block Diagram .............................................................. 1 Disable Operation ...................................................................... 17 Revision History ............................................................................... 2 DC Errors .................................................................................... 18 Specifications..................................................................................... 3 Bias Current Cancellation ......................................................... 18 ±5 V Supply ................................................................................... 3 Noise Considerations ................................................................. 19 +5 V Supply ................................................................................... 4 Capacitance Drive ...................................................................... 19 +3 V Supply ................................................................................... 6 Applications Information .............................................................. 20 Absolute Maximum Ratings............................................................ 8 Typical Performance Values ...................................................... 20 Thermal Resistance ...................................................................... 8 Low Noise, Gain Selectable Amplifier ..................................... 21 Maximum Power Dissipation ..................................................... 8 Medical Ultrasound Applications ............................................ 22 ESD Caution .................................................................................. 8 Layout Considerations ............................................................... 24 Pin Configurations and Function Descriptions ........................... 9 Outline Dimensions ....................................................................... 25 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 27 REVISION HISTORY 4/12—Rev. A to Rev. B Changed 6-Lead Single SOT-23 (ADA4897-1) Thermal Reistance from 306°C/W to 150°C/W ........................................... 8 Changes to Figure 3 .......................................................................... 8 10/11—Rev. 0 to Rev. A Added ADA4897-2 and 10-Lead MSOP ......................... Universal Change to Table 1 ............................................................................. 1 Changes to Table 3 ............................................................................ 3 Changes to Table 4 ............................................................................ 4 Changes to Table 5 ............................................................................ 6 Changes to Table 7 and Figure 3 ..................................................... 8 Changes to Figure 4, Table 8, and Table 9 ..................................... 9 Added Figure 8 and Table 10; Renumbered Sequentially ......... 10 Changed Summary Statement for Typical Performance Characteristics Section................................................................... 11 Changes to Figure 18 ...................................................................... 12 Change to Figure 20 ....................................................................... 12 Change to Figure 26; Moved Figure 26........................................ 13 Changes to Figure 37...................................................................... 15 Changes to Amplifier Description Section, Disable Operation Section, Figure 44, and Figure 45 ................................................. 17 Added Bias Current Cancellation Section, Figure 47, Table 11, and Table 12 .................................................................... 18 Changes to Table 13 ....................................................................... 20 Changes to Low Noise, Gain Selectable Amplifier Section and Figure 52................................................................................... 21 Deleted Figure 51............................................................................ 22 Changes to Power Supply Bypassing Section ............................. 24 Moved Figure 57 ............................................................................. 25 Moved Figure 58 ............................................................................. 26 Added Figure 60 ............................................................................. 27 Changes to Ordering Guide .......................................................... 27 7/11—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 SPECIFICATIONS ±5 V SUPPLY TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) Input Voltage Noise Input Current Noise 0.1 Hz to 10 Hz Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Differential Input Capacitance Common-Mode Differential Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Positive Negative Output Current Short-Circuit Current Capacitive Load Drive Test Conditions/Comments Min Typ Max Unit G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.02 V p-p G = +2, VOUT = 2 V p-p, RL = 100 Ω G = +2, VOUT = 6 V step G = +2, VOUT = 2 V step G = +2, VOUT = 2 V step 230 30 90 7 120 45 90 MHz MHz MHz MHz V/μs ns ns VOUT = 2 V p-p fC = 100 kHz fC = 1 MHz fC = 2 MHz fC = 5 MHz f = 10 Hz f = 100 kHz f = 10 Hz f = 100 kHz G = +101, RF = 1 kΩ, RG = 10 Ω −115 −93 −80 −61 2.4 1 11 2.8 99 dBc dBc dBc dBc nV/√Hz nV/√Hz pA/√Hz pA/√Hz nV p-p −500 −17 −0.6 100 VOUT = −4 V to +4 V VCM = −2 V to +2 V −92 VIN = ±5 V, G = +2 RL = 1 kΩ RL = 100 Ω RL = 1 kΩ RL = 100 Ω SFDR = −45 dBc Sinking/sourcing 30% overshoot, G = +2 Rev. B | Page 3 of 28 4.85 4.5 −4.85 −4.5 −28 0.2 −11 3 −0.02 110 +500 −4 +0.6 μV μV/°C μA nA/°C μA dB 10 10 MΩ kΩ 3 11 −4.9 to +4.1 −120 pF pF V dB 81 ns 4.96 4.73 −4.97 −4.84 80 135 39 V V V V mA mA pF ADA4896-2/ADA4897-1/ADA4897-2 Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Data Sheet Test Conditions/Comments Min Typ Max Unit 2.8 3 to 10 3.0 0.13 3.2 0.25 V mA mA −96 −96 −125 −121 dB dB Enabled Disabled >+VS − 0.5 <+VS − 2 V V DISABLE = +5 V DISABLE = −5 V −1.2 −40 μA μA 0.25 12 μs μs DISABLE = −5 V Power Supply Rejection Ratio (PSRR) Positive Negative DISABLE PIN (ADA4897-1/ADA4897-2) DISABLE Voltage Input Current Enabled Disabled Switching Speed Enabled Disabled +VS = 4 V to 6 V, −VS = −5 V +VS = 5 V, −VS = −4 V to −6 V +5 V SUPPLY TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) Input Voltage Noise Input Current Noise 0.1 Hz to 10 Hz Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain Test Conditions/Comments Min Typ Max Unit G = +1, VOUT = 0.02 V p-p G = +1, VOUT = 2 V p-p G = +2, VOUT = 0.02 V p-p G = +2, VOUT = 2 V p-p, RL = 100 Ω G = +2, VOUT = 3 V step G = +2, VOUT = 2 V step G = +2, VOUT = 2 V step 230 30 90 7 100 45 95 MHz MHz MHz MHz V/μs ns ns VOUT = 2 V p-p fC = 100 kHz fC = 1 MHz fC = 2 MHz fC = 5 MHz f = 10 Hz f = 100 kHz f = 10 Hz f = 100 kHz G = +101, RF = 1 kΩ, RG = 10 Ω −115 −93 −80 −61 2.4 1 11 2.8 99 dBc dBc dBc dBc nV/√Hz nV/√Hz pA/√Hz pA/√Hz nV p-p −500 −17 VOUT = 0.5 V to 4.5 V Rev. B | Page 4 of 28 −0.6 97 −30 0.2 −11 3 −0.02 110 +500 −4 +0.6 μV μV/°C μA nA/°C μA dB Data Sheet Parameter INPUT CHARACTERISTICS Input Resistance Common-Mode Differential Input Capacitance Common-Mode Differential Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Positive Negative Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier ADA4896-2/ADA4897-1/ADA4897-2 Test Conditions/Comments Min Input Current Enabled Disabled Switching Speed Enabled Disabled Max Unit 10 10 MΩ kΩ 3 11 0.1 to 4.1 −118 pF pF V dB 96 ns 4.98 4.88 0.014 0.08 70 125 39 V V V V mA mA pF 2.6 3 to 10 2.8 0.05 V mA mA −96 −96 −123 −121 dB dB Enabled Disabled >+VS − 0.5 <+VS − 2 V V DISABLE = +5 V DISABLE = 0 V −1.2 −20 μA μA 0.25 12 μs μs VCM = 1 V to 4 V −91 VIN = 0 V to 5 V, G = +2 RL = 1 kΩ RL = 100 Ω RL = 1 kΩ RL = 100 Ω SFDR = −45 dBc Sinking/sourcing 30% overshoot, G = +2 4.85 4.8 0.15 0.2 DISABLE = 0 V Power Supply Rejection Ratio (PSRR) Positive Negative DISABLE PIN (ADA4897-1/ADA4897-2) DISABLE Voltage Typ +VS = 4.5 V to 5.5 V, −VS = 0 V +VS = 5 V, −VS = −0.5 V to +0.5 V Rev. B | Page 5 of 28 2.9 0.18 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet +3 V SUPPLY TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. Table 5. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Harmonic Distortion (SFDR) Input Voltage Noise Input Current Noise 0.1 Hz to 10 Hz Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Bias Current Drift Input Bias Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Common-Mode Differential Input Capacitance Common-Mode Differential Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) OUTPUT CHARACTERISTICS Output Overdrive Recovery Time Output Voltage Swing Positive Negative Output Current Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current per Amplifier Test Conditions/Comments Min Typ Max Unit G = +1, VOUT = 0.02 V p-p G = −1, VOUT = 1 V p-p G = +2, VOUT = 0.02 V p-p G = +2, VOUT = 2 V p-p, RL = 100 Ω G = +2, VOUT = 1 V step G = +2, VOUT = 2 V step G = +2, VOUT = 2 V step 230 45 90 7 85 45 96 MHz MHz MHz MHz V/μs ns ns fC = 100 kHz, VOUT = 2 V p-p, G = +2 fC = 1 MHz, VOUT = 1 V p-p, G = −1 fC = 2 MHz, VOUT = 1 V p-p, G = −1 fC = 5 MHz, VOUT = 1 V p-p, G = −1 f = 10 Hz f = 100 kHz f = 10 Hz f = 100 kHz G = +101, RF = 1 kΩ, RG = 10 Ω −105 −84 −77 −60 2.3 1 11 2.8 99 dBc dBc dBc dBc nV/√Hz nV/√Hz pA/√Hz pA/√Hz nV p-p −500 −17 VOUT = 0.5 V to 2.5 V VCM = 1.1 V to 1.9 V −0.6 95 −90 VIN = 0 V to 3 V, G = +2 RL = 1 kΩ RL = 100 Ω RL = 1 kΩ RL = 100 Ω SFDR = −45 dBc Sinking/sourcing 30% overshoot, G = +2 2.85 2.8 0.15 0.2 2.5 DISABLE = 0 V Rev. B | Page 6 of 28 −30 0.2 −11 3 −0.02 108 +500 −4 +0.6 μV μV/°C μA nA/°C μA dB 10 10 MΩ kΩ 3 11 0.1 to 2.1 −124 pF pF V dB 83 ns 2.97 2.92 0.01 0.05 60 120 39 V V V V mA mA pF 3 to 10 2.7 0.035 2.9 0.15 V mA mA Data Sheet Parameter Power Supply Rejection Ratio (PSRR) Positive Negative DISABLE PIN (ADA4897-1/ADA4897-2) DISABLE Voltage Input Current Enabled Disabled Switching Speed Enabled Disabled ADA4896-2/ADA4897-1/ADA4897-2 Test Conditions/Comments Min Typ +VS = 2.7 V to 3.7 V, −VS = 0 V +VS = 3 V, −VS = −0.3 V to +0.7 V −96 −96 −121 −120 dB dB Enabled Disabled >+VS − 0.5 <−VS + 2 V V DISABLE = +3 V DISABLE = 0 V −1.2 −15 μA μA 0.25 12 μs μs Rev. B | Page 7 of 28 Max Unit ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 6. Rating 11 V See Figure 3 −VS − 0.7 V to +VS + 0.7 V 0.7 V −65°C to +125°C −40°C to +125°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for surfacemount packages. Table 7 lists the θJA for the ADA4896-2/ ADA4897-1/ADA4897-2. VOUT 2 RL RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. VS / 4 2 PD VS I S RL In single-supply operation with RL referenced to −VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduces θJA. 3.5 MAXIMUM POWER DISSIPATION (W) θJA 222 61 133 150 210 V V PD VS I S S OUT RL 2 Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature on a JEDEC standard 4-layer board. θJA values are approximations. Table 7. Thermal Resistance Package Type 8-Lead Dual MSOP (ADA4896-2) 8-Lead Dual LFCSP (ADA4896-2) 8-Lead Single SOIC (ADA4897-1) 6-Lead Single SOT-23 (ADA4897-1) 10-Lead Dual MSOP (ADA4897-2) PD = Quiescent Power + (Total Drive Power − Load Power) Unit °C/W °C/W °C/W °C/W °C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4896-2/ ADA4897-1/ADA4897-2 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4896-2/ADA4897-1/ADA4897-2. Exceeding a junction temperature of 175C for an extended period of time can result in changes in silicon devices, potentially causing degradation or loss of functionality. TJ = 150°C 3.0 2.5 2.0 1.5 8-LEAD LFCSP 6-LEAD SOT-23 10-LEAD MSOP 8-LEAD SOIC 1.0 0.5 8-LEAD MSOP 0 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125 AMBIENT TEMPERATURE (°C) 09447-053 Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature The quiescent power dissipation is the voltage between the supply pins (±VS) multiplied by the quiescent current (IS). Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4896-2/ADA4897-1/ADA4897-2 drive at the output. Rev. B | Page 8 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADA4896-2 OUT1 1 8 +VS 6 –IN2 OUT1 1 8 +VS –VS 4 5 +IN2 –IN1 2 7 OUT2 +IN1 3 6 –IN2 –VS 5 +IN2 NOTES 1. THE EXPOSED PAD CAN BE CONNECTED TO GND OR POWER PLANES, OR IT CAN BE LEFT FLOATING. 09447-022 7 OUT2 +IN1 3 4 TOP VIEW (Not to Scale) Figure 4. 8-Lead LFCSP Pin Configuration 09447-002 ADA4896-2 –IN1 2 Figure 5. 8-Lead MSOP Pin Configuration Table 8. ADA4896-2 Pin Function Descriptions Description Output 1. Inverting Input 1. Noninverting Input 1. Negative Supply. Noninverting Input 2. Inverting Input 2. Output 2. Positive Supply. Exposed Pad (LFCSP Only). The exposed pad can be connected to GND or power planes, or it can be left floating. NC 1 8 DISABLE –IN 2 7 +VS 6 OUT 5 NC +IN 3 –VS 4 ADA4897-1 NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Mnemonic NC −IN +IN −VS OUT +VS DISABLE +VS –VS 2 5 DISABLE 4 –IN ADA4897-1 Figure 7. 6-Lead SOT-23 Pin Configuration Table 9. ADA4897-1 Pin Function Descriptions Pin No. SOT-23 N/A 4 3 2 1 6 5 6 +IN 3 Figure 6. 8-Lead SOIC Pin Configuration SOIC 1, 5 2 3 4 6 7 8 OUT 1 09447-017 Mnemonic OUT1 −IN1 +IN1 −VS +IN2 −IN2 OUT2 +VS EPAD 09447-016 Pin No. 1 2 3 4 5 6 7 8 Description No Connect. Do not connect to these pins. Inverting Input. Noninverting Input. Negative Supply. Output. Positive Supply. Disable. Rev. B | Page 9 of 28 Data Sheet OUT1 1 10 +VS –IN1 2 9 OUT2 +IN1 3 8 –IN2 –VS 4 7 +IN2 6 DISABLE2 DISABLE1 5 ADA4897-2 09447-069 ADA4896-2/ADA4897-1/ADA4897-2 Figure 8. 10-Lead MSOP Pin Configuration Table 10. ADA4897-2 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic OUT1 −IN1 +IN1 −VS DISABLE1 DISABLE2 +IN2 −IN2 OUT2 +VS Description Output 1. Inverting Input 1. Noninverting Input 1. Negative Supply. Disable 1. Disable 2. Noninverting Input 2. Inverting Input 2. Output 2. Positive Supply. Rev. B | Page 10 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 TYPICAL PERFORMANCE CHARACTERISTICS RL = 1 kΩ, unless otherwise noted. When G = +1, RF = 0 Ω; otherwise, RF = 249 Ω. 2 G = –1 OR G = +2 –1 G = +10 –2 –3 –4 –5 –6 0.1 1 10 100 300 FREQUENCY (MHz) NORMALIZED CLOSED-LOOP GAIN (dB) VS = ±5V –1 –2 –3 –4 –5 0.1 1 10 100 2V p-p –3 –4 0.1 500 FREQUENCY (MHz) 0.4 RF = RG = 49.9Ω 0.3 0.2 0.1 0 –0.1 –0.2 NORMALIZED CLOSED-LOOP GAIN (dB) +25°C –3 –4 1G FREQUENCY (Hz) 09447-038 NORMALIZED CLOSED-LOOP GAIN (dB) –2 100M 1 10 50 100 FREQUENCY (MHz) 2 10M RF = RG = 100Ω 0.5 –40°C +125°C 1M 500 Figure 13. 0.1 dB Bandwidth at Selected RF Values 0 –5 100k 100 RF = RG = 249Ω –0.3 0.1 2 –1 10 VS = +5V 0.7 VOUT = 2V p-p G = +2 0.6 RL = 1kΩ Figure 10. Small Signal Frequency Response vs. Supply Voltage VS = +5V G = +1 1 VOUT = 20mV p-p 1 0.8 1 0 400mV p-p –2 Figure 12. Frequency Response for Various Output Voltages VS = +3V VS = +5V 100mV p-p –1 FREQUENCY (MHz) 09447-005 NORMALIZED CLOSED-LOOP GAIN (dB) G = +1 VOUT = 20mV p-p 20mV p-p 0 –5 Figure 9. Small Signal Frequency Response vs. Gain 2 1 09447-061 0 VS = ±5V G = +1 09447-008 G = +1 NORMALIZED CLOSED-LOOP GAIN (dB) 1 09447-006 VS = +5V VOUT = 20mV p-p 09447-010 NORMALIZED CLOSED-LOOP GAIN (dB) 2 Figure 11. Small Signal Frequency Response vs. Temperature 1 VS = +5V VOUT = 2V p-p G = –1 G = +1 0 –1 G = +10 –2 –3 –4 –5 –6 0.1 1 10 FREQUENCY (MHz) Figure 14. Large Signal Frequency Response vs. Gain Rev. B | Page 11 of 28 ADA4896-2/ADA4897-1/ADA4897-2 CL = 39pF –40 RL = 100Ω, SECOND –50 DISTORTION (dBc) 1 CL = 20pF –70 –1 –90 –100 –3 0.1 1 10 100 FREQUENCY (MHz) DISTORTION (dBc) RL = 100Ω, THIRD RL = 1kΩ, THIRD –70 –80 –100 –110 –110 RL = 1kΩ, SECOND 1 FREQUENCY (MHz) 5 Figure 16. Harmonic Distortion vs. Frequency, G = +1 –50 VS = +5V VOUT = 2V p-p G = +5 8V p-p, THIRD 8V p-p, SECOND –90 –100 –50 –60 RL = 100Ω, SECOND G = +2 RL = 1kΩ VS = +5V, SECOND VS = +5V, THIRD –70 DISTORTION (dBc) –70 –80 RL = 100Ω, THIRD –90 –80 –90 –100 –120 09447-041 5 VS = ±5V, SECOND –100 RL = 1kΩ, SECOND FREQUENCY (MHz) VS = +3V, SECOND VS = ±5V, THIRD –110 RL = 1kΩ, THIRD 1 5 1 FREQUENCY (MHz) Figure 19. Harmonic Distortion vs. Frequency for Various Output Voltages –60 –110 0.1 2V p-p, SECOND 2V p-p, THIRD 4V p-p, SECOND 4V p-p, THIRD –120 0.1 09447-021 DISTORTION (dBc) –80 –40 VS = ±5V G = +1 RL = 1kΩ –60 RL = 100Ω, SECOND –120 0.1 5 Figure 18. Harmonic Distortion vs. Frequency, G = +10 –50 –70 1 FREQUENCY (MHz) VS = +5V VOUT = 2V p-p G = +1 –90 RL = 1kΩ, SECOND –110 0.1 Figure 15. Small Signal Frequency Response vs. Capacitive Load DISTORTION (dBc) RL = 1kΩ, THIRD CL = 0pF –2 –60 RL = 100Ω, THIRD –80 09447-026 0 –60 09447-070 2 –50 VS = +5V VOUT = 2V p-p G = +10 –130 0.1 VS = +3V, THIRD 1 5 FREQUENCY (MHz) Figure 20. Harmonic Distortion vs. Frequency for Various Supplies Figure 17. Harmonic Distortion vs. Frequency, G = +5 Rev. B | Page 12 of 28 09447-045 3 –30 VS = +5V G = +2 RL = 100Ω VOUT = 20mV p-p 09447-007 NORMALIZED CLOSED-LOOP GAIN (dB) 4 Data Sheet Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 VS = ±5V 100 UNITS 16 σ = 309.2µV/°C –100 GAIN 50 PHASE –140 40 –160 30 –180 20 10 –200 0 14 NUMBER OF PARTS –120 60 OPEN-LOOP PHASE (Degrees) 70 100k 1M 10M –240 1G 100M 8 6 2 0 –600 09447-044 –20 10k 10 4 –220 –10 12 FREQUENCY (Hz) 0 200 400 600 800 1000 Figure 24. Input Offset Voltage Drift Distribution VS = +3V VS = +5V VS = ±5V 7 G = +1 VOUT = 20mV p-p TIME = 100ns/DIV 10 6 OUTPUT VOLTAGE (mV) VOLTAGE NOISE (nV/√Hz) –200 OFFSET VOLTAGE DRIFT DISTRIBUTION (nV/°C) Figure 21. Open-Loop Gain and Phase vs. Frequency 8 –400 09447-066 80 OPEN-LOOP GAIN (dB) 18 –80 90 5 4 3 2 VS = ±5V 0 09447-050 –10 0 1 10 100 1k 10k 100k 1M 5M FREQUENCY (Hz) 09447-027 1 Figure 22. Voltage Noise vs. Frequency 100 Figure 25. Small Signal Transient Response for Various Supplies, G = +1 VS = +3V VS = ±5V VS = +5V OUTPUT VOLTAGE (mV) 10 VS = ±5V 0 1 09447-040 –10 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 23. Current Noise vs. Frequency 1M 5M 09447-060 CURRENT NOISE (pA/√Hz) 10 G = +2 VOUT = 20mV p-p TIME = 100ns/DIV Figure 26. Small Signal Transient Response for Various Supplies, G = +2 Rev. B | Page 13 of 28 ADA4896-2/ADA4897-1/ADA4897-2 3 0 –10 2 VOUT 1 0 –1 –2 –3 1.5 VS = ±5V VOUT = 2V p-p TIME = 100ns/DIV G = +2 G = +1 0.5 0 –0.5 09447-009 –1.0 –1.5 250 VS = +5V G = +2 200 150 100 50 0 0 100 200 300 400 500 600 700 800 900 OVERLOAD DURATION (ns) Figure 28. Large Signal Transient Response, G = +1 and G = +2 4 VIN 105.0 VS = +5V G = +1 TIME = 100ns/DIV VOUT = 3V p-p VS = +5V G = +2 102.5 RISING EDGE 100.0 1 SLEW RATE (V/µs) 2 VOUT 0 –1 –2 97.5 95.0 FALLING EDGE 92.5 90.0 87.5 85.0 –3 09447-049 INPUT AND OUTPUT VOLTAGE (V) 3 Figure 31. Average Output Overload Recovery Time vs. Overload Duration –4 82.5 80.0 –40 –25 –10 5 20 35 50 65 80 95 TEMPERATURE (°C) Figure 29. Input Overdrive Recovery Time Figure 32. Slew Rate vs. Temperature Rev. B | Page 14 of 28 110 125 09447-052 OUTPUT VOLTAGE (V) 1.0 Figure 30. Output Overdrive Recovery Time AVERAGE OUTPUT OVERLOAD RECOVERY TIME (ns) Figure 27. Small Signal Transient Response for Various Capacitive Loads 09447-055 10 VS = +5V G = +2 TIME = 100ns/DIV 2× VIN 09447-051 INPUT AND OUTPUT VOLTAGE (V) VS = ±5V G = +2 TIME = 100ns/DIV 09447-039 OUTPUT VOLTAGE (mV) CL = 39pF CL = 20pF CL = 0pF Data Sheet Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 0.3 VS = +5V G = +1 PIN = –30dBm 10000 OUTPUT IMPEDANCE (Ω) 0.2 0.1 0 –0.1 –0.2 PART DISABLED 1000 100 10 PART ENABLED 1 09447-028 0.1 –0.3 0.01 0.1 1 10 100 500 FREQUENCY (MHz) Figure 33. Settling Time to 0.1% –20 –30 Figure 36. Output Impedance vs. Frequency –26.0 VS = +5V ΔVCM = 2V p-p INPUT OFFSET VOLTAGE (µV) –40 –50 –60 CMRR (dB) 09447-013 SETTLING TIME (%) 100000 VS = +5V G = +2 VOUT = 2V STEP RL = 1kΩ TIME = 10ns/DIV –70 –80 –90 –100 –110 VS = ±5V –28.5 VS = +5V VS = +3V –31.0 10k 100k 1M 10M 100M FREQUENCY (Hz) –33.5 –40 09447-029 –130 1k 0 –20 20 35 50 65 80 95 110 125 –10.50 VS = ±5V INPUT BIAS CURRENT (µA) –30 –40 –PSRR –60 –70 +PSRR –80 –90 –100 –10.75 VS = +5V –11.00 VS = +3V –11.25 –110 –130 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 35. PSRR vs. Frequency –11.50 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 38. Input Bias Current vs. Temperature for Various Supplies Rev. B | Page 15 of 28 09447-046 –120 09447-030 PSRR (dB) 5 Figure 37. Input Offset Voltage vs. Temperature for Various Supplies VS = +5V ΔVS = 2V p-p G = +1 –50 –10 TEMPERATURE (°C) Figure 34. CMRR vs. Frequency –10 –25 09447-042 –120 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet VS = ±5V 3.1 SUPPLY CURRENT (mA) 5.0 4.5 2.9 2.8 2.7 3.5 DISABLE PIN (V) VS = +5V VS = +3V –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 09447-043 –25 Figure 39. Supply Current vs. Temperature for Various Supplies 3.750 3.625 3.375 –40°C 3.0 3.250 2.5 3.125 2.0 3.000 1.5 2.875 2.750 +125°C 0.5 2.5 –40 3.875 3.500 1.0 2.6 –50 +25°C 4.0 3.0 –40 TIME = 2µs/DIV VS = +5V G = +1 VIN = 1V DISABLE PIN OUTPUT VOLTAGE (V) 5.5 2.625 0 2.500 –0.5 2.375 09447-056 3.2 Figure 42. Turn-Off Time vs. Temperature (ADA4897-1 and ADA4897-2) –30 VS = +5V G = +2 VOUT = 2V p-p –40 –50 –60 VS = +5V G = +2 RL = 100Ω VOUT = 2V p-p ISOLATION (dB) CROSSTALK (dB) –60 –70 –80 –90 –100 –70 –80 –90 –100 –110 –110 –120 –120 0.1 1 10 100 FREQUENCY (MHz) –140 0.01 3.500 3.5 3.0 2.5 +25°C –40°C 3.250 3.125 2.875 1.5 0.5 3.375 3.000 2.0 1.0 +125°C TIME = 200ns/DIV VS = +5V G = +1 VIN = 1V 2.750 OUTPUT VOLTAGE (V) 3.625 4.0 2.625 0 2.500 –0.5 2.375 09447-054 DISABLE PIN (V) 3.750 4.5 10 Figure 43. Forward Isolation vs. Frequency 3.875 DISABLE PIN 5.0 1 FREQUENCY (MHz) Figure 40. Crosstalk, OUT1 to OUT2 (ADA4896-2 and ADA4897-2) 5.5 0.1 Figure 41. Turn-On Time vs. Temperature (ADA4897-1 and ADA4897-2) Rev. B | Page 16 of 28 100 09447-015 –130 09447-014 –130 0.01 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 THEORY OF OPERATION AMPLIFIER DESCRIPTION The ADA4896-2/ADA4897-1/ADA4897-2 are 1 nV/√Hz input noise amplifiers that consume 3 mA from supplies ranging from 3 V to 10 V. Fabricated on the Analog Devices SiGe bipolar process, the ADA4896-2/ADA4897-1/ADA4897-2 have a bandwidth in excess of 200 MHz. The amplifiers are unity-gain stable, and the input structure results in an extremely low input 1/f noise for a high speed amplifier. The rail-to-rail output stage is designed to drive the heavy feedback load required to achieve an overall low output referred noise. To meet more demanding system requirements, the large signal bandwidth of the ADA4896-2/ADA4897-1/ADA4897-2 was increased beyond the typical fundamental limits of other low noise, unity-gain stable amplifiers. The maximum offset voltage of 500 μV and drift of 0.2 μV/°C make the ADA4896-2/ADA4897-1/ ADA4897-2 excellent amplifier choices even when the low noise performance is not needed because there is minimal power penalty in achieving the low input noise or the high bandwidth. The ESD clamps begin to conduct for input voltages that are more than 0.7 V above the positive supply and input voltages more than 0.7 V below the negative supply. If an overvoltage condition is expected, it is recommended that the input current be limited to less than 10 mA. DISABLE OPERATION Figure 45 shows the ADA4897-1/ADA4897-2 power-down circuitry. If the DISABLE pin is left unconnected, the base of the input PNP transistor is pulled high through the internal pull-up resistor to the positive supply and the part is turned on. Pulling the DISABLE pin to ≥2 V below the positive supply turns the part off, reducing the supply current to approximately 18 μA for a 5 V voltage supply. +VS IBIAS ESD DISABLE ESD INPUT PROTECTION The ADA4896-2/ADA4897-1/ADA4897-2 are fully protected from ESD events, withstanding human body model ESD events of 2.5 kV and charged-device model events of 1 kV with no measured performance degradation. The precision input is protected with an ESD network between the power supplies and diode clamps across the input device pair, as shown in Figure 44. BIAS ESD ESD ESD –IN ESD 09447-068 –VS TO THE REST OF THE AMPLIFIER –VS Figure 45. DISABLE Circuit The DISABLE pin is protected by ESD clamps, as shown in Figure 45. Voltages beyond the power supplies cause these diodes to conduct. For protection of the DISABLE pin, the voltage to this pin should not exceed 0.7 V above the positive supply or 0.7 V below the negative supply. If an overvoltage condition is expected, it is recommended that the input current be limited with a series resistor to less than 10 mA. +VS +IN 09447-037 TO AMPLIFIER BIAS Figure 44. Input Stage and Protection Diodes For differential voltages above approximately 0.7 V, the diode clamps begin to conduct. Too much current can cause damage due to excessive heating. If large differential voltages must be sustained across the input terminals, it is recommended that the current through the input clamps be limited to less than 10 mA. Series input resistors that are sized appropriately for the expected differential overvoltage provide the needed protection. When the amplifier is disabled, its output goes to a high impedance state. The output impedance decreases as frequency increases; this effect can be observed in Figure 36. In disable mode, a forward isolation of 50 dB can be achieved at 10 MHz. Figure 43 shows the forward isolation vs. frequency data. Rev. B | Page 17 of 28 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet DC ERRORS The output error due to the input currents can be estimated as Figure 46 shows a typical connection diagram and the major dc error sources. ⎛ ⎛ R ⎞ R ⎞ VOUTERROR = (R F || RG ) × ⎜⎜1 + F ⎟⎟ × I B − − R S × ⎜⎜ 1 + F ⎟⎟ × I B + (5) RG ⎠ ⎝ RG ⎠ ⎝ RF – VIN + BIAS CURRENT CANCELLATION + VOS – RG RG RS RF 09447-031 – VIP + To cancel the output voltage error due to unmatched bias currents at the inputs, RBP and RBN can be used (see Figure 47). + VOUT – IB– IB+ Figure 46. Typical Connection Diagram and DC Error Sources ⎛ ⎛R R ⎞ VOUT = ⎜⎜1 + F ⎟⎟ × V IP − ⎜⎜ F R G ⎠ ⎝ ⎝ RG RS ⎞ ⎟ × V IN ⎟ ⎠ (1) Figure 47. Using RBP and RBN to Cancel Bias Current Error Table 11. Setting RBN and RBP to Cancel Bias Current Errors For noninverting gain (VIN = 0 V) ⎛ R ⎞ = ⎜⎜ 1 + F ⎟⎟ × V IP R G ⎠ ⎝ (2) For inverting gain (VIP = 0 V) ⎛ − RF VOUT = ⎜⎜ ⎝ RG RBP To compensate for the unmatched bias currents at the two inputs, set RBP and RBN as shown in Table 11. This equation reduces to the familiar forms for noninverting and inverting op amp gain expressions, as follows: VOUT 09447-048 RBN The ideal transfer function (all error sources set to 0 and infinite dc gain) can be written as Value of RF||RG Greater Than RS Less Than RS Value of RBP (Ω) RF||RG − RS 0 Value of RBN (Ω) 0 RS − RF||RG Table 12 shows sample values for RBP and RBN when RF||RG > RS and when RF||RG < RS. ⎞ ⎟ × VIN ⎟ ⎠ (3) Table 12. Examples of RBN and RBP Settings Gain +2 +10 The total output voltage error is the sum of errors due to the amplifier offset voltage and input currents. The output error due to the offset voltage can be estimated as VOUTERROR = V VCM V − V PNOM R ⎞ ⎛ ⎞ ⎛ + P + OUT ⎟ × ⎜⎜ 1 + F ⎟⎟ ⎜ VOFFSET NOM + CMRR PSRR A R ⎝ ⎠ ⎝ G ⎠ (4) where: VOFFSETNOM is the offset voltage at the specified supply voltage, which is measured with the input and output at midsupply. VCM is the common-mode voltage. VP is the power supply voltage. VPNOM is the specified power supply voltage. CMRR is the common-mode rejection ratio. PSRR is the power supply rejection ratio. A is the dc open-loop gain. Rev. B | Page 18 of 28 RF (Ω) 249 249 RG (Ω) 249 27.4 RS (Ω) 50 50 RBP (Ω) 74.5 0 RBN (Ω) 0 25.3 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 500 NOISE CONSIDERATIONS RF vn _ RF = 4kT × RF ven RG vn _ RG = 4kT × RG NOISE (nV/√Hz) Figure 48 illustrates the primary noise contributors for the typical gain configurations. The total rms output noise is the root-mean-square of all the contributions. + vout_en – ien 50 AMPLIFIER AND RESISTOR NOISE 5 SOURCE RESISTANCE NOISE iep TOTAL AMPLIFIER NOISE Figure 48. Noise Sources in Typical Connection 0.5 50 50k SOURCE RESISTANCE (Ω) Figure 49. RTI Noise vs. Source Resistance vout _ en = [ ] 2 (6) where: k is Boltzmann’s constant. T is the absolute temperature (degrees Kelvin). iep and ien represent the amplifier input current noise spectral density (pA/√Hz). ven is the amplifier input voltage noise spectral density (nV/√Hz). RS is the source resistance, as shown in Figure 48. RF and RG are the feedback network resistances, as shown in Figure 48. Source resistance noise, amplifier voltage noise (ven), and the voltage noise from the amplifier current noise (iep × RS) are all subject to the noise gain term (1 + RF/RG). Note that with a 1 nV/√Hz input voltage noise and 2.8 pA/√Hz input current noise, the noise contributions of the amplifier are relatively small for source resistances from approximately 50 Ω to 700 Ω. Figure 49 shows the total RTI noise due to the amplifier vs. the source resistance. In addition, the value of the feedback resistors used affects the noise. It is recommended that the value of the feedback resistors be maintained between 250 Ω and 1 kΩ to keep the total noise low. CAPACITANCE DRIVE Capacitance at the output of an amplifier creates a delay within the feedback path that, if within the bandwidth of the loop, can create excessive ringing and oscillation. The ADA4896-2/ADA4897-1/ ADA4897-2 show the most peaking at a gain of +2 (see Figure 9). Placing a small snub resistor (RSNUB) in series with the amplifier output and the capacitive load mitigates the problem. Figure 50 shows the effect of using a snub resistor (RSNUB) on reducing the peaking for the worst-case frequency response (gain of +2). Using RSNUB = 100 Ω eliminates the peaking entirely, with the trade-off that the closed-loop gain is reduced by 0.8 dB due to attenuation at the output. RSNUB can be adjusted from 0 Ω to 100 Ω to maintain an acceptable level of peaking and closedloop gain (see Figure 50). 3 VS = +5V VOUT = 200mV p-p 2 G = +2 RSNUB = 0Ω 1 RSNUB = 50Ω RSNUB = 100Ω 0 –1 R2 249Ω –2 R1 249Ω –3 –4 ADA4896-2 VIN –5 0.1 RSNUB VOUT RL 1kΩ 1 CL 39pF 10 FREQUENCY (MHz) Figure 50. Using a Snub Resistor to Reduce Peaking Due to Output Capacitive Load Rev. B | Page 19 of 28 100 09447-058 2 2 2 ⎞ ⎛R ⎞ ⎟⎟ 4kTRs + iep RS 2 + ven + ⎜⎜ F ⎟⎟ 4kTRG + ien 2 RF 2 ⎠ ⎝ RG ⎠ NORMALIZED CLOSED-LOOP GAIN (dB) ⎛ R 4kTRF + ⎜⎜1 + F ⎝ RG 5k 500 The output noise spectral density can be calculated by 09447-057 vn _ RS = 4kT × RS 09447-034 RS ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet APPLICATIONS INFORMATION 2 Note that as the gain increases, the small signal bandwidth decreases, as is expected from the gain bandwidth product relationship. In addition, the phase margin improves with higher gains, and the amplifier becomes more stable. As a result, the peaking in the frequency response is reduced (see Figure 51). VS = +5V VOUT = 200mV p-p 1 RF = 249Ω RL = 1kΩ G = +5 G = +2 0 –1 G = +10 G = +1 –2 G = +20 –3 –4 –5 –6 0.1 1 10 100 500 FREQUENCY (MHz) 09447-020 To reduce design time and eliminate uncertainty, Table 13 provides a reference for typical gains, component values, and performance parameters. The supply voltage used is 5 V. The bandwidth is obtained with a small signal output of 200 mV p-p, and the slew rate is obtained with a 2 V output step. NORMALIZED CLOSED-LOOP GAIN (dB) TYPICAL PERFORMANCE VALUES Figure 51. Small Signal Frequency Response at Various Gains Table 13. Recommended Values and Typical Performance Gain +1 +2 +5 +10 +20 RF (Ω) 0 249 249 249 249 RG (Ω) N/A 249 61.9 27.4 13.0 −3 dB BW (MHz) 92 54 30 17 9 Slew Rate, tR/tF (V/μs) 78/158 101/140 119/137 87/88 37/37 Rev. B | Page 20 of 28 Peaking (dB) 0.8 1.2 0 0 0 Total Output Noise Including Resistors (nV/√Hz) 1.0 3.6 6.8 12.0 21.1 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 LOW NOISE, GAIN SELECTABLE AMPLIFIER USING S3B IS OPTIONAL RF2 225Ω S3B RF1 75Ω +5V 6 +5V 2 8 S1B ADA4896-2 VIN 3 1 V01 D1 S1A V2 4 7 ADA4896-2 S2B V1 8 V02 D2 5 RL 4 RBALANCE S2A 150Ω –5V 09447-100 RG1 75Ω ADG633 D3 ADG633 –5V Figure 52. Using the ADA4896-2 and the ADG633 to Construct a Low Noise, Gain Selectable Amplifier to Drive a Low Resistive Load In the circuit shown in Figure 52, the switches are implemented with the ADG633 and are configured such that either S1A and S2A are on, or S1B and S2B are on. In this example, when the S1A and S2A switches are on, the first stage amplifier gain is +4. When the S1B and S2B switches are on, the first stage amplifier gain is +2. The first set of switches of the ADG633 is placed on the output side of the feedback loop, and the second set of switches is used to sample at a point (V1 or V2) where switch resistances and nonlinear resistances do not matter. In this way, the gain error can be reduced while preserving the noise performance of the ADA4896-2. Note that the input bias current of the output buffer can cause problems with the impedance of the S2A and S2B sampling switches. Both sampling switches are not only nonlinear with voltage but with temperature as well. If this is an issue, place the unused switch of the ADG633 (S3B) in the feedback path of the output buffer to balance the bias currents (see Figure 52). The following derivation shows that sampling at V1 yields the desired signal gain without gain error. RS denotes the switch resistance. V2 can be derived using the same method. ⎛ R + RS1 ⎞ ⎟ V01 = VIN × ⎜⎜1 + F1 RG1 ⎟⎠ ⎝ ⎛ R F1 + R G1 V1 = V 01 × ⎜⎜ ⎝ R F1 + R G1 + R S1 (7) ⎞ ⎟ ⎟ ⎠ (8) Substituting Equation 1 into Equation 2, the following derivation is obtained. ⎛ R ⎞ V1 = VIN × ⎜⎜1 + F1 ⎟⎟ RG1 ⎠ ⎝ (9) Note that if V01 yields the desired signal gain without gain error, the buffered output V02 will also be free from gain error. Figure 53 shows the normalized frequency response of the circuit at V02. 6 In addition, the bias current of the input amplifier causes an offset at the output that varies based on the gain setting. Because the input amplifier and the output buffer are monolithic, the relative matching of their bias currents can be used Rev. B | Page 21 of 28 VS = ±5V 3 VIN = 100mV p-p RL = 1kΩ 0 –3 G = +4 –6 G = +2 –9 –12 –15 –18 –21 –24 –27 –30 0.1 1 10 100 FREQUENCY (MHz) Figure 53. Frequency Response of V02/VIN 500 09447-064 Figure 52 presents an innovative switching technique used in the gain selectable amplifier such that the 1 nV/Hz noise performance of the ADA4896-2 is preserved while the nonlinear gain error is much reduced. With this technique, the user can also choose switches with minimal capacitance to optimize the bandwidth of the circuit. to cancel out the varying offset. Placing a resistor equal to the difference between RF2 and RF1 in series with Switch S2A results in a more constant offset voltage. NORMALIZED CLOSED-LOOP GAIN (dB) A gain selectable amplifier makes processing a wide range of input signals possible. A traditional gain selectable amplifier uses switches in the feedback loops connecting to the inverting input. The switch resistances degrade the noise performance of the amplifier, as well as adding significant capacitance on the inverting input node. The noise and capacitance issues can be especially bothersome when working with low noise amplifiers. Also, the switch resistances contribute to nonlinear gain error, which is undesirable. ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet MEDICAL ULTRASOUND APPLICATIONS BEAMFORMER CENTRAL CONTROL Tx BEAMFORMER AD9279 HV MUX/ DEMUX T/R SWITCHES LNA ADC VGA AAF Rx BEAMFORMER (B AND F MODES) TRANSDUCER ARRAY SPECTRAL DOPPLER PROCESSING MODE ADA4896-2/ ADA4897-1/ ADA4897-2 AUDIO OUTPUT IMAGE AND MOTION PROCESSING (B MODE) COLOR DOPPLER PROCESSING (F MODE) DISPLAY 09447-033 CW (ANALOG) BEAMFORMER Figure 54. Simplified Ultrasound System Block Diagram Overview of the Ultrasound System Medical ultrasound systems are among the most sophisticated signal processing systems in widespread use today. By transmitting acoustic energy into the body and receiving and processing the returning reflections, ultrasound systems can generate images of internal organs and structures, map blood flow and tissue motion, and provide highly accurate blood velocity information. Figure 54 shows a simplified block diagram of an ultrasound system. The ultrasound system consists of two main operations: the time gain control (TGC) operation and the continuous wave (CW) Doppler operation. The AD9279 integrates the essential components of these two operations into a single IC. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA), an antialiasing filter (AAF), an analog-to-digital converter (ADC), and an I/Q demodulator with programmable phase rotation. For detailed information about how to use the AD9279 in an ultrasound system, see the AD9279 data sheet. Rev. B | Page 22 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 ADA4896-2/ADA4897-1/ADA4897-2 in the Ultrasound System RFILT CWI+ Φ CHANNEL A RA CFILT AD7982 50Ω 1.5V LNA 1.5V Φ ADA4896-2/ 2.5V ADA4897-1/ ADA4897-2 2.5V CWI– ADA4896-2/ ADA4897-1/ ADA4897-2 50Ω RA CFILT 18-BIT ADC I 4nF RFILT RFILT CWQ+ RA CFILT AD7982 50Ω Φ CHANNEL H 1.5V 1.5V LNA ADA4896-2/ 2.5V ADA4897-1/ ADA4897-2 2.5V CWQ– 50Ω RA Φ ADA4896-2/ ADA4897-1/ ADA4897-2 CFILT 18-BIT ADC Q 4nF RFILT 4 LO GENERATION 09447-032 4LO– 4LO+ RESET AD9279 Figure 55. Using the ADA4896-2/ADA4897-1/ADA4897-2 as Filters, I-to-V Converters, Current Summers, and ADC Drivers After the I/Q Outputs of the AD9279 The ADA4896-2/ADA4897-1/ADA4897-2 are used in the CW Doppler path in the ultrasound application after the I/Q demodulators of the AD9279. Doppler signals can be typically between 100 Hz to 100 kHz. The low noise floor and high dynamic range of the ADA4896-2/ADA4897-1/ADA4897-2 make them excellent choices for processing weak Doppler signals. The rail-to-rail output and the high output current drive of the ADA4896-2/ADA4897-1/ADA4897-2 make them suitable candidates for the I-to-V converter, current summer, and ADC driver. Figure 55 shows an interconnection block diagram of all eight channels of the AD9279. Two stages of the ADA4896-2 amplifiers are used. The first stage performs an I-to-V conversion and filters the high frequency content that results from the demodulation process. The second stage of the ADA4896-2 amplifiers is used to sum the output currents of multiple AD9279 devices, to provide gain, and to drive the AD7982 device, an 18-bit SAR ADC. The output-referred noise of the CW signal path depends on the LNA gain, the selection of the first stage summing amplifier, and the value of RFILT. To determine the output-referred noise, it is important to know the active low-pass filter (LPF) values RA, RFILT, and CFILT, as shown as Figure 55. Typical filter values for all eight channels of a single AD9279 are 100 Ω for RA, 500 Ω for RFILT, and 2.0 nF for CFILT; these values implement a 100 kHz, single-pole LPF. The gain of the I-to-V converter can be increased by increasing the filter resistor, RFILT. To keep the corner frequency unchanged, decrease the filter capacitor, CFILT, by the same factor. The factor limiting the magnitude of the gain is the output swing and drive capability of the op amp selected for the I-to-V converter, in this example, the ADA4896-2/ADA4897-1/ADA4897-2. Because any amplifier has limited drive capability, a finite number of channels can be summed. Rev. B | Page 23 of 28 ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet LAYOUT CONSIDERATIONS To ensure optimal performance, careful and deliberate attention must be paid to the board layout, signal routing, power supply bypassing, and grounding. Ground Plane It is important to avoid ground in the areas under and around the input and output of the ADA4896-2/ADA4897-1/ADA4897-2. Stray capacitance created between the ground plane and the input and output pads of a device is detrimental to high speed amplifier performance. Stray capacitance at the inverting input, along with the amplifier input capacitance, lowers the phase margin and can cause instability. Stray capacitance at the output creates a pole in the feedback loop, which can reduce phase margin and can cause the circuit to become unstable. Power Supply Bypassing Power supply bypassing is a critical aspect in the performance of the ADA4896-2/ADA4897-1/ADA4897-2. A parallel connection of capacitors from each power supply pin to ground works best. Smaller value capacitor electrolytics offer better high frequency response, whereas larger value capacitor electrolytics offer better low frequency performance. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided with a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier—especially when the amplifier PSRR begins to roll off—because the bypass capacitors can help lessen the degradation in PSRR performance. The smallest value capacitor should be placed on the same side of the board as the amplifier and as close as possible to the amplifier power supply pins. The ground end of the capacitor should be connected directly to the ground plane. It is recommended that a 0.1 μF ceramic capacitor with a 0508 case size be used. The 0508 case size offers low series inductance and excellent high frequency performance. A 10 μF electrolytic capacitor should be placed in parallel with the 0.1 μF capacitor. Depending on the circuit parameters, some enhancement to performance can be realized by adding additional capacitors. Each circuit is different and should be analyzed individually for optimal performance. Rev. B | Page 24 of 28 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 0.80 0.55 0.40 0.23 0.09 6° 0° 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 56. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 2.44 2.34 2.24 3.10 3.00 SQ 2.90 0.50 BSC 8 5 0.50 0.40 0.30 0.80 0.75 0.70 0.30 0.25 0.20 1 4 BOTTOM VIEW TOP VIEW SEATING PLANE 1.70 1.60 1.50 EXPOSED PAD 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED Figure 57. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-11) Dimensions shown in millimeters Rev. B | Page 25 of 28 PIN 1 INDICATOR (R 0.15) 01-24-2011-B PIN 1 INDEX AREA ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet 5.00 (0.1968) 4.80 (0.1890) 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 1.75 (0.0688) 1.35 (0.0532) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 58. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.00 2.90 2.80 1.70 1.60 1.50 6 5 4 1 2 3 PIN 1 INDICATOR 3.00 2.80 2.60 0.95 BSC 1.90 BSC 0.15 MAX 0.05 MIN 1.45 MAX 0.95 MIN 0.50 MAX 0.30 MIN 0.20 MAX 0.08 MIN SEATING PLANE 10° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 59. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters Rev. B | Page 26 of 28 0.60 BSC 0.55 0.45 0.35 12-16-2008-A 1.30 1.15 0.90 Data Sheet ADA4896-2/ADA4897-1/ADA4897-2 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 60. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4896-2ARMZ ADA4896-2ARMZ-R7 ADA4896-2ARMZ-RL ADA4896-2ACPZ-R2 ADA4896-2ACPZ-R7 ADA4896-2ACPZ-RL ADA4896-2ACP-EBZ ADA4896-2ARM-EBZ ADA4897-1ARZ ADA4897-1ARZ-R7 ADA4897-1ARZ-RL ADA4897-1ARJZ-R2 ADA4897-1ARJZ-R7 ADA4897-1ARJZ-RL ADA4897-1AR-EBZ ADA4897-1ARJ-EBZ ADA4897-2ARMZ ADA4897-2ARMZ-R7 ADA4897-2ARMZ-RL ADA4897-2ARM-EBZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD Evaluation Board for the 8-Lead LFCSP Evaluation Board for the 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 Evaluation Board for the 8-Lead SOIC_N Evaluation Board for the 6-Lead SOT-23 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board for the 10-Lead MSOP Z = RoHS Compliant Part. Rev. B | Page 27 of 28 Package Option RM-8 RM-8 RM-8 CP-8-11 CP-8-11 CP-8-11 Ordering Quantity 50 1,000 3,000 250 1,500 5,000 Branding H2P H2P H2P H2P H2P H2P R-8 R-8 R-8 RJ-6 RJ-6 RJ-6 98 1,000 2,500 250 3,000 10,000 H2K H2K H2K RM-10 RM-10 RM-10 50 1,000 3,000 H2N H2N H2N ADA4896-2/ADA4897-1/ADA4897-2 Data Sheet NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09447-0-4/12(B) Rev. B | Page 28 of 28