TI Designs
System on Module for G3 Power Line Communication
(CENELEC Frequency Band)
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Design Resources
TIDM-SOMPLC-G3-CENELEC
TMDSPLCKIT-V4
TMS320F28069
AFE031
TPS62240
TPS3828-33
SN74LVC2G07
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WEBENCH® Calculator Tools
Power
Lines
Small Size: 1.5 × 1.9 in
PRIME and G3 Compatible
F28PLC83 PLC Engine with VCU
CENELEC A Functionality
AFE031 Integrated Analog Front End (AFE)
34-Pin Mini Header for Interfacing Other Designs
Multiple Serial Communications Interfaces
Available, Including UART, SPI, I2C, and CAN
Additional ADC Interface
Additional GPIO Interfaces
EEPROM
Power Line Communication (PLC) Modem
Smart E-Meter: AMR and AMI
Solar Power Inverter
Clock
AFE031
PA
SPI
+
±
HV
Cap
UART
HOST
MCU
Processor
Coupling
Transformer
+
±
Surge
Protector
ADC
PGA
Isolated AC/DC Supply
System
Power
Power Management
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
All trademarks are the property of their respective owners.
TIDU442A – July 2014 – Revised February 2015
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System on Module for G3 Power Line Communication (CENELEC Frequency
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1
SOMPLC Description
1
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SOMPLC Description
The SOMPLC-F28PLC83 is a single-board system on module (SOM) for PLC in the CENELEC frequency
band. This single hardware design supports several popular PLC industry standards including G3. TI's
certified PLC software is available along with the SOMPLC-F28PLC83. Engineers can take the SOM
design and integrate it into their overall system board or keep the design as an add-on board to their
application. The only additional hardware required is the AC mains line coupling circuitry. The included
hardware schematics and Gerber files help engineers add PLC to their end system. Original equipment
manufacturers (OEMs) will benefit from having the ability to rapidly evaluate and prototype PLC
technology in their application.
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System Description
The TMS320F28PLC83 PLC MCU is optimized to meet the requirements for PLC communications
networks in smart grid deployments around the world. The F28PLC83 MCU features the C28x 32-bit CPU
that can execute the narrowband OFDM PLC modem standards, which adhere to key international and
industry standards such as PRIME, G3-PLC, IEEE-1901.2, ITU G.9903, and ITU G.9904 in the CENELEC
frequency bands. The F28PLC83 MCU is optimized to work with the AFE031 PLC analog front end. The
AFE031 is an integrated PLC AFE that is capable of a transformer coupled connected to the AC mains
power line. This AFE is ideal for driving high-current, low-impedance lines driving up to 1.9 A into reactive
loads. The AFE031 is compliant to CENELEC A, B, C, and D (EN50065-1, -2, -3, and -7, respectively).
3
Boot Modes (SW1 Positions)
The boot mode can be selected using the switch SW1. The available settings are described below.
ON
FLASH Boot Mode (Default Setting)
Position 1: OFF
Position 2: OFF
1
2
ON
SCI-A Boot Mode
Position 1: OFF
Position 2: ON
1
2
Figure 1. Boot Modes
2
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UART SCI Communication
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4
UART SCI Communication
In
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order to communicate with the SCI, meet the following requirements:
Baud rate = 57600
Message data bits = 8
Stop bits = 1
Parity = None
Handshake = None
RTS enable = True
NOTE: The SOMPLC does not have a RS-232 driver. Consider communications to RS-232 devices
external to this design.
5
SOMPLC 34-Pin Definition
The interfaces are supported on this module.
Table 1. Required and Optional Connections for Interfaces
REQUIRED CONNECTIONS
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SCI (UART)
Line
15 V
3V3
GND
OPTIONAL CONNECTIONS
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TIDU442A – July 2014 – Revised February 2015
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ADC
GPIOs
SCI (UART)
CAN
SPI
I2C
Zero cross
Analog GND
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3
SOMPLC 34-Pin Definition
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Table 2. 34-Pin Connector Details
4
PIN#
NAME
I/O
ELECTRICAL
1
L1
I/O
0 V (GND)
DESCRIPTION
2
L2
I/O
0V
(±6-V Peak)
3
NC
NC
—
Unused
4
NC
NC
—
Unused
5
GND
—
—
Ground
6
GND
—
—
Ground
7
V15
—
15 to 18 V
8
3V3
—
3.14 to 3.47 V
9
EN
I-I/O
–0.3 V to VCC+0.3 V
System enable (logical level, active high). Controls power up/down
function of the module. When low, the module goes to power down mode.
This feature is not yet implemented in software or GPIO13.
10
ZC
I
–0.5 to 6.5 V
Buffered ZC input. This input must be isolated from the power line before
entering this pin.
11
RX-A
I
–0.3 V to VCC+0.3 V
Asynchronous serial host-transmit, SCI-A
Neutral (analog ground), connected to the PL coupler
Analog PLC signal, connected to the PL coupler
Power supply pin (15 V). Peak current 400 mA in transmit mode (average
100 mA).
CPU and Logic Digital Power pin (3.3 V). Max current 1000 mA.
12
TX-A
O
–0.3 V to VCC+0.3 V
Asynchronous serial host-receive, SCI-A
13
Phase B/GPIO
I-I/O
–0.3 V to VCC+0.3 V
Phase B Enable signal (for 3-phase selection) or GPIO5
14
I/O
–0.3 V to VCC+0.3 V
Phase C enable signal (for 3-phase selection ) or GPIO10
15
I/O
–0.3 V to VCC+0.3 V
I2C data pin
16
I
–0.3 V to VCC+0.3 V
I2C clock pin
17
I
–0.3 V to VCC+0.3 V
Unused ADC input. (ADC-B0)
18
—
—
19
I/O
–0.3 V to VCC+0.3 V
20
—
—
21
I/O
–0.3 V to VCC+0.3 V
Analog ground
Unused multi-purpose I/O, GPIO26
Ground
Unused multi-purpose I/O, GPIO27
22
—
—
23
I-I/O
–0.3 V to VCC+0.3 V
Ground
CAN RX interface or GPIO30
24
O-I/O
–0.3 V to VCC+0.3 V
CAN TX interface or GPIO31
25
I
–0.3 V to VCC+0.3 V
SPI clock or general purpose I/O (GPIO18)
26
I
–0.3 V to VCC+0.3 V
SPI slave transmit enable or general purpose I/O (GPIO19)
27
I
–0.3 V to VCC+0.3 V
SPI slave in, master out or general purpose I/O (GPIO16)
28
O
–0.3 V to VCC+0.3 V
SPI master in, slave out or general purpose I/O (GPIO17).
29
I
–0.3 V to VCC+0.3 V
Reset of SOMPLC (active low)
30
I/O
–0.3 V to VCC+0.3 V
Unused multi-purpose I/O pin, GPIO04.
31
NC
—
Unused
32
NC
—
Unused
33
I
–0.3 V to VCC+0.3 V
Asynchronous serial host-receive, SCI-B
34
O
–0.3 V to VCC+0.3 V
Asynchronous serial host-transmit, SCI-B
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Mechanical Specification
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6
Mechanical Specification
The connectors used on the SOMPLC are as follows:
• A male 0.05-mil header (2 × 17) is placed on the SOMPLC module.
– This connector is keyed so that the module cannot be placed backwards.
– An example part that will fit this design is a Sullins Connector Solutions,
part number: SBH31-NBPB-D17-SP-BK, Digikey part number: S9108-ND
• A female 0.05-mil receptacle (2 × 17) should be used on the host board to mate with the
SOMPLC module.
– This connector is keyed and should follow the appropriate orientation as the male connector.
– An example part that will fit this design is a Sullins Connector Solutions,
part number: SFH31-NPPB-D17-SP-BK, Digikey part Number:S9117-ND
The top view of the female connector, which would be placed on the host board, is shown in Figure 2.
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2
3
4
5
6
7
8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
Figure 2. Pin Female Connector Top View
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PLC SOM Programming
7
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PLC SOM Programming
Depending on the end use of the SOM, different versions of the PLC software may be programmed to the
module. For this design, you can download the G3-PLC software package from Section 11 and check out
the G3-PLC binaries (.hex, .out, and .sbin) under the installation directory.
7.1
Using the XDS100 and CodeSkin to program the F28069 MCU
Programming with this method eliminates the need for CCS to load the release(.out) file. A .hex release
file is used instead and therefore the installation of CCS is not necessary.
1. Install the desired Texas Instruments PLC Development Package from www.ti.com/plc.
2. Download, install, and start the latest C2Prog from www.codeskin.com.
3. Set switch SW1 to FLASH Boot Mode as described in Section 3.
4. Connect a Texas Instruments XDS100-class emulator to the SOM module using the 14-pin JTAG
header.
5. Power up the SOM module by applying both 15 V and 3.3 V through the 34-pin host connector.
6. Program the *.hex (located in c:\Texas Instruments\<PackageName>\SW\bin) as shown in Figure 3.
Select 28069,67,66 in the Target pull-down and JTAG in the Options pull-down.
Figure 3. Selecting G3-PLC Binary to Be Flashed (via XDS100)
6
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PLC SOM Programming
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7. Click on the Configure Ports button and set the JTAG port to XDS100v1.
Figure 4. Selecting JTAG Port (via XDS100)
8. Start flashing the F28069.
Figure 5. Flashing G3-PLC Firmware (via XDS100)
9. Power cycle the device when the programming procedure completes.
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PLC SOM Programming
7.2
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Using CCS and JTAG Emulator to Program the F28069 MCU
If the XDS100 emulator is not available, use Code Composer Studio (CCS) or higher and a XDS510 or
XDS560 emulator to program the device. Install CCS v4.2.4 or higher before following these procedures:
1. Install the desired Texas Instruments PLC Development Package from www.ti.com/plc.
2. Set switch SW1 to FLASH Boot Mode as described in Section 3. When used, a JTAG emulator is
capable of interrupting the set boot mode to gain control of the MCU. When the programming
procedure is complete, set the mode to FLASH Boot Mode for the SOM module to continue to work
properly.
3. Power up the SOM module by applying both 15 V and 3.3 V through the 34-pin host connector.
4. Connect the emulator to the SOM module with the 14-pin JTAG cable.
5. Open CCS.
6. Create a F28069 target configuration.
7. Connect to the F28069 device.
8. Load the PLC specific .out firmware (located in c:\Texas Instruments\<PackageName>\SW\bin). CCS
will automatically flash the firmware onto the F28069 device.
8
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PLC SOM Programming
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7.3
Using a Serial Port (RS-232/SCI) to Program the F28069 MCU
Some user situations may require the SOM module to connect directly to a computer’s serial port using
RS-232 communications. In this scenario, have a host board that is capable of converting the RS-232
communications protocol to work with the F28069 SCI-A port. In most cases, this conversion is performed
by using an external RS-232 driver device such as the MAX3221ECPWR by Texas Instruments. Once in
place, follow these steps:
1. Install the desired Texas Instruments PLC Development Package from www.ti.com/plc
2. Download, install and start the latest C2Prog from www.codeskin.com
3. Make sure the SOM module is not powered on. Set switch SW1 to SCI-A Boot Mode as described in
Section 3.
4. Connect the SOM module to the RS-232 host using the appropriate cable.
5. Power up the SOM module by applying both 15 V and 3.3 V through the 34-pin host connector.
6. Program the *.hex (located in c:\Texas Instruments\<PackageName>\SW\bin) as shown in Figure 6. If
the UART cable is used, select serial port. Otherwise, if the USB-serial cable is used, select JTAG
port.
Figure 6. Selecting G3-PLC Binary to Be Flashed (via SCI)
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PLC SOM Programming
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7. Start flashing the F28069.
Figure 7. Flashing G3-PLC Firmware (via SCI)
8. Once the flashing is done, close the program and remove the power supply from the SOM module.
9. Make sure the SOM module is not powered off. Set switch SW1 to FLASH Boot Mode as described in
Section 3.
10. Now that the programming procedure is complete, apply power to the SOM module.
10
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Test Setup
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8
Test Setup
To
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8.1
test the SOM modules, the operator will need the following items:
A host computer running Windows® XP or Windows® 7 and two available USB ports.
Two SOM docking stations
A 15-V external power supply for each docking station
A PLC for each docking station
A USB cable for connecting to host PC for each docking station
– A single host PC can be shared between the two kits
Zero-configuration GUI
– Requires a modified .config file
Setup
1. Plug in the included SOM module to each 34-pin SOM module connector.
34 pin SOM
Module Connector
SOMPLC Docking Station
SW2 (SCI-A)
USB
(SCI-A/SCI-B)
Power Grid
Connection
External Power
Connector
SW1 (SCI-B)
SW3
Figure 8. SOMPLC Docking Station
2. Connect Neutral and Line (marked with words on the AC Power Cable) to the power grid connector P1
of each kit. Make sure the neutral and line connections are not shorted.
Figure 9. Line Connection
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Test Setup
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3. Ensure the position of switches SW1 and SW2 are set to their default setting, as shown in Figure 10,
to communicate to PC GUI via SCI-A.
Default settings
ON
SW1
1
2
3
ON
SW2
1
2
Figure 10. Software Configuration
8.2
Power Up
1. Connect the 15-V wall-mounted power supply to the AC receptacle of each kit.
2. Turn on switch SW3 of each kit to power the boards.
OFF (Default setting)
Turn to the inside of board
ON
Turn to the outside of board
Figure 11. SW3
8.3
Connecting to a PC
1. Plug in the micro-USB to the kit and connect the USB cable to the PC. Repeat this step for the second
kit.
NOTE: If asked to install USB-Serial drivers, proceed to install the drivers. The drivers can be found
in C:\Texas Instruments\<PackageName>\XDS100 Drivers. Reboot the PC after the drivers
are installed, even if Windows does not ask to.
2. Verify the modems have been installed correctly by using the Device Manager (Start→Control
Panel→System→Device Manager→Ports).
NOTE: The four ports on picture are for two boards.
Figure 12. Device Manager: Port Configuration
12
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Testing
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9
Testing
1. Install the Zero Configuration tool from C:\TexasInstruments\<PackageName>\Tools, and launch it. If
using one PC to operate, launch two instances, one for each modem.
NOTE: When the zero-configuration GUI opens, it will use the first available COM port to attach to a
PLC.
2. Ensure Diagnostic Port/Data Port configures to SCI-A by pressing CTRL+A in the GUI window.
Figure 13. Zero-Configuration GUI
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Testing
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3. Connect each PLC kit to the power line. Ensure that the devices are connected on the same power
line phase.
WARNING
HIGH VOLTAGE!
Use caution when connecting to the power grid. If there is concern
about connecting to the power grid, use a power strip to connect
the two modems together. In this case, the power strip does not
need to be plugged into the power grid. Connect each PLC kit to
the power line.
SCI-A or SCI-B
Unit 1
Unit 2
Power Line
Figure 14. Testing Setup
14
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Testing
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4. Enter the desired text into the Message Window, and press the Send Message button. The message
will then be received by the other GUI.
Figure 15. P2P Test with Zero-Configuration GUI
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Testing
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5. Use the File Transfer function contained in the bottom left-hand corner of GUI option to transfers files.
Figure 16. File Transfer TX
16
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Testing
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6. Click on the Browse button to display the standard windows file chooser dialog to choose the file to
transfer. Only one file can transfer at a time.
(a) After the file is chosen, click on the Transfer File button.
(b) The other PLC must also be controlled by the zero-configuration GUI.
(c) When the transfer starts, the GUI will display a progress bar on both zero-configuration GUIs. The
GUI in Figure 17 is the receiving zero-configuration GUI and displays the path and file name where
the received file is being copied. The user is not allowed to change the directory path of the
received file.
Figure 17. File Transfer RX
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Testing
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When the file transfer completes, the message box below displays on both zero-configuration GUIs.
Figure 18. Message Box
If the file transfer fails, the sending GUI displays one of the following message boxes.
Figure 19. Case 1: File Transfer Failed
Figure 20. Case 2: File Transfer Failed
Cancel the file transfer by clicking on the Cancel button on either GUI.
18
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Design Files
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10
Design Files
10.1 Schematics
To download the schematics for each board, see the design files at TIDM-SOMPLC-G3-CENELEC.
NOTE: The transformer may not be necessary in a production design.
3V3
3V3
U1A
56R
R1
R33
22
23
24
25
26
27
ADCINB0
C2
3n3F
ADCINB0
ADCINB1
ADCINB2/COMP1B/AIO10
ADCINB4/COMP2B/AIO12
ADCINB5
ADCINB6/COMP3B/AIO14
ADCINA0/VREFHI
ADCINA1
ADCINA2/COMP1A/AIO2
ADCINA4/COMP2A/AIO4
ADCINA5
ADCINA6/COMP3A/AIO6
GPIO0/EPWM1A
GPIO1/EPWM1B/EMU0(O)/COMP1OUT
GPIO2/EPWM2A
GPIO3/EPWM2B/SPISOMIA/COMP2OUT
GPIO4/EPWM3A
GPIO5/EPWM3B/SPISIMOA/ECAP1
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO7/EPWM4B/SCIRXDA/ECAP2
GPIO8/EPWM5A/ADCSOCAON
GPIO9/EPWM5B/SCITXDB/ECAP3
GPIO10/EPWM6A/ADCSOCBON
GPIO11/EPWM6B/SCIRXDB/ECAP1
GPIO12/TZ1N/SCITXDA/SPISIMOB
GPIO13/TZ2N/SPISOMIB
GPIO14/TZ3N/SCITXDB/SPICLKB
GPIO15/ECAP2/SCIRXDB/SPISTEB
GPIO16/SPISIMOA/TZ2N
GPIO17/SPISOMIA/TZ3N
GPIO18/SPICLKA/SCITXDB/XCLKOUT
GPIO19/XCLKIN/SPISTEA/SCIRXDB/ECAP1
GPIO20/EQEP1A/MDXA/COMP1OUT
GPIO21/EQEP1B/MDRA/COMP2OUT
GPIO22/EQEP1S/MCLKXA/SCITXDB
GPIO23/EQEP1I/MFSXA/SCIRXDB
GPIO24/ECAP1/EQEP2A/SPISIMOB
GPIO25/ECAP2/EQEP2B/SPISOMIB
USB0DP/GPIO26/ECAP3/EQEP2I/SPICLKB
USB0DM/GPIO27/HRCAP2/EQEP2S/SPISTEB
GPIO28/SCIRXDA/SDAA/TZ2N
GPIO29/SCITXDA/SCLA/TZ3N
GPIO30/CANRXA/EQEP2I/EPWM7A
GPIO31/CANTXA/EQEP2S/EPWM8A
3V3
R9
GPIO32/SDAA/EPWMSYNCI/ADCSOCAON
GPIO33/SCLA/EPWMSYNCO/ADCSOCBON
GPIO34/COMP2OUT/EMU1(O)/COMP3OUT
GPIO39
2K
DNP
19
18
17
16
15
14
C55
C1
0.1UF
DNP
U2
3V3
1K
R4
1K
1
2
3
4
R2 56R
6
EMU0
R3
3
ADCINA1
69
68
67
66
7
8
46
45
NC
A1
A2
GND
8
7
6
5
VCC
WP
SCL
SDA
SCL
SDA
C3
6
6
3
3
GPIO_04
GPIO_05
GPIO_06
GPIO_07
3n3F
AT24C1024
NO STUBS
GPIO_08
43
39
60
59
35
75
76
70
44
42
41
52
5
6
78
1
ZC
GPIO_10
6
6
GPIO_12
GPIO_13
TX_B
RX_B
3
6
6
6
DNP
R5
680R
R6
680R
D1
D2
3V3
6
6
6
6
3
3
3
3
C4
0.1UF
U3
GPIO_08
1
GPIO_39
3
2
6
6
6
6
6
6
USBDP
USBDM
RX_A
TX_A
CANRX
CANTX
3V3
LED_RED_5MA_SMT
LED_RED_5MA_SMT
SPISIMOA
SPISOMIA
SPICLKA
SPISTEA
MDXA_SPISIMO
MDRA_SPISOMI
MCLKXA_SPICLK
MFSXA_SPISTE
77
31
62
61
40
34
33
32
79
80
55
53
R34
DNP
R7
5K49
5K49
1Y
GND
2Y
5
6
4
OPTIONAL if BOR is handled by
the system or Host processor
6
6
6
SDA
SCL
EMU1
GPIO_39
Vcc
2A
SN74LVC2G07DBVR
3V3
R8
1A
3V3
R10 57K6
36
9
RESETn
20Mhz OSC 20ppm
X1
X2
48
47
TEST2
XRSN
X1
X2
GPIO35(TDI)
GPIO36(TMS)
GPIO37(TDO)
GPIO38/XCLKIN(TCK)
TRSTN
57
58
56
54
10
TDI
TMS
TCK
TRST
6
6
6
6
3V3
TDO
X1
X2
3
GND2
GND1
5
R12
F2806x_80Pin
1
o
o
2
3
o
o
4
C7
15pf
2POS_DIPSW
4
2
15pf
U4
3V3
2K2
C6
57K6
SW1
X1
1
R11
6
C5
0.1UF
3
4
2
R13
2K2
R14
2K2
R15
6
VDD
MRz
RESETz
1
RESETn
WDI
GND
TPS3828
RSTn
0R
Bootmode selection can be
hard wired if reqired modes
are known.
Figure 21. MCU
TIDU442A – July 2014 – Revised February 2015
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3V3
Vafe
R16
10K
R17
10K
R18
10K
R19
10K
3V3
3V3
U11
18V
U6
2
2
DVDD
3
4
5
6
7
2 MCLKXA_SPICLK
2 MDXA_SPISIMO
2 MDRA_SPISOMI
2 MFSXA_SPISTE
GPIO_07
SCLK
DIN
DOUT
CS
DAC
35
34
33
32
31
R20
10K
R21
10K
ZC_IN1
ZC_IN2
ZC_OUT1
ZC_OUT2
8
9
10
48
47
46
3V3
R32
33K
SD
INT
TSENSE
RX_FLAG
TX_FLAG
PA_ISET
19
28
R22
10K
1
2
C14
10nF
GPIO_06
PA_OUT2
PA_OUT1
PA_IN
E_TX_CLK
E_TX_IN
E_TX_OUT
E_RX_IN
E_RX_OUT
39
38
37
36
GPIO_12
AVDD1
AVDD2
PA_VS2
PA_VS1
C15
1uF
TX_F_OUT
TX_F_IN2
TX_F_IN1
TX_PGA_OUT
TX_PGA_IN
RX_PGA1_IN
RX_PGA1_OUT
RX_F_IN
RX_C1
RX_C2
RX_F_OUT
RX_PGA2_IN
RX_PGA2_OUT
C1
C2
AGND1
AGND2
PA_GND2
PA_GND1
DGND
PowerPad
11
30
44
45
42
43
18
4
TxLinePF
C8
3n3F
17
16
15
14
13
R42
TP_CLIP_5015
R41
C62
DNP
C61
TP1
27
26
25
24
23
22
21
20
RxLineF
DNP
4
Optional Components:
necessary for G1 only, use
2700 pF 6V for C62 and
a 510R 5% for R42
C9
10nF
C10
680pf
C11
680pf
Optional Components:
necessary for G1 only, use
2700 pF 6V for C61 and
a 510R 5% for R41
12
29
40
41
49
NOTE:
For CENELEC A band use 680pf for C10 and C11
For CENELEC B/C band use 560pf for C10 and
270pf for C11.
TP3
TP_CLIP_5015
R23
330R
AFE031
ADCINA1
C53
10nF
0
0
2
C54
1uF
as close to U6 as possible
Minimize Trace Length
Place Near U6
Vafe
C16
100nF
C17
100nF
C18
10nF
C19
10nF
C20
10UF
C21
47uf
U6 MUST BE on TOP (OUTER, FREE-AIR) side of board.
Place Near U6
3V3
C22
100nF
C23
10nF
C24
10nF
C25
10nF
C26
10UF
Figure 22. AFE031
20
System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
Copyright © 2014–2015, Texas Instruments Incorporated
TIDU442A – July 2014 – Revised February 2015
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TP4
TP_CLIP_5015
3V3
U7
DNI C27
3
RxLineF
L1
330uH
R24
150R
RxLineF
RxLine
U8
10nF
DNI
L2
C29
22nf
Vafe
R25
150R
470uH
Vafe
R30
DNP
3
6
C28 33nf
U9
B350A-13-F
L3
C30
1uH
10UF
TxLine
TxLinePF
R31
DNP
6
U10
B350A-13-F
NOTE: Several components on this page have
been removed or changed in the BOM.
Figure 23. AFE1 (Passive RX Filter)
TIDU442A – July 2014 – Revised February 2015
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OPTIONAL: Heatsink is not needed.
3V3
3V3
P1
1
2
1V8
1
2
HS
C31
10UF
U1B
37
20
3V3
4
11
30
49
63
74
R43
10k
71
3
13
28
50
R27
DNP
VDD3VFL
VDDA
VDDIO.1
VDDIO.2
VDDIO.3
VDDIO.4
VDDIO.5
VDDIO.6
VDD.6
VDD.5
VDD.4
VDD.3
VDD.2
VDD.1
PWRPAD1
VREGENZ
VSSA/VREFLO
VSS.1
VSS.2
VSS.7
VSS.3
VSS.6
VSS.4
VSS.5
72
65
51
29
12
2
+ C32
47UF
+ C35
47UF
C33
0.1uf
C34
0.1uf
C36
0.1uf
C37
0.1uf
C38
0.1uf
C39
0.1uf
C40
0.1uf
C41
0.1uf
Place caps under U1
81
1V8
21
38
73
64
C42
10UF
+ C43
47UF
+ C44
47UF
C45
0.1uf
C46
0.1uf
C47
0.1uf
C48
0.1uf
C49
0.1uf
C50
0.1uf
F2806x_80Pin
Place caps under U1
OPTIONAL: to source VDD with the
on chip LDO, do not populate R43
and place a 10k resistor on R27.
Additionaly, the optional components
below are not needed.
3V3
3
C56
2
4u7
VIN
1V8
L4
U12
1
SW
5
2u2H
EN
GND
FB
4
R35
357k
C57
33pf
C58
10uf
TPS62240
R36
165K
OPTIONAL: For reduced power consumption use a
DC/DC converter instead of the On-Chip Linear Supply
Note: Follow Layout Procedures
described in TPS62240 Datasheet
Figure 24. Power
22
System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
Copyright © 2014–2015, Texas Instruments Incorporated
TIDU442A – July 2014 – Revised February 2015
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3V3 Vafe
J1
TP5
TP_CLIP_5015
TXRX
0R
4
TxLine
4
RxLine
R28
TXRX
0R
R29
2
2
2
2
2
2
2
2
2
3V3
J2
2
2
2
2
TRST
TMS
TDI
TCK
2
1
3
11
9
2
2
2
TDO
EMU0
EMU1
7
13
14
TRST_N
TMS
TDI
TCK
TCK_RET
TDO
EMU0
EMU1
KEY
VDD
GND
GND
GND
GND
6
5
GPIO_13
ZC
RX_A
TX_A
GPIO_05
GPIO_10
SDA
SCL
ADCINB0
2
2
RSTn
GPIO_04
2
2
RX_B
TX_B
2
USBDP
2
USBDM
2
2
2
2
2
2
CANRX
CANTX
SPICLKA
SPISTEA
SPISIMOA
SPISOMIA
4
8
10
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
L1
L2
BLANK1
BLANK2
GND1
GND2
V15
3V3
EN
ZC
RX-A
TX-A
FB
FC
SDAA
SCLA
ADC-B0
AGND
USBDP
GND3
USBDM
GND4
CANRX
CANTX
CLKC
STEC
SIMOC
SOMIC
RESET
PWM/GPIO04
BLANK9
BLANK10
RX-B
TX-B
SBH31-NBPB-D17-SP-BK
DSP JTAG Header
Figure 25. Connector
space
space
space
space
space
space
space
space
space
space
space
space
space
space
space
space
TIDU442A – July 2014 – Revised February 2015
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23
Design Files
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10.2 Bill of Materials
To download the bill of materials (BOM), see the design files at TIDM-SOMPLC-G3-CENELEC.
Table 3. BOM
ITEM
#
24
PART
#
QTY
PART
TYPE
PART
REF
VENDOR
VENDOR
PN
VALUE
PCB
FOOTPRINT
TOLERANCE
AVX
0603YC104KA
T*A
Capacitor, 0.1
µF,16 V,
10 %,X7R, 0603
0.1 µF
C0603
10%
Cap Ceramic 10 V
SMT 0402
3n3F
C0402
0
GRM1555C1H
150JZ01D
Cap Cer 15 pF 50
V 5% C0G 0402
15 pF
C0402
ECHU1H332JX5
CAP .0033 µF 50
V PPS Film 1206
5%
3n3F
Cap Ceramic 10 V,
SMT 0402
1
10000003
3
CAP
C1, C4, C5
2
30000017
2
CAP
C2, C3
3
30000056
2
CAP
C6, C7
4
30000038
1
CAP
C8
5
30000013
1
CAP
C9
6
30000085
2
CAP
C10, C11
Yageo
CC0805KRX7
R9BB681
7
30000040
5
CAP
C14, C23, C24,
C25, C53
Murata
GRM188R71C
103KA01D
8
30000036
2
CAP
C15, C54
Taiyo Yuden
9
30000041
2
CAP
C16, C17
Murata
GRM155F51E
104ZA01D
10
30000043
2
CAP
C18, C19
Murata
GRM188R71E
103KA01D
11
30000039
2
CAP
C20, C30
Taiyo Yuden
12
30000042
1
CAP
C21
13
30000014
1
CAP
14
30000008
1
15
30000037
1
DESCRIPTION
DISTRIBUTOR
PN
DISTRIBUTOR
478-1239-2-ND
Digikey
0
490-1280-1-ND
Digikey
C1206
0
PCF1334CT-ND
Digikey
10 nF
C0402
0
Cap 680 pF 50 V
Ceramic X7R 0805
680 pF
C0805
0
311-1126-1-ND
Digikey
Cap Cer 10000 pF
16 V 10% X7R
0603
10 nF
C0603
0
490-1525-2-ND
Digikey
UMK107BJ105 Cap Ceramic 50 V
KA-T
SMT 0603
1 µF
C0603
0
587-2400-1-ND
Digikey
Cap Cer .1 µF
(100nf) 25 V Y5V
0402
100 nF
C0402
0
490-3271-1-ND
Digikey
Cap Cer 10000 pF
(10nf) 25 V 10%
X7R 0603
10 nF
C0603
0
490-1520-1-ND
Digikey
GMK316F106Z Cap Ceramic 35 V
L-T
SMT 1206
10 µF
C1206
0
587-1352-1-ND
Digikey
TDK
C5750Y5V1E4
76Z
Cap Cer 47 µF 25
V Y5V 2220
47 µF
C2220
0
445-3486-2-ND
Digikey
C22
Kemet
Electronics
Corporation
C0402C104K8
PACTU
Cap Ceramic 10 V
SMT 0402
100 nF
C0402
0
399-3027-2-ND
Digikey
CAP
C26
Panasonic
ECJ2FB0J106M
Capacitor,10UF,6.
3 V, 20 %, X5R,
10 µF
C0805
0.2
CAP
C27
AVX
06035C103KA
T2A
Cap Ceramic 50 V
SMT 0603
10 nF
C0603
0
478-1227-1-ND
Digikey
Murata
Panasonic
System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
Copyright © 2014–2015, Texas Instruments Incorporated
CROSS
REF
TIDU442A – July 2014 – Revised February 2015
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Table 3. BOM (continued)
ITEM
#
PART
#
QTY
PART
TYPE
PART
REF
VENDOR
VENDOR
PN
DESCRIPTION
VALUE
PCB
FOOTPRINT
TOLERANCE
DISTRIBUTOR
PN
DISTRIBUTOR
CROSS
REF
16
30000028
1
CAP
C28
Cap Ceramic SMT
0402
33 nF
C0402
0
17
30000026
1
CAP
C29
Cap Ceramic SMT
0402
22 nF
C0402
0
18
30000011
2
CAP
C31, C42
ECJ1VB0J106M
Cap Ceramic 10
µF 6.3 V X5R
0603
10 µF
C0603
20%
rPCC2395CTND
Digikey
19
30000012
4
CAP
C32, C35, C43,
C44
Vishay
298D476X001
0P2T
Cap Tant 47 µF 10
V 20% 0805
47 µF
C0805P
0
718-1608-1-ND
Digikey
20
30000044
14
CAP
C33,
C37,
C40,
C46,
C49,
Murata
GRM155R61A
104KA01D
Cap Cer .1 µF 10
V 10% X5R 0402
0.1 µF
C0402
0
490-1318-1-ND
Digikey
21
30000057
3
CAP
C55, C61, C62
Cap Ceramic SMT
0402
DNP
C0402
0
22
30000063
1
CAP
C56
TDK
Cap Cer 4.7 µF
C1005X5R0G4
4.0 V X5R 10%
75K
0402
DNI
DNI
0
445-5949-1-ND
Digikey
DNI
23
30000062
1
CAP
C57
Johanson
Dielectrics
Inc
250R07S330J
V4T
Cap Cer 33pF 25
V S 0402 UHI Q
DNI
DNI
0
712-1298-1-ND
Digikey
DNI
24
30000064
1
CAP
C58
TDK
C1608X5R0J1
06M
Cap Cer 10 µF 6.3
V X5R 20% 0603
DNI
DNI
0
445-4112-1-ND
Digikey
DNI
25
20000010
2
FET_DI
D1, D2
ODE
Panasonic
LNJ208R8ARA
LED, Red, 3.0 VR,
0.2 IF,Surf. Mount
LED_RED_5
LED0603H35
MA_SMT
0
26
32000013
1
CONN
Sullins
Connector
Solutions
SBH31-NBPBD17-SP-BK
CONN. header
1.27 mm 34-POS
GOLD SMD
SBH31NBPB-D17SP-BK
Male
0
S9108-ND
Digikey
27
12000068
1
CONN
J2
SAMTEC
TSM-107-01S-DV
CONN. 2 × 7
header, SMT, DSP
JTAG, Pin 6
removed
DSP JTAG
Header
hdr_14p
0
28
33000009
1
MAGN
ETICS
L1
Panasonic ECG
ELJ-EA331KF
Inductor 330 µH
10% 1210 SMD
330 uH
IND1210
0
PCD1432CT
Digikey
29
33000010
1
MAGN
ETICS
L2
Taiyo Yuden CB2518T471K
Inductor power
470 µH 1007
470 uH
IND1007
0
587-2194-1-ND
Digikey
30
33000011
1
MAGN
ETICS
L3
Taiyo Yuden LB3218T1R0M
Inductor 1.0 µH
1.075 A 20% SMD
1 uH
IND1207
0
587-2032-1-ND
Digikey
31
33000021
1
MAGN
ETICS
L4
Inductor 2.2 µH
350 ma 20% 0805
DNI
DNI
0
445-3625-1-ND
Digikey
C34,
C38,
C41,
C47,
C50
Panasonic
C36,
C39,
C45,
C48,
J1
TIDU442A – July 2014 – Revised February 2015
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GLCR2012T2
R2M-HC
DNI
System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
Copyright © 2014–2015, Texas Instruments Incorporated
25
Design Files
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Table 3. BOM (continued)
ITEM
#
26
PART
#
QTY
PART
TYPE
32
49000002
1
33
31000041
2
RES
34
31000035
2
35
31000011
36
PART
REF
VENDOR
VENDOR
PN
Heat_S
P1
ink
DESCRIPTION
VALUE
PCB
FOOTPRINT
TOLERANCE
DNI
DNI
R1, R2
Resistors 56R, 5%
- SMD, 0402
56R
R0402
0.05
RES
R3, R4
Resistors,1K,5%,
SMD,0402
1K
R0402
0
2
RES
R5, R6
Resistors, 680R,
5% - SMD, 0603
680R
R0603
0.05
31000042
2
RES
R7, R8
Resistors 5K49 5%
- SMD, 0402
5K49
R0402
0
37
31000043
1
RES
R9
Resistors 2K 5% SMD, 0402
2K
R0402
0
38
31000044
2
RES
R10, R11
Resistors 57K6 5%
- SMD, 0402
57K6
R0402
0
39
31000045
3
RES
R12, R13, R14
Resistors 2K2 5%
- SMD, 0402
2K2
R0402
0
40
31000029
3
RES
R15, R28, R29
Resistors, 0R, 5%
- SMD, 0402
0R
R0402
0
41
31000049
7
RES
R16, R17, R18,
R19, R20, R21,
R22
Resistor 10K 5% SMD,0402
10K
R0402
0
42
31000063
1
RES
R23
Res 330 Ω 1/16W
5% 0402 SMD
330R
R0402
0
43
31000051
2
RES
R24, R25
Resistor 150R 5%
- SMD,0402
150R
R0402
0
44
31000030
3
RES
R33, R34
Resistors, DNP SMD, 0402 (Do
not populate)
DNP
R0402
0
45
11000230
2
RES
R30, R31
Resistors DNP SMD, 0603
DNP
R0603
0
46
31000067
1
RES
R32
Resistor 33-K 5% SMD,0402
33K
R0402
0
47
31000090
1
RES
R35
Panasonic
ERJ2RKF3573X
RES 357-KΩ
1/10W 1% 0402
SMD
DNI
DNI
48
31000091
1
RES
R36
Panasonic
ERJ2RKF1653X
RES 165-KΩ
1/10W 1% 0402
SMD
DNI
49
31000102
2
RES
R41, R42
Panasonic ECG
ERJ2GE0R00X
RES 0.0 Ω 1/10 W
0402 SMD
0
Vishay
CRCW040233
0RJNED
System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
Copyright © 2014–2015, Texas Instruments Incorporated
DISTRIBUTOR
PN
DISTRIBUTOR
0
CROSS
REF
DNI
541-330JCT-ND
Digikey
0
P357KLCT-ND
Digikey
DNI
DNI
0
P165KLCT-ND
Digikey
DNI
R0402
0
P0.0JCT-ND
Digikey
TIDU442A – July 2014 – Revised February 2015
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Table 3. BOM (continued)
ITEM
#
PART
#
QTY
PART
TYPE
RES
PART
REF
50
31000104
1
51
20600010
1
SWITC
SW1
H
52
28000005
4
MTG_
TP1, TP3, TP4,
HOLE_
TP5
TP
53
40000003
2
FET_DI
U10, U9
ODE
54
40000007
1
FET_DI
U11
ODE
55
40200037
1
IC
U12
56
40200034
1
IC
57
40200027
1
IC
58
40200005
1
59
20300037
1
60
40200028
1
61
40000027
2
FET_DI
U7, U8
ODE
62
40500009
1
OSC_X
X1
TAL
63
31000030
3
VENDOR
VENDOR
PN
DESCRIPTION
VALUE
PCB
FOOTPRINT
TOLERANCE
DNP
R0402
0
Panasonic
ERJ2GEJ103X
RES 10-KΩ 1/10
W 5% 0402 SMD
CTS
218-2LPST
Switch DIP Half
Pitch 2POS
2POS_DIPS
W
SMT218LP_
2POS
0
5015
PC Test Point
Miniature SMT
TP_CLIP_50
15
TP_5015
0
B350A-13-F
Diode Schottky 3A 50-V SMA
B350A-13-F
DO-214AB
1SMB5931BT3
Diode ZENER 3-W
18-V SMB
18 V
TI
TPS62240
2.25-MHz 300-mA
Step Down
Converter
U1
TI
F2806x
U2
Atmel
U3
POWE
U4
R
IC
IC
RES
R43
U6
R27
TIDU442A – July 2014 – Revised February 2015
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DISTRIBUTOR
PN
DISTRIBUTOR
CT2182LPSTND
Digikey
0
B350A-FDICTND
Digikey
DO-214AA
0
1SMB5931BT3G
OSCT-ND
Digikey
DNI
DNI
0
F28069, 80-Pin
PFP LQFP
F2806x_80Pi
n
PFP (80)
0
AT24C1024BTH-T
IC EEPROM 1-Mb
1-MHz 8TSSOP
AT24C1024
TSSOP8
0
DNP
TI
SN74LVC2G0
7DBV
IC,Dual
Buffer/Driver with
Open-Drain
Outputs, SOT23-6
SN74LVC2G
07DBVR
DBV6
0
296-13494-2
Digikey
TI
TPS382833DBV
Reset Supervisor,
SOT23-5
TPS3828
DBV5
0
296-2638-1
Digikey
TI
AFE031
AFE031 TI PLC
Integrated AFE,
48-pin QFN RGZ
AFE031
RGZ
0
Diodes Inc
DNI
DNI
DNI
DO-214AB
0
Abracon
Corporation
ABM3B20.000MHZ10-1-U-T
Crystal 20.0000MHz 10-pF SMD
20-Mhz OSC
20ppm
4-SMD
(0.197" L x
0.126" W)
0
300-8214-1-ND
Digikey
Resistors, DNP SMD, 0402
10K
R0402
0
P10KJTR-ND
Digikey
TI
Diodes Inc
On Semi
CROSS
REF
DNI
DNI
System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
Copyright © 2014–2015, Texas Instruments Incorporated
27
Design Files
www.ti.com
10.3 Layer Plots
To download the layer plots, see the design files at TIDM-SOMPLC-G3-CENELEC.
Figure 26. Primary Side
Figure 27. Internal Neg Plane 1
Figure 28. Internal Neg Plane 2
Figure 29. Secondary Side
10.4 Gerber Files
To download the Gerber files, see the design files at TIDM-SOMPLC-G3-CENELEC.
28
System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
TIDU442A – July 2014 – Revised February 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
Design Files
www.ti.com
10.5 Assembly Drawings
To download the Gerber files, see the design files at TIDM-SOMPLC-G3-CENELEC.
Figure 30. Primary Side
11
Figure 31. Secondary Side
Software Files
To download the software files, see the design files at TIDM-SOMPLC-G3-CENELEC.
12
About the Author
WONSOO KIM is a system applications engineer at Texas Instruments, where he is responsible for
providing technical support and training on power-line communication software and systems, driving
solutions for Smart Grid and Energy Metering, and working on defining future requirements in roadmap.
He received a Ph.D. degree in electrical and computer engineering from the University of Texas at Austin,
TX.
NAVEEN KALA is a system applications engineer at Texas Instruments, where he is responsible for
providing technical support and training on power-line communication hardware, driving solutions for
Smart Grid and Energy Metering, and working on defining future requirements in roadmap. He received an
MEng degree in electrical and computer engineering from the University of Iowa.
TIDU442A – July 2014 – Revised February 2015
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System on Module for G3 Power Line Communication (CENELEC Frequency
Band)
Copyright © 2014–2015, Texas Instruments Incorporated
29
Revision History
www.ti.com
Revision History
Changes from Original (July 2014) to A Revision ........................................................................................................... Page
•
•
Changed CENELEC functionality from A, B, C, and D to A ......................................................................... 1
Added note on transformer to Section 10.1 .......................................................................................... 19
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
30
Revision History
TIDU442A – July 2014 – Revised February 2015
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Copyright © 2014–2015, Texas Instruments Incorporated
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