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Rail Cleaner With Adjustable Output Voltage Drop and
Soft-Start Capabilities
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Design Resources
TIDA-00533
Design Folder
LP38798
Product Folder
Low-Noise Post-Regulation Rail Ripple Cleaner
Adjustable Output Voltage Dropout
Output Voltage Disabled Feature
Adjustable Soft-Startup
Small Footprint
Featured Applications
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Input voltage
3 V to 20 V
Personal Electronics: Set-Top Box, Audio, Portable
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Communication Equipment: Audio RF, VCO Power,
Wireless LAN Devices, Wireless Cable Modems,
Servers
Output voltage
VIN minus VDO
DC
Vin
EN
x
Vout
LP38798
SET
GND
R1
FB
C6
Q1
VOFF
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.
All trademarks are the property of their respective owners.
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1
Key System Specifications
1
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Key System Specifications
Table 1. Key System Specifications
PARAMETER
2
SPECIFICATION
DETAILS
Voltage drop
Adjustable output voltage drop
See Section 4.1 and Section 6.3
Safety features
Current limiting
Undervoltage lockout (UVLO)
Thermal shutdown
See Section 4.2
Soft start
Adjustable soft start
See Section 4.3 and Section 6.4
Shut off
Output voltage disable feature with fast
start after exiting the disable mode
See Section 4.4 and Section 6.5
System Description
The TIDA-00533 reference design features a post regulation voltage follower and rail cleaner for noise
sensitive applications, with adjustable output voltage drop, adjustable soft-start, and output disable
features.
These additional safety features make this solution more beneficial than a discrete rail cleaner:
• Output current limiting
• Over temperature protection
• Undervoltage lockout (UVLO)
Design characteristics:
• Minimum operating input voltage: 3 V
• Maximum operating input voltage: 20.0 V
• Output voltage: VIN – VDO
• Adjustable output voltage drop (VDO): 500 mV to 1 V
• Maximum operating output current: 800 mA
2
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Block Diagram
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3
Block Diagram
Input voltage
3 V to 20 V
Output voltage
VIN minus VDO
DC
Vin
EN
x
Vout
LP38798
SET
GND
R1
FB
C6
Q1
VOFF
Figure 1. TIDA-00533 Block Diagram
3.1
3.1.1
Highlighted Devices
LP38798-ADJ
The LP38798-ADJ is a high-performance linear regulator capable of supplying 800 mA output current.
Designed to meet the requirements of sensitive RF/Analog circuitry, the LP38798-ADJ implements a novel
linear topology on an advanced CMOS process to deliver ultra-low output noise and high PSRR at
switching power supply frequencies. The LP38798SD-ADJ is stable with both ceramic and tantalum output
capacitors and requires a minimum output capacitance of only 1 μF for stability.
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System Design Theory
4
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System Design Theory
The blue line and red line in Figure 2 represent two connections that must be made to enable the
LP38798-ADJ as a voltage follower. The blue connection disables Comparator 1 by connecting the
comparator’s negative feedback (FB) input to the higher potential of the Enable pin (EN). The red
connection sets the required voltage drop (VDROP) for the rail cleaner; VDROP is a function of ISET and R1.
Section 4.1 explains how to set the VDROP.
The rail cleaner does a great job of minimizing the input noise. Any noise at the LP38798-ADJ SET pin is
reduced by an internal first-order low-pass RC filter before it is passed to the output buffer stage. The lowpass filter has a –3-dB cut-off frequency of approximately 0.08 Hz. The noise introduced in the IN pins will
be minimized by the Active Ripple Rejection block.
LP38798SD-ADJ
IN
Active Ripple
Rejection
IN
OUT
OUT
PMOS
Current
Limit
+
200 mV
IN
Thermal
Shutdown
+
-
UVLO
OUT
98%
Charge Pump
3.5 MHz
tau= 2 s
R1
2
CP
SET
IEN
2 PA
ISET
52 PA
Typically
+
-
1
99.5%
C6
EN
FB
5V
VOFF
1.24 V
VREF
1.200 V
GND
GND
Figure 2. LP38798SD-ADJ Functional Block Diagram
4
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System Design Theory
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4.1
Voltage Drop Setup
The input-to-output voltage drop must be at least the sum of the dropout voltage at the rated current plus
the peak-to-peak ripple. Failure to set the input-to-output voltage drop to an adequate value will result in
an inferior performance. The resistor R1 may be adjusted as needed to achieve the desired output voltage
drop. Equation 1 determines the output voltage:
(
V OUT = V IN - R1 ´ I SET
)
(1)
Alternately, Equation 2 can determine the appropriate R1 value for a given VDROP:
æ V DROP ö
R1 = ç
÷
ç I SET ÷
è
ø
(2)
The current source from the ISET pin varies depending on the input voltage. An output voltage tolerance of
±5% across the input voltage range is expected if the typical ISET current of 52 μA is used to calculate the
voltage drop. If the application requires a more accurate output voltage at a certain input voltage range,
ISET can be calculated using Equation 3; however, there will be a compromise in the output voltage
accuracy at lower input voltages as shown in Section 6.3.
The XY plot on Figure 3 was made using the typical ISET values from the LP38798-ADJ datasheet
(SNOSCT6). The plot shows a projection of the ISET current at various input voltages.
75
70
65
ISET (µA)
60
55
50
45
40
35
30
3
4
5
6
7
8
9
Input Voltage (V)
10
11
12
13
D001
Figure 3. ISET versus Input Voltage
Equation 3 was obtained from the trend line of Figure 3, which gives an approximation of the ISET current
at various input voltages.
2
( )
I SET = 0.0331 ´ V IN
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( )
+ 2.1188 ´ V IN + 39.349
Rail Cleaner With Adjustable Output Voltage Drop and Soft-Start Capabilities
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(3)
5
System Design Theory
4.2
4.2.1
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Safety Features
Current Limiting
The LP38798-ADJ incorporates active output current limiting. The threshold for the output current limiting
is set well above the ensured output operating current such that it does not interfere with normal
operation.
NOTE: Output current limiting is provided as a safety feature and is outside the recommended
operating conditions. Operation at the current limit is not recommended as the device
junction temperature (TJ) will rise rapidly and operation will likely cross into thermal shutdown
behavior.
4.2.2
UVLO
The LP38798-ADJ incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the
LP38798-ADJ disabled while a rising VIN is less than 2.65 V (typical). The rising UVLO threshold is
approximately 350 mV below the recommended minimum operating VIN of 3 V.
4.2.3
Thermal Shutdown
The LP38798-ADJ includes thermal protection that will shut off the output current when activated by
excessive device dissipation. Thermal shutdown (TSD) occurs when the junction temperature has risen to
170°C. The junction temperature must fall typically 12°C from the shutdown temperature for the output
current to be restored. Junction temperature is calculated from the formula in Equation 4:
(
T J = T A + PD ´ R qJA
)
(4)
The power being dissipated, PD, is defined by Equation 5:
(
)
PD = V IN - V OUT ´ I OUT
(5)
NOTE: Thermal shutdown is provided as a safety feature and is outside the specified operating
ratings temperature range. Operation with a junction temperature (TJ) above 125°C is not
recommended as the device behavior is not specified.
4.3
Soft Start
The programmable soft-start function limits the inrush current to the device being powered and controls
the output voltage raise time during power-up. When the LP38789-ADJ is disabled through a high logic
signal at the VOFF pin, the device will have a fast start-up independent of the soft-start settings.
The resistive-capacitive (R1 × C6) circuit at the SET pin defines the time constant of the output slew rate.
Note that the soft-start function only works when the LDO is powered from 0 VIN, not when the shut-off or
output-disabling function is used.
4.4
Disable Output Voltage Feature
Using the output voltage disable or shut-off feature minimizes the power drain to meet the requirements of
portable battery operated systems while providing a fast start-up after exiting the shut-off mode.
The Enable pin in the LP38798-ADJ is internally pulled high by a 2-μA current. Q1 is used to pull the EN
pin low. The gate of Q1 has a pull-down resistor that keeps Q1 inactive by default by pulling the VOFF pin
high either by connecting to a voltage greater than 2.5 V (typical) or by connecting directly to the input
voltage, which will activate Q1 and will disable the LP38798-ADJ output.
6
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Getting Started: Hardware
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5
Getting Started: Hardware
Before applying power to the TIDA-00533 rail cleaner board, verify all external connections. The external
power supply must be turned off before being connected. Confirm proper polarity to the VIN and GND
terminals before turning the external power supply on. Connect an appropriate load between the VOUT and
GND terminals. Under basic evaluation conditions, all of the test points can be left open. The evaluation
board will be in the normal operating mode when input power is applied.
6
Test Data
6.1
Test Equipment
Table 2. Test Equipment
6.2
TEST EQUIPMENT
PART NUMBER
Oscilloscope
Agilent MSO7034B
Voltage supply
Agilent E6131A
Network analyzer
Agilent E5061B
Digital multimeter
Agilent 34401A
Power Supply Ripple Rejection
The output voltage ripple rejection ratio was calculated by comparing the regulated output ripple to the
input voltage ripple of 50 mV over a frequency range of 10 Hz to 10 MHz.
Input voltage = 5.5 V + 50 mV Cos (ωt)
100
90
PSRR (dB)
80
70
60
50
40
30
10
100
1000
10000
Frequency (Hz)
100000
1000000
1E+7
D002
Figure 4. Frequency versus PSRR
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Test Data
6.3
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Voltage Drop Setup
The output voltage drop is a function of ISET and R1. ISET varies with the input voltage. The higher the
voltage drop, the higher the VOUT tolerance.
When the typical ISET current of 52 μA at 5.5 VIN is used to calculate the output voltage drop, a maximum
output voltage tolerance of ±5% is expected over the full range of the operating voltage at room
temperature 23°C. The blue line in Figure 5 shows the VOUT tolerance at 500 mVDROP. The blue line in
Figure 6 shows the VOUT tolerance at 1 mVDROP. The VOUT tolerance is lower at the lower VDROP setup.
If the application requires a higher output voltage accuracy at a higher input voltage range, the VOUT
tolerance can be optimized by calculating the ISET current using Equation 2 from Section 4.1 and then with
the resulting current value calculate R1 using Equation 3. The green and red lines in Figure 5 and
Figure 6 show a lower VOUT tolerance at higher VIN.
Table 3. Voltage Drop Test Conditions
PARAMETER
VALUE
Load resistance
3.3 kΩ
VIN
3.5 to 20.5 V
5%
500 mV Voltage Drop (Ideal)
500 mV Voltage Drop Optimize for 5.5 V (R1 = 6 k)
500 mV Voltage Drop Optimize for 11.5 V (R1 = 7.5 k)
500 mV Voltage Drop Optimize for 17 V (R1 = 9.53 k)
4%
3%
VOUT Tolerance
2%
1%
0
-1%
-2%
-3%
-4%
-5%
3
4
5
6
7
8
9
10
11
12
13
Input Voltage (V)
14
15
16
17
18
19
20
D003
Figure 5. Output Voltage Tolerance at 500 mVDROP versus Input Voltage
5%
1 V Voltage Drop (Ideal)
1 V Voltage Drop Optimize for 5.5 V IN (R1 = 19.1 k)
1 V Voltage Drop Optimize for 11.5 VIN (R1 = 15 k)
1 V Voltage Drop Optimize for 17 VIN (R1 = 12.1 k)
4%
3%
VOUT Tolerance
2%
1%
0
-1%
-2%
-3%
-4%
-5%
3
4
5
6
7
8
9
10
11
12
13
Input Voltage (V)
14
15
16
17
18
19
20
D004
Figure 6. Output Voltage Tolerance at 1 VDROP versus Input Voltage
8
Rail Cleaner With Adjustable Output Voltage Drop and Soft-Start Capabilities
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Test Data
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6.4
Soft Start
The soft-start function was evaluated by shutting down the LP38798-ADJ completely and applying 5.5 V at
the VIN pin.
Table 4. Soft Start Test Conditions
PARAMETER
VALUE
Load resistance
3.3 kΩ
VIN
3.5 to 20.5 V
R1 and C6 form the RC time constant (Tau), which contributes to the output voltage rise time (TRISE).
Figure 7 shows the relationship of Tau and TRISE.
160
140
TRISE (mS)
120
100
80
60
40
20
0
0
20
40
60
80
100
Tau (mS)
D005
Figure 7. Output Voltage Rise Time (TRISE) versus RC Time Constant (Tau)
Equation 6 gives a close approximation of the time that the output voltage takes from 10% VOUT_MAX to
reach 90% VOUT_MAX.
T RISE = - 0.001 ´ Tau 2 + 1.6114 ´ Tau + 2.1897
(6)
Table 5 compares the discrepancy between the computed TRISE using Equation 6 and the measured TRISE
at different time constants settings.
Table 5. Measured TRISE versus Computed TRISE
Tau (ms)
COMPUTED TRISE (ms)
MEASURED (ms)
DISCREPANCY (%)
1
3.8
3.8
0
10
18.2
18.2
0
35.2
57.7
56
3
56.9
90.6
94
4
70.5
110.8
106
5
90.2
139.5
146
4
94
144.8
154
6
100
153
153
0
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Test Data
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Figure 8. No Capacitor C6;
Tau = N/A; Measured TRISE = 2.54 ms
Figure 9. Tau = 1 ms; Measured TRISE = 3.80 ms
Figure 10. Tau = 10 ms; Measured TRISE = 18.2 ms
Figure 11. Tau = 100 ms; Measured TRISE = 153 ms
Rail Cleaner With Adjustable Output Voltage Drop and Soft-Start Capabilities
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Test Data
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6.5
Disable Output Voltage and Fast Startup
This test was accomplished by applying 2.5 V at the VOFF pin to disable the output voltage and then
removing the 2.5 V at the VOFF pin to enable the output voltage again.
Table 6. Disable Output Voltage Test Conditions
PARAMETER
VALUE
VIN
5.5 V
IOUT
383 mA
VOFF
2.5 V
Load resistance
13 Ω
C3
10-µF ceramic
C4
10-µF tantalum
When 2.5 V is applied to the VOFF pin under the specified conditions, the output voltage takes
approximately 1 ms to fall from 5 to 0 VOUT.
VIN
VOUT
Figure 12. VOFF from Low to High
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Test Data
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When 2.5 V is removed from the VOFF pin, the device exits the shut-off mode and the output voltage rises
from 0 VOUT to 5 VOUT in approximately 40 μs as shown in Figure 13.
VIN
VOUT
Figure 13. VOFF from High to Low
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Design Files
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7
Design Files
7.1
Schematics
To download the schematics, see the design files at TIDA-00533.
U1
TP1
VIN
VIN
C1
10µF
C2
1µF
FB_EN
1
2
IN[CP]
4
CP
EN
V_OFF
2N7002KW
Q1 C5
1
6
GND[CP]
0.1µF
VOUT
OUT
VOUT
C3
10µF
11
C4
10µF
10
OUT[FB]
9
SET
R1
8
FB
FB_EN
VIN
10.0k
7
13
GND
DAP
LP38798SD-ADJ/NOPB
2
R2
100k
6091
12
OUT
3
V_OFF
IN
3
5
TP5
IN
TP2
GND
C6
10µF
GND
GND
6092
TP3
6092
TP4
Figure 14. TIDA-00533 Schematic
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Design Files
7.2
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Bill of Materials
To download the bill of materials (BOM), see the design files at TIDA-00533.
7.3
PCB Layout Recommendations
The dynamic performance of the LP38798 is dependant on the layout of the PCB. PCB layout practices
that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the
LP38798.
Best performance is achieved by placing all of the components on the same side of the PCB as the
LP38798, and as close as is practical to the LP38798 package. All component ground connections should
be back to the LP38798 analog ground connection using as wide, and as short, of a copper trace as is
practical. The datasheet recommends a short connection between the FB pin and VSET; in this case, the
FB trace length will not be as critical.
Connections using long trace lengths, narrow trace widths, and connections through vias should be
avoided. These connections will add parasitic inductances and resistance that results in an inferior
performance, especially during transient conditions.
A ground plane, either on the opposite side of a two-layer PCB or embedded in a multi-layer PCB, is
strongly recommended. This ground plane serves two purposes:
1. Provides a circuit reference plane to assure accuracy
2. Provides a thermal plane to remove heat from the LP38798 through thermal vias under the package
DAP
7.3.1
Layer Plots
To download the layer plots, see the design files at TIDA-00533.
7.4
Altium Project
To download the Altium project files, see the design files at TIDA-00533.
7.5
Gerber Files
To download the Gerber files, see the design files at TIDA-00533.
7.6
Assembly Drawings
To download the assembly drawings for each board, see the design files at TIDA-00533.
8
References
1. Texas Instruments, Soft-start circuits for LDO linear regulators, Analog and Mixed-Signal Products
Technical Brief (SLYT096).
9
About the Author
ANTONY PIERRE CARVAJALES is an applications engineer on the mobile power devices RF power
group at Texas Instruments. Antony has worked in various business units expanding his knowledge in
analog circuitry design to help customers solve their design challenges using TI technologies. Antony
earned his bachelors of science in electrical engineering from Florida International University, FL.
14
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