Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 LP38798-ADJ High PSRR, Ultra Low Noise, 800 mA Linear Voltage Regulator for RF/Analog Circuits FEATURES DESCRIPTION • The LP38798-ADJ is a high performance linear regulator capable of supplying 800 mA output current. Designed to meet the requirements of sensitive RF/Analog circuitry, the LP38798-ADJ implements a novel linear topology on an advanced CMOS process to deliver ultra-low output noise and high PSRR at switching power supply frequencies. The LP38798SD-ADJ is stable with both ceramic and tantalum output capacitors and requires a minimum output capacitance of only 1 µF for stability. 1 • • • • • • • Ultra-Low Output Noise: 5 µVRMS (10Hz to 100 kHz) High PSRR: 90 dB at 10 kHz, 60 dB at 100 kHz Wide Operating Input Voltage Range: 3.0V to 20V ±1.0% Output Voltage Initial Accuracy (TJ = 25°C) Very Low Dropout : 200 mV (Typical) at 800mA Stable with Ceramic or Tantalum Output Capacitors Excellent Line and Load Transient Response Current Limit and Over-Temperature Protection The LP38798-ADJ can operate over a wide input voltage range (3.0V to 20V) making it well suited for many post-regulation applications. The LP38798-ADJ is available in a 12-Lead WSON package (4.0 x 4.0 x 0.8 mm) with Thermal Pad. APPLICATIONS • • • • RF and VCO Power Wireless LAN Devices Wireless Cable Modems Low Noise Post-Regulation Typical Application Circuit 1 VIN 2 3 + VEN IN OUT IN OUT IN(CP) OUT(FB) 12 VOUT 11 10 COUT LP38798-ADJ CIN 4 CP SET EN FB 9 CCP R1 5 8 ON OFF 6 7 GND(CP) R2 GND DAP GND GND *. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com Connection Diagram Top View IN 1 2 3 CP 4 EN 5 GND(CP) 6 Exposed Pad on Bottom (DAP) LP38798SD IN IN(CP) 12 OUT 11 OUT 10 OUT(FB) 9 SET 8 FB 7 GND Connect WSON DAP to GND at Pins 6 and 7 Figure 1. LP38798SD-ADJ 12-Lead WSON Package (Top View) PIN DESCRIPTIONS Pin Name Function 1, 2 IN 3 IN(CP) Device unregulated input voltage pins. Connect pins together at the package. Charge pump input voltage pin. Connect directly to pins 1 and 2 at the package. 4 CP Charge pump output. See Charge Pump section in the Applications Information for more information. 5 EN Enable pin. A Logic high level is required on this pin to enable the LDO output. A Logic low level will turn the output off and reduce the operating current of the device. See Enable Input Operation section in the Applications Information for more information. 6 GND Device charge pump ground pin. 7 GND Device analog ground pin. 8 FB 9 SET 10 OUT(FB) OUT buffer feedback pin. Connect directly to pins 11 and 12 at the package. 11, 12 OUT Device regulated output voltage pins. Connect pins together at the package. Exposed Pad DAP The exposed die attach pad on the bottom of the package should be connected to a thermal pad at ground potential. See 12-Lead WSON Package Thermal Considerations section in the APPLICATIONS INFORMATION for more information. Feedback pin for programming the output voltage. Internally filtered pre-buffered output. A feedback resistor divider network from this pin to FB and GND will set the output voltage of the device. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 2 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) IN –0.3V to 22V OUT –0.3V to VIN +0.3V FB, EN –0.3V to 6.0V Storage Temperature Range –65°C to +150°C Soldering (2) 260°C, 10 sec ESD Rating (HBM) (3) 2 kV Power Dissipation (4) Internally Limited IOUT (Survival) Internally Limited (1) (2) (3) (4) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. Peak Reflow Temperatures for Surface Mount devices are defined in “Absolute Maximum Ratings for Soldering,” Literature Number: SNOA549C The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5 kΩ; resistor into each pin. Applicable test standard is JESD-22-A114-C. The value of θJ−A for the WSON package is dependent on PCB copper area, copper thickness, the number of copper layers in the PCB, and the number of thermal vias under the exposed thermal pad (DAP). Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator may go into thermal shutdown. See 12-Lead WSON Package Thermal Considerations in the Applications Information. OPERATING RATINGS (1) Input Voltage, VIN 3.0V to 20.0V Output Voltage, VOUT 1.2V to (VIN – VDO) Enable Voltage, VEN 0.0V to 5.0V Junction Temperature, TJ (1) –40°C to +125°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Operating Range conditions indicate the conditions at which the device is functional and the device should not be operated beyond such conditions. 3 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of –40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Minimum and Maximum limits are specified through test, design, or statistical correlation. Unless otherwise stated the following conditions apply: VIN = 5.5 V, VSET = 5.0 V, CCP= 10 nF X7R, CIN = 10 μF 50 mΩ Tantalum, COUT = 10 μF X7R MLCC, IOUT = 10 mA, and TJ = 25°C. Symbol Parameter VFB Feedback Voltage VOS VOUT – VSET IFB Feedback Pin Current ISET SET Pin Internal Current Sink ΔVOUT / ΔVIN Line Regulation (1) 1.212 1.224 16.0 mV 1 µA VIN = 3.0 V, VSET = 2.5 V - 46 - VIN = 5.5 V, VSET = 5.0 V 25.2 52 67.8 VIN = 12.5 V, VSET = 12.0 V - 71 - 5.5 V ≤ VIN ≤ 20.0 V IOUT = 10 mA - 0.005 - %/V - -0.2 - %/A IOUT = 800 mA Undervoltage Lock-Out VIN Rising until output is on UVLO Hysteresis - 200 420 mV 2.65 2.83 V VIN Falling from > UVLO threshold until output is off - 180 - mV IOUT = 800 mA - 1.4 2.25 VIN = 20.0 V, IOUT = 800 mA - 1.6 2.51 Ground Pin Current, Quiescent (4) IOUT = 0 mA - 1.4 2.1 VIN = 20.0 V, IOUT = 0 mA - 1.5 2.2 ISD Ground Pin Current, Shutdown (4) VEN = 0.0 V - 9 20 VIN = 20.0 V, VEN = 0.0 V - 12 40 ISC Short Circuit Current RLOAD = 0Ω 850 1200 1600 - 2.8 - VIN = 20.0V - 2.3 - From VEN > VEN(ON) to VOUT ≥ 98% of VOUT(NOM) - 155 300 VOUT = 1.2 V, f = 10 kHz - 110 - VOUT = 5.0 V, f = 10 kHz - 90 - VOUT = 1.2 V, f = 100 kHz - 90 - VOUT = 5.0 V, f = 100 kHz - 60 - VOUT = 1.2 V, f = 1 MHz - 70 - VOUT = 5.0 V, f = 1 MHz - 60 - VCP – VIN tSTART Start-up Time Power Supply Rejection Ratio μA 2.47 IQ ΔVCP V 0 Dropout Voltage (3) PSRR (4) 1.2 Units 3.5 VDO Ground Pin Current (4) 1.176 Max - VIN = 5.5 V 10 mA ≤ IOUT ≤ 800 mA IGND Typical 0 VFB = 1.2 V Load Regulation (2) ΔUVLO Min 1.188 5.5 V ≤ VIN ≤ 20.0 V ΔVOUT / ΔIOUT UVLO (1) (2) (3) Conditions mA mA µA mA V µs dB Line Regulation: % change in VOUT(NOM) for every 1V change in VIN= (( ΔVOUT / VOUT(NOM)) / ΔVIN ) x 100% Load Regulation: % change in VOUT(NOM) for every 1A change in IOUT = (( ΔVOUT / VOUT(NOM) ) / ΔIOUT ) x 100% Dropout voltage (VDO) is defined as the differential voltage measured between VOUT and VIN when VIN, falling from VIN = VOUT + 1V, causes VOUT to drop 2% below the value measured with VIN = VOUT + 1V. Dropout voltage specification does not apply when the programmed output voltage is below the Minimum Operating Input Voltage. Ground pin current is the sum of the current in both GND pins (Pin 4 + Pin 5) only, and does not include current from the SET pin. 4 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of –40°C to +125°C. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Minimum and Maximum limits are specified through test, design, or statistical correlation. Unless otherwise stated the following conditions apply: VIN = 5.5 V, VSET = 5.0 V, CCP= 10 nF X7R, CIN = 10 μF 50 mΩ Tantalum, COUT = 10 μF X7R MLCC, IOUT = 10 mA, and TJ = 25°C. Symbol eN Parameter Output Noise Voltage (RMS) Conditions Min Typical Max Units VIN = 3.0 V, VOUT = 1.2 V COUT = 1 µF X7R BW = 10 Hz to 100 kHz - 4.96 - VIN = 3.0 V, VOUT = 1.2 V BW = 10 Hz to 100 kHz - 5.21 - VIN = 3.0 V, VOUT = 1.2 V BW = 10 Hz to 10 MHz - 11.53 - VIN = 6.0 V, VOUT = 5.0 V COUT = 1 µF X7R BW = 10 Hz to 100 kHz - 5.38 - VIN = 6.0 V, VOUT = 5.0 V BW = 10 Hz to 100 kHz - 5.43 - VIN = 6.0 V, VOUT = 5.0 V BW = 10 Hz to 10 MHz - 11.58 - 1.14 1.24 1.34 V µV(RMS) ENABLE INPUT VEN(ON) Enable ON Threshold Voltage VEN rising from 500 mV until Output is ON ΔVEN Enable Threshold Voltage VEN Falling from VEN(ON) Hysteresis - 110 - mV IEN(IL) EN Pin Pull-up Current VEN = 500 mV - 2 3.0 µA IEN(IH) EN Pin Pull-up Current VEN = 2.0 V - 2 3.0 µA Enable Pin Clamp Voltage EN pin = Open - 5.0 - V VEN(CLAMP) Thermal Shutdown TSD Thermal Shutdown Junction Temperature (TJ) Rising - 170 - ΔTSD Thermal Shutdown Hysteresis Junction Temperature (TJ) Falling from TSD - 12 - °C 5 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS 120 120 110 110 100 100 90 90 80 80 PSRR (dB) PSRR (dB) Unless otherwise specified: VIN = 5.5V, VOUT = 5.0 V, IOUT = 10 mA, COUT = 10 µF MLCC 16V X7R, TJ = 25°C. 70 60 10 mA 50 100 mA 40 20 VIN = 5.5 V VOUT = 5.0 V COUT = 10 µF MLCC 400 mA 10 60 10 mA 50 100 mA 40 200 mA 30 70 800 mA 30 200 mA 20 400 mA 10 0 800 mA 0 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 10 100 10k 100k 1M FREQUENCY (Hz) 10M C008 Figure 3. PSRR, VIN = 6.0 V, VOUT = 5.0 V 1 1 Cout = 1 µF Cout = 1 µF Cout = 10 µF Cout = 10 µF OUTPUT NOISE (µV¥Hz) OUTPUT NOISE (µV¥Hz) 1k C007 Figure 2. PSRR, VIN = 5.5V, VOUT = 5.0V 0.1 0.01 VIN = 3.0 V VOUT = 1.2 V IOUT = 500 mA 0.001 0.1 0.01 VIN = 6.0 V VOUT = 5.0 V IOUT = 500 mA 0.001 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 10 100 110 100 100 90 90 80 80 PSRR (dB) 120 70 VOUT = 5.0 V COUT = 10 µF MLCC IOUT = 10 mA 40 100k 1M 10M C010 Figure 5. Noise Density, VOUT = 5.0 V 110 50 10k FREQUENCY (Hz) 120 60 1k C009 Figure 4. Noise Density, VOUT = 1.2 V PSRR (dB) VIN = 6.0 V VOUT = 5.0 V COUT = 10 µF MLCC 70 VOUT = 5.0 V COUT = 10 µF MLCC IOUT = 100 mA 60 50 40 30 30 20 Vin = 5.5V 20 10 Vin = 6.0V 10 0 Vin = 5.5V Vin = 6.0V 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 10 100 Figure 6. PSRR, VOUT = 5.0 V, IOUT = 10 mA 1k 10k 100k 1M FREQUENCY (Hz) C001 10M C002 Figure 7. PSRR, VOUT = 5.0 V, IOUT = 100 mA 6 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) 120 120 110 110 100 100 90 90 80 80 PSRR (dB) PSRR (dB) Unless otherwise specified: VIN = 5.5V, VOUT = 5.0 V, IOUT = 10 mA, COUT = 10 µF MLCC 16V X7R, TJ = 25°C. 70 VOUT = 5.0 V COUT = 10 µF MLCC IOUT = 200 mA 60 50 40 70 VOUT = 5.0 V COUT = 10 µF MLCC IOUT = 400 mA 60 50 40 30 30 20 Vin = 5.5V 20 Vin = 5.5V 10 Vin = 6.0V 10 Vin = 6.0V 0 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 10 110 100 100 90 90 80 80 PSRR (dB) PSRR (dB) 120 110 70 VOUT = 5.0 V COUT = 10 µF MLCC IOUT = 800 mA 40 100k 1M 10M C004 70 VIN = 5.5 V VOUT = 5.0 V IOUT = 800 mA 60 50 40 30 30 20 20 Vin = 5.5V 10 Cout = 10 µF 10 Vin = 6.0V 0 Cout = 50 µF 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 10 100 1k 10k 100k 1M FREQUENCY (Hz) C005 Figure 10. PSRR, VOUT = 5.0 V, IOUT = 800 mA 10M C006 Figure 11. PSRR, VOUT = 5.0 V, IOUT= 800mA 3.0 1.40 2.9 Rising VIN (ON) 2.8 ENABLE THRESHOLDS (V) UVLO THRESHOLDS (V) 10k Figure 9. PSRR, VOUT = 5.0 V, IOUT = 400 mA 120 50 1k FREQUENCY (Hz) Figure 8. PSRR, VOUT = 5.0 V, IOUT = 200 mA 60 100 C003 2.7 2.6 2.5 2.4 2.3 Falling VIN (OFF) 2.2 1.35 Rising VEN (ON) 1.30 1.25 1.20 1.15 1.10 Falling VEN (OFF) 1.05 2.1 2.0 1.00 -50 -25 0 25 50 75 100 TEMPERATURE, TJ (ƒC) 125 -50 C023 Figure 12. UVLO Thresholds vs. TJ -25 0 25 50 75 100 TEMPERATURE, TJ (ƒC) 125 C024 Figure 13. Enable Thresholds vs. TJ 7 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VIN = 5.5V, VOUT = 5.0 V, IOUT = 10 mA, COUT = 10 µF MLCC 16V X7R, TJ = 25°C. 2.5 1.35 2.0 Rising VEN (ON) 1.30 VIN = 5.5 V VOUT = 1.2 V 1.5 1.25 VOLTS (V) ENABLE THRESHOLDS (V) 1.40 1.20 1.15 1.0 Ven 0.5 Vout 125ƒC 1.10 0.0 1.05 Vout 25ƒC Falling VEN (OFF) Vout -40ƒC 1.00 -0.5 0 2 4 6 8 10 12 14 16 18 TIME (50µs/DIV) 20 INPUT VOLTAGE, VIN (V) C025 C026 Figure 14. Enable Thresholds vs VIN Figure 15. Start-up Time, VOUT = 1.2 V 2.5 5.5 5.0 2.0 4.0 VIN = 5.5 V VOUT = 1.5 V 3.5 VOLTS (V) 1.5 VOLTS (V) VIN = 5.5 V VOUT = 5.0 V 4.5 1.0 Ven 0.5 0.0 2.5 2.0 Ven 1.5 Vout 125ƒC 1.0 Vout -40ƒC Vout 25ƒC 0.5 Vout 25ƒC 0.0 Vout -40ƒC -0.5 3.0 Vout 125ƒC -0.5 TIME (50µs/DIV) TIME (50µs/DIV) C027 C028 Figure 16. Start-up Time, VOUT = 1.5V Figure 17. Start-up Time, VOUT = 5.0 V 6.0 0.5 Vout = 5.0V 0.4 Vout = 3.3V Vout = 1.2V 4.0 VOUT (V) VIN = 5.5 V Normalized to TJ = 25ƒC 0.3 VFB VARIATION (%) 5.0 3.0 2.0 UVLO 0.2 0.1 0.0 -0.1 -0.2 -0.3 1.0 -0.4 0.0 -0.5 0.0 1.0 2.0 3.0 4.0 VIN (V) 5.0 6.0 -50 C038 Figure 18. VOUT vs. Rising VIN -25 0 25 50 75 TEMPERATURE, TJ (ƒC ) 100 125 C029 Figure 19. VFB Variation vs. TJ 8 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VIN = 5.5V, VOUT = 5.0 V, IOUT = 10 mA, COUT = 10 µF MLCC 16V X7R, TJ = 25°C. 20 5.5 5.0 VEN = 0.0V 16 4.5 14 4.0 VEN(CLAMP) (V) INPUT CURRENT, IIN (µA) 18 12 10 8 6 4 2 3.5 3.0 2.5 2.0 125ƒC 1.5 125ƒC 25ƒC 1.0 25ƒC 0.5 -40ƒC 0 -40ƒC 0.0 0 2 4 6 8 10 12 14 16 18 INPUT VOLTAGE, VIN (V) 20 0 2 4 6 8 10 12 14 16 18 INPUT VOLTAGE, VIN (V) C030 Figure 20. IN pin Current vs. VIN 20 C031 Figure 21. VEN(CLAMP) vs. VIN 3.0 350 DROPOUT VOLTAGE, VDO (mV) IEN(IL) PULL-UP CURRENT (µA) 125ƒC 2.5 2.0 1.5 1.0 125ƒC 0.5 25ƒC 300 25ƒC 250 -40ƒC 200 VOUT = 3.0V 150 100 50 -40ƒC 0.0 0 2 4 6 8 10 12 14 16 18 INPUT VOLTAGE, VIN (V) 0 0.01 20 Figure 22. Enable pin Pull-up Current vs VIN 1 C033 Figure 23. Dropout Voltage vs. Output Current 350 2.0 125ƒC 300 25ƒC 250 -40ƒC 200 VOUT = 5.0V VIN = 5.5 V VOUT = 5.0 V IOUT = 800 mA Normalized to 25ƒC 1.5 VOUT VARIATION (%) DROPOUT VOLTAGE, VDO (mV) 0.1 OUTPUT CURRENT (A) C032 150 100 50 1.0 0.5 0.0 -0.5 -1.0 -1.5 0 0.01 -2.0 0.1 1 OUTPUT CURRENT (A) -50 C034 Figure 24. Dropout Voltage vs. Output Current -25 0 25 50 75 TEMPERATURE, TJ (ƒC) 100 125 C035 Figure 25. VOUT Variation vs. TJ 9 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) 2.0 0.05 1.8 0.04 LINE REGULATION (%/V) LOAD REGULATION (%/A) Unless otherwise specified: VIN = 5.5V, VOUT = 5.0 V, IOUT = 10 mA, COUT = 10 µF MLCC 16V X7R, TJ = 25°C. 1.6 1.4 1.2 1.0 0.8 0.6 VIN = 5.5 V VOUT = 5.0 V ûIOUT = 10 mA to 800 mA 0.4 0.2 ûVIN = 5.5 V to 15 V VOUT = 5.0 V IOUT = 10 mA 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 -0.04 0.0 -0.05 -50 -25 0 25 50 75 100 TEMPERATURE, TJ (ƒC) 125 -50 -25 0 25 50 75 100 TEMPERATURE, TJ (ƒC) C036 Figure 26. Load Regulation vs. TJ 125 C037 Figure 27. Line Regulation vs. TJ 1.5 CURRENT LIMIT, ISC (A) 1.4 VIN 1V /DIV 1.3 VIN = 7.0 V VIN = 6.0 V VOUT = 5.0 V COUT = 10 µF IOUT = 800 mA 1.2 1.1 ûVOUT 1.0 ûVOUT 20 mV /DIV 0.9 0.8 -50 -25 0 25 50 75 100 TEMPERATURE (ƒC) C039 Figure 28. Current Limit, ISC vs. TJ VIN 1V /DIV TIME (500µs/DIV) 125 C022 Figure 29. Line Transient, VOUT = 5.0 V, IOUT = 800 mA VIN 1V /DIV VIN = 7.0V VIN = 7.0 V VIN = 6.0V VOUT = 5.0 V COUT = 10 µF IOUT = 400 mA VOUT = 5.0 V COUT = 10 µF IOUT = 10 mA ûVOUT ûVOUT 20 mV /DIV VIN = 6.0 V ûVOUT ûVOUT 20 mV /DIV TIME (500µs/DIV) TIME (500µs/DIV) C021 Figure 30. Line Transient, VOUT = 5.0 V, IOUT = 400 mA C020 Figure 31. Line Transient, VOUT = 5.0 V, IOUT = 10 mA 10 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VIN = 5.5V, VOUT = 5.0 V, IOUT = 10 mA, COUT = 10 µF MLCC 16V X7R, TJ = 25°C. VOUT = 1.2 V COUT = 10 µF IOUT = 800 mA VIN 1V /DIV VOUT = 1.2 V COUT = 10 µF IOUT = 400 mA VIN = 4.3 V VIN = 3.3 V VIN = 4.3 V VIN = 3.3 V VIN 1V /DIV ûVOUT ûVOUT ûVOUT 20 mV /DIV ûVOUT 20 mV /DIV TIME (500µs/DIV) TIME (500µs/DIV) C019 Figure 32. Line Transient, VOUT = 1.2 V, IOUT = 800 mA VOUT = 1.2 V COUT = 10 µF IOUT = 10 mA VIN 1V /DIV C018 Figure 33. Line Transient, VOUT = 1.2 V, IOUT= 400 mA IOUT 200 mA /DIV VIN = 4.3 V VIN = 3.3 V IOUT = 800 mA IOUT = 400 mA VIN = 5.5 V VOUT = 5.0 V COUT = 10 µF ûVOUT ûVOUT 20 mV /DIV ûVOUT 20 mV /DIV ûVOUT TIME (500µs/DIV) TIME (500µs/DIV) C017 Figure 34. Line Transient, VOUT = 1.2 V, IOUT= 10 mA IOUT 200 mA /DIV VIN = 5.5 V VOUT = 5.0 V COUT = 10 µF C016 Figure 35. Load Transient, VOUT = 5.0 V, IOUT = 400 mA to 800 mA IOUT 200 mA /DIV IOUT = 800 mA VIN = 5.5 V VOUT = 5.0 V COUT = 10 µF IOUT = 400 mA IOUT = 10 mA IOUT = 10 mA ûVOUT 20 mV /DIV ûVOUT 20 mV /DIV ûVOUT TIME (500µs/DIV) ûVOUT TIME (500µs/DIV) C015 Figure 36. Load Transient, VOUT = 5.0 V, IOUT = 10 mA to 800 mA C014 Figure 37. Load Transient, VOUT = 5.0 V, IOUT = 10 mA to 400 mA 11 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VIN = 5.5V, VOUT = 5.0 V, IOUT = 10 mA, COUT = 10 µF MLCC 16V X7R, TJ = 25°C. IOUT 200 mA /DIV IOUT 200 mA /DIV IOUT = 800 mA VIN = 3.3 V VOUT = 1.2 V COUT = 10 µF VIN = 3.3 V VOUT = 1.2 V COUT = 10 µF IOUT = 800 mA IOUT = 400 mA IOUT = 10 mA ûVOUT 20 mV /DIV ûVOUT 20 mV /DIV ûVOUT ûVOUT TIME (500µs/DIV) TIME (500µs/DIV) C013 Figure 38. Load Transient, VOUT = 1.2 V, IOUT = 400 mA to 800 mA IOUT 200 mA /DIV C012 Figure 39. Load Transient, VOUT = 1.2 V, IOUT = 10 mA to 800 mA VIN = 3.3 V VOUT = 1.2 V COUT = 10 µF IOUT = 400 mA IOUT = 10 mA ûVOUT 20 mV /DIV ûVOUT TIME (500µs/DIV) C011 Figure 40. Load Transient, VOUT = 1.2 V, IOUT= 10 mA to 400 mA 12 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 APPLICATIONS INFORMATION Functional Block Diagram LP38798SD-ADJ IN Active Ripple Rejection IN Current Limit OUT(FB) + - UVLO OUT PMOS 200 mV IN(CP) OUT Thermal Shutdown 98% Charge Pump 3.5 MHz tau= 2s CP SET IEN 2 PA 99.5% + - ISET 52 PA EN FB 5V 1.24V VREF 1.200V GND(CP) GND Package Information The LP38798-ADJ is available in the 12-Lead WSON surface mount package that allows for increased power dissipation compared to the standard PSOP-8 and WQFN-8 packages. External Capacitors Like any low-dropout regulator, the LP38798-ADJ requires external capacitors for regulator stability. These capacitors must be correctly selected for optimum performance. INPUT CAPACITOR: The minimum recommended input capacitance is 1 µF, ceramic or tantalum. However, if the LP38798 is operating in conditions where input ripple, fast changes in the input voltage, or large changes in the load current demand are expected, a minimum input capacitance of 10 µF is strongly recommended. Ceramic capacitor tolerance and variations due temperature and applied voltage must be considered when selecting a capacitor to assure the minimum input capacitance requirement is met over the intended operating range. The input capacitor must be located as close as physically possible to the input pin and returned to a clean analog ground. Any good quality tantalum capacitor may be used, while a ceramic capacitor should be X5R or X7R rated with appropriate adjustments due to the loss of capacitance value from the applied DC voltage. Larger input capacitance values are encouraged if fast output current steps are expected, as this will minimize voltage drops at the input pin. However, if there is any PCB trace inductance between the bulk supply and the input pin it is recommended that a tantalum capacitor be placed in parallel with the ceramic input capacitor. This will help to damp out undesired ringing that may occur during input transient conditions. 13 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com OUTPUT CAPACITOR: The LP38798 requires an output capacitance of at least 1 µF, ceramic or tantalum, however a minimum output capacitance of 10 µF is strongly recommended if fast load transient conditions are expected. While the LP38798 is designed to work with Ceramic output capacitors, the output capacitor can be Ceramic, Tantalum, or a combination. The total output capacitance should be sized appropriately to handle any fast load current steps. Capacitance type, tolerance, ESR, as well as temperature and voltage characteristics, must be considered when selecting an output capacitor for the application. Even though the LP38798 is stable with an output capacitance of 1 µF to 10 µF, a single output capacitor will generally not be able to provide the best PSRR performance across a wide frequency range. Multiple parallel capacitors, each with a different self-resonance frequency will provide better performance over a wider frequency range. The output capacitor must be located not more than 0.5" from the output pin and returned to a clean analog ground to the LP38798 GND pin. Charge Pump The charge pump is running when both the input voltage is above the UVLO threshold (2.65 V typical) and the EN pin voltage is above the VEN(ON) threshold (1.24 V typical). The typical charge pump operating frequency is 3.5 MHz. A low leakage 10 nF X7R storage capacitor is required between the CP pin and ground to store the energy required for gate drive of the internal NMOS pass device. Do not make any other connection to the CP pin. Loading this pin in any manner will degrade regulator performance. No external biasing may be applied to, or derived from, this pin, as permanent damage to the internal charge pump circuitry may occur. Programming the Output Voltage Current sourced from the SET pin, through R1 and R2, must be kept to less than 100 µA. The minimum allowed value for R2 is 12.9 kΩ; ISET = VFB / R2 R2MIN = VFB(MAX) / 100 μA R2MIN = 12.9 kΩ; (1) (2) (3) The values for R1 and R2 may be adjusted as needed to achieve the desired output voltage as long as the value for R2 is no less than 12.9 kΩ. The maximum recommended value for R2 is 100 kΩ. The following equation is used to determine the output voltage: VOUT = ( VFB x ( 1 + ( R1 / R2 ) ) ) + VOS (4) Alternately, the following formula can be used to determine the appropriate R1 value for a given R2 value: R1 = R2 x ( ( (VOUT) / VFB) – 1) (5) The following table suggests some ±1% values for R1 and R2 for a range of output voltages using the typical VFB value of 1.200V. This is not a definitive list, as other combinations exist that will provide similar, possibly better, performance. Target VOUT R1 R2 Typical VOUT 1.5 V 4.22 kΩ 16.9 kΩ 1.5 V 1.8 V 10.5 kΩ 21.0 kΩ 1.8 V 2.0 V 10.0 kΩ 15.0 kΩ 2.0 V 2.5 V 16.2 kΩ 15.0 kΩ 2.496 V 3.0 V 21.0 kΩ 14.0 kΩ 3.0 V 3.3 V 23.2 kΩ 13.3 kΩ 3.293 V 5.0 V 47.5 kΩ 15.0 kΩ 5.0 V 14 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 Noise Filter Any noise at LP38798 SET pin is reduced by an internal passive, first order low-pass RC filter before it is passed to the output buffer stage. The low-pass filter has a -3dB cut-off frequency of approximately 0.08Hz. To keep the low-pass filter from interfering with the output voltage rise time at start-up, a voltage comparator keeps the filter in a fast-charge mode while the output voltage (VOUT) is less than 99.5% of the SET pin voltage (VSET) . When the rising VOUT is within 0.5% of VSET the fast-charge mode ends, and VOUT will rise the final 0.5% based on the RC time constant (τ = 2s) of the filter. Should VOUT be more than 2% above the VSET voltage, a voltage comparator will put the filter into the fast-charge mode to allow the filter to discharge and VOUT to fall a value closer to VSET. When the falling VOUT is within 2% of VSET the fast-charge mode ends, and VOUT will fall the final 2% based on the RC time constant (τ = 2s) of the filter. If the input voltage has an extended rise time, the output voltage may exhibit a stair-case waveform as the fastcharge mode is activated and de-activated as VSET rises with VIN, and VOUT follows. Once the VIN has risen above the programmed VSET voltage, and VOUT is within 0.5% of VSET, the stair-case behavior will end. Enable Input Operation The Enable pin (EN) is pulled high internally by a 2 μA (typical) current source from the IN pin, and internally clamped at 5V (typical) by a zener. Pulling the EN pin low, by sinking the IEN current to ground, will turn the output off. If the EN function is not needed the EN pin should be left open (floating). Do not connect the EN pin directly to VIN if there is any possibility that VIN might exceed 5.5V (i.e. EN pin AbsMax). If external pull-up is required, the external current into the EN pin should be limited to no more than 10 μA. RPULL-UP > ( VPULL-UP - 5V) / 10 μA ) (6) Thermal Shutdown The LP38798 includes thermal protection that will shut-off the output current when activated by excessive device dissipation. Thermal shutdown (TSD) will occur when the junction temperature has risen to 170°C. The junction temperature must fall typically 12°C for the output current to be restored. Junction temperature is calculated from the following formula: TJ = (TA + ( PD x θJ-A)) (7) Where the power being dissipated, PD, is defined as: PD = ((VIN - VOUT) x IOUT) (8) Note that Thermal Shutdown is provided as a safety feature and is outside the specified Operating Ratings temperature range. Operation with a junction temperature (TJ) above 125°C is not recommended as the device behavior is not specified. 12-Lead WSON Package Thermal Considerations The value of θJ−A for the 12-lead WSON package is specifically dependent on PCB copper area, copper thickness, the number of layers, and thermal vias under the exposed thermal pad (DAP). Please refer to AN1520 (Literature Number: SNVA183A) for general guidelines for mounting packages with exposed thermal pads. Exceeding the maximum allowable power dissipation defined by the final θJ−A will cause excessive die temperature, and the regulator may go into thermal shutdown. Mounting the 12-lead WSON Package The 12-Lead WSON package requires specific mounting techniques that are detailed in Texas Instruments Application Note # 1187 (Literature Number: SNOA401Q). Referring to the section PCB Design Recommendations in AN-1187, it should be noted that the pad style that should be used with the WSON DNT0012B package is the NSMD (non-solder mask defined) type. Additionally, it is recommended the PCB terminal pads to be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection. 15 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 SNOSCT6A – MARCH 2013 – REVISED MAY 2013 www.ti.com The thermal dissipation of the 12-lead WSON package is directly related to the printed circuit board construction and the amount of additional copper area connected to the DAP. The DAP (exposed pad) on the bottom of the 12-lead WSON DNT0012B package is connected to the die substrate with a conductive die attach adhesive. The DAP has no direct electrical (wire) connection to any of the twelve pins. There is a parasitic PN junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be connected directly to the ground at device leads 6 and 7 (i.e. GND). Alternately, but not recommended, the DAP may be left floating (i.e. no electrical connection). The DAP must not be connected to any potential other than ground. For the LP38798SD in the 12-Lead WSON DNT0012B package, the junction-to-case thermal resistance rating, θJC, is 5°C/W, where the case is defined as being on the bottom of the package at the center of the DAP. The junction-to-ambient thermal performance, θJA, for the LP38798SD in the 12-lead WSON DNT0012B package, using the JEDEC JESD51 standards, is summarized in the following table: LP38798SD-ADJ (12-lead WSON DNT0012B) Thermal Performance Board Type Thermal Vias θJA ΨJB θJC JEDEC 2-Layer JESD 51-3 None 138°C/W 45.9°C/W 5°C/W 1 51°C/W 26.1°C/W 2 45°C/W 24.7°C/W 4 39°C/W 18.0°C/W 6 36°C/W 14.9°C/W 8 34°C/W 13.2°C/W JEDEC 4-Layer JESD 51-7 5°C/W Estimating the Junction Temperature The EIA/JEDEC standard (JESD51-2) provides methodologies to estimate the junction temperature from external measurements (ΨJB references the temperature at the PCB, and ΨJT references the temperature at the top surface of the package) when operating under steady-state power dissipation conditions. These methodologies have been determined to be relatively independent of the copper thermal spreading area that may be attached to the package DAP when compared to the more typical θJA. Refer to ' Application Report : Semiconductor and IC Package Thermal Metrics' , Literature Number SPRA953B, for specifics. Board Layout The dynamic performance of the LP38798 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDO's may degrade the PSRR, noise, or transient performance of the LP38798. Best performance is achieved by placing all of the components on the same side of the PCB as the LP38798, and as close as is practical to the LP38798 package. All component ground connections should be back to the LP38798 analog ground connection using as wide, and as short, of a copper trace as is practical. The connection from the FB pin to the VSET resistors must be as short as possible as the FB pin is a high impedance input. Any trace length on the FB pin will act as an antenna. Connections using long trace lengths, narrow trace widths, and connections through vias should be avoided. These will add parasitic inductances and resistance that results in inferior performance especially during transient conditions. A Ground Plane, either on the opposite side of a two-layer PCB, or embedded in a multi-layer PCB, is strongly recommended. This Ground Plane serves two purposes : 1) Provide a circuit reference plane to assure accuracy, and 2) provides a thermal plane to remove heat from the LP38798 through thermal vias under the package DAP. 16 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 LP38798 www.ti.com SNOSCT6A – MARCH 2013 – REVISED MAY 2013 Typical Applications 1 5.50V VIN 2 3 CIN 1 PF MLCC OUT IN OUT IN(CP) OUT(FB) 12 VOUT 11 5 6 CP SET EN FB + COUT 10 PF 9 (5.00V) 8 (1.20V) R1 47.5k R2 15.0k 7 GND(CP) 5.00V 10 LP38798 4 CCP 10 nF VEN IN GND DAP GND GND Figure 41. Typical Application, VOUT = 5.0V 1 5.50V VIN L1 10 PH 1 PF MLCC 2 + 3 CIN1 33 PF 50 m: Tant VEN CIN2 47 PF MLCC IN OUT IN OUT IN(CP) OUT(FB) 12 VOUT 11 10 + COUT 10 PF LP38798 4 CCP 10 nF 5 6 CP SET EN FB 9 (5.00V) 8 (1.20V) 7 GND(CP) GND 5.00V R1 47.5k R2 15.0k DAP GND GND Figure 42. Improving PSRR at High Frequencies 17 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LP38798 PACKAGE OPTION ADDENDUM www.ti.com 19-May-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) LP38798SD-ADJ/NOPB ACTIVE WSON DNT 12 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L00075B LP38798SDE-ADJ/NOPB ACTIVE WSON DNT 12 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L00075B LP38798SDX-ADJ/NOPB ACTIVE WSON DNT 12 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L00075B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 19-May-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LP38798SD-ADJ/NOPB WSON DNT 12 LP38798SDE-ADJ/NOPB WSON DNT LP38798SDX-ADJ/NOPB WSON DNT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 12 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 12 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP38798SD-ADJ/NOPB WSON DNT 12 1000 210.0 185.0 35.0 LP38798SDE-ADJ/NOPB WSON DNT 12 250 210.0 185.0 35.0 LP38798SDX-ADJ/NOPB WSON DNT 12 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DNT0012B WSON - 0.8mm max height SON (PLASTIC SMALL OUTLINE - NO LEAD) SDA12B (Rev A) 4214928/A 03/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to a thermal pad on the board for thermal and mechanical performance. For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271). www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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