LMZ10505
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SNVS633G – JANUARY 2010 – REVISED APRIL 2013
LMZ10505 5A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage
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FEATURES
1
•
•
2
•
•
•
•
•
Integrated Shielded Inductor
Flexible Startup Sequencing Using External
Soft-Start, Tracking, and Precision Enable
Protection Against In-Rush Currents and
Faults such as Input UVLO and Output ShortCircuit
-40°C to +125°C Junction Temperature
Operating Range
Single Exposed Pad and Standard Pinout for
Easy Mounting and Manufacturing
Pin-to-Pin Compatible with
– LMZ10503 (3A/15W max)
– LMZ10504 (4A/20W max)
Fully Enable for WEBENCH® and Power
Designer
ELECTRICAL SPECIFICATIONS
•
•
•
•
•
•
PERFORMANCE BENEFITS
•
•
•
•
APPLICATIONS
•
•
•
•
Point-of-Load Conversions from 3.3V and 5V
Rails
Space constrained applications
Extreme Temperatures/no Air Flow
Environments
Noise Sensitive Applications (i.e. Transceiver,
Medical)
25W Maximum Total Output Power
Up to 5A Output Current
Input Voltage Range 2.95V to 5.5V
Output Voltage Range 0.8V to 5V
±1.63% Feedback Voltage Accuracy Over
Temperature
Efficiency up to 96%
•
•
Operates at High Ambient Temperatures
High Efficiency up to 96% Reduces System
Heat Generation
Low Radiated Emissions (EMI) Complies with
EN55022 Class B Standard (2)
Passes 10V/m Radiated Immunity EMI Ttest
Standard EN61000 4-3
Low Output Voltage Ripple of 10 mV Allows
for Powering Noise-Sensitive Transceiver and
Signaling ICs
Fast Transient Response for Powering FPGAs
and ASICs
DESCRIPTION
The LMZ10505 SIMPLE SWITCHER® power module
is a complete, easy-to-use DC-DC solution capable of
driving up to a 5A load with exceptional power
conversion efficiency, output voltage accuracy, line
and load regulation. The LMZ10505 is available in an
innovative
package
that
enhances
thermal
performance and allows for hand or machine
soldering.
Figure 1. Easy to Use 7 Pin Package
PFM 7 Pin Package
10.16 x 13.77 x 4.57 mm (0.4 x 0.39 x 0.18 in)
θJA = 20°C/W, θJC = 1.9°C/W (1)
RoHS Compliant
(1)
θ JA measured on a 2.25” x 2.25” (5.8 cm x 5.8 cm) four layer
board, with one ounce copper, thirty six 10mil thermal vias, no
air flow, and 1W power dissipation. Refer to PCB Layout
Diagrams or Evaluation Board Application Note: AN-2022
(SNVA421).
(2)
EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007.
See Table 9 and layout for information on device under test.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LMZ10505
SNVS633G – JANUARY 2010 – REVISED APRIL 2013
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DESCRIPTION (CONTINUED)
The LMZ10505 can accept an input voltage rail between 2.95V and 5.5V and deliver an adjustable and
highly accurate output voltage as low as 0.8V. One megahertz fixed frequency PWM switching provides a
predictable EMI characteristic. Two external compensation components can be adjusted to set the fastest
response time, while allowing the option to use ceramic and/or electrolytic output capacitors. Externally
programmable soft-start capacitor facilitates controlled startup. The LMZ10505 is a reliable and robust
solution with the following features: lossless cycle-by-cycle peak current limit to protect for over current or
short-circuit fault, thermal shutdown, input under-voltage lock-out, and pre-biased startup.
System Performance
Figure 2. Current Derating (VOUT = 3.3V)
Figure 3. Efficiency (VOUT = 3.3V)
Figure 4. Radiated Emissions (EN 55022, Class B)
2
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Typical Application Circuit
VIN
VOUT
1
VIN
Cin
2
VOUT
6, 7
LMZ10505
FB
EN
SS
CO
5
GND
4, EP
3
Rfbt
CSS
Rcomp
Ccomp
Rfbb
Connection Diagram
Exposed Pad
Connect to GND
7
VOUT
6
VOUT
5
FB
4
GND
3
SS
2
EN
1
VIN
Figure 5. 7-Lead PFM - Top View
Package Number NDW0007A
PIN DESCRIPTIONS
Pin Number
Name
1
VIN
Power supply input. A low ESR input capacitance should be located as close as possible to the VIN pin and
exposed pad (EP).
Description
2
EN
Active high enable input for the device.
3
SS
Soft-start control pin. An internal 2 µA current source charges an external capacitor connected between SS
and GND pins to set the output voltage ramp rate during startup. The SS pin can also be used to configure
the tracking feature.
4
GND
Power ground and signal ground. Provide a direct connection to the EP. Place the bottom feedback resistor
as close as possible to GND and FB pin.
5
FB
Feedback pin. This is the inverting input of the error amplifier used for sensing the output voltage. Keep the
copper area of this node small.
6, 7
VOUT
The output terminal of the internal inductor. Connect the output filter capacitor between VOUT pin and EP.
EP
Exposed
Pad
Exposed pad is used as a thermal connection to remove heat from the device. Connect this pad to the PC
board ground plane in order to reduce thermal resistance value. EP must also provide a direct electrical
connection to the input and output capacitors ground terminals. Connect EP to pin 4.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2)
VIN, VOUT, EN, FB, SS to GND
-0.3V to 6.0V
ESD Susceptibility (3)
±2 kV
Power Dissipation
Internally Limited
Junction Temperature
150°C
Storage Temperature Range
-65°C to 150°C
Peak Reflow Case Temperature
(30 sec)
245°C
For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c
(1)
(2)
(3)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22-AI14S.
Operating Ratings (1)
VIN to GND
2.95V to 5.5V
Junction Temperature(TJ)
(1)
-40°C to 125°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C only; limits in bold face type apply over the operating junction
temperature range TJ of -40°C to 125°C. Minimum and maximum limits are ensured through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only. VIN = VEN = 3.3V, unless otherwise indicated in the conditions column.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
SYSTEM PARAMETERS
V FB
Total Feedback Voltage Variation
Including Line and Load Regulation
VIN = 2.95V to 5.5V
VOUT = 2.5V
IOUT = 0A to 5A
0.78
0.8
0.82
V
V FB
Feedback Voltage Variation
VIN = 3.3V, VOUT = 2.5V
IOUT = 0A
0.787
0.8
0.812
V
V FB
Feedback Voltage Variation
VIN = 3.3V, VOUT = 2.5V
IOUT = 5A
0.785
0.798
0.81
V
Input UVLO Threshold (Measured at VIN
pin)
Rising
2.6
2.95
V
ISS
Soft-Start Current
Charging Current
IQ
Non-Switching Input Current
VFB = 1V
1.55
3
mA
267
500
µA
7.3
8.7
A
VIN(UVLO)
Falling
ISD
Shut Down Quiescent Current
VIN = 5.5V, VEN = 0V
IOCL
Output Current Limit (Average Current)
VOUT = 2.5V
fFB
Frequency Fold-back
In current limit
1.95
2.4
2
5.1
µA
250
kHz
PWM SECTION
fSW
Drange
Switching Frequency
750
PWM Duty Cycle Range
1000
0
1160
kHz
100
%
1.8
V
ENABLE CONTROL
(1)
(2)
4
VEN-IH
EN Pin Rising Threshold
VEN-IF
EN Pin Falling Threshold
1.23
0.8
1.06
V
Min and Max limits are 100% production tested at an ambient temperature (TA) of 25°C. Limits over the operating temperature range are
ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality
Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ = 25°C only; limits in bold face type apply over the operating junction
temperature range TJ of -40°C to 125°C. Minimum and maximum limits are ensured through test, design, or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes
only. VIN = VEN = 3.3V, unless otherwise indicated in the conditions column.
Symbol
Parameter
Conditions
Min (1)
Typ (2)
Max (1)
Units
THERMAL CONTROL
TSD
TSD-HYS
TJ for Thermal Shutdown
145
°C
Hysteresis for Thermal Shutdown
10
°C
THERMAL RESISTANCE
θJA
Junction to Ambient
See (3)
20
°C/W
θJC
Junction to Case
No air flow
1.9
°C/W
Refer to Table 3
VOUT = 2.5V
Bandwidth Limit = 2 MHz
10
mVpk-
Output Voltage Ripple
Refer to Table 5
Bandwidth Limit = 20 MHz
5
Feedback Voltage Line Regulation
ΔVIN = 2.95V to 5.5V
IOUT = 0A
0.04
%
Output Voltage Line Regulation
ΔVIN = 2.95V to 5.5V
IOUT = 0A, VOUT = 2.5V
0.04
%
Feedback Voltage Load Regulation
IOUT = 0A to 5A
0.25
%
Output Voltage Load Regulation
IOUT = 0A to 5A
VOUT = 2.5V
0.25
%
Peak Efficiency (1A) VIN = 5V
VOUT = 3.3V
96.1
VOUT = 2.5V
94.8
VOUT = 1.8V
93.1
VOUT = 1.5V
92
VOUT = 1.2V
90.4
VOUT = 0.8V
86.8
VOUT = 2.5V
95.7
VOUT = 1.8V
94.1
VOUT = 1.5V
93.0
VOUT = 1.2V
91.6
VOUT = 0.8V
88.3
VOUT = 3.3V
93.1
VOUT = 2.5V
91.2
VOUT = 1.8V
88.5
VOUT = 1.5V
86.7
VOUT = 1.2V
84.1
VOUT = 0.8V
78.2
VOUT = 2.5V
89.8
VOUT = 1.8V
86.9
VOUT = 1.5V
85.1
VOUT = 1.2V
82.5
VOUT = 0.8V
76.2
PERFORMANCE PARAMETERS
ΔVOUT
ΔVOUT
ΔVFB / VFB
ΔVOUT / VOUT
ΔVFB / VFB
ΔVOUT / VOUT
Output Voltage Ripple
pk
mVpkpk
Efficiency
η
η
η
η
(3)
Peak Efficiency (1A) VIN = 3.3V
Full Load Efficiency (3A) VIN = 5V
Full Load Efficiency (3A) VIN = 3.3V
%
%
%
%
θ JA measured on a 2.25” x 2.25” (5.8 cm x 5.8 cm) four layer board, with one ounce copper, thirty six 10mil thermal vias, no air flow,
and 1W power dissipation. Refer to PCB Layout Diagrams or Evaluation Board Application Note: AN-2022 (SNVA421).
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Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VIN = VEN = 5.0V, CIN is 47 µF 10V X5R ceramic capacitor; TAMBIENT
= 25°C for efficiency curves and waveforms.
6
Load Transient Response
VIN = 3.3V, VOUT = 2.5V, IOUT = 0.5A to 4.5A to 0.5A step
20 MHz Bandwidth Limited
Refer to Table 5 for BOM, includes optional components
Load Transient Response
VIN = 5.0V, VOUT = 2.5V, IOUT = 0.5A to 4.5A to 0.5A step
20 MHz Bandwidth Limited
Refer to Table 5 for BOM, includes optional components
Figure 6.
Figure 7.
Output Voltage Ripple
VIN = 3.3V, VOUT = 2.5V, IOUT = 5A, 20 mV/DIV
Refer to Table 5 for BOM
Output Voltage Ripple
VIN = 5.0V, VOUT = 2.5V, IOUT = 5A, 20 mV/DIV
Refer to Table 5 for BOM
Figure 8.
Figure 9.
Efficiency
VOUT = 3.3V
Efficiency
VOUT = 2.5V
Figure 10.
Figure 11.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = VEN = 5.0V, CIN is 47 µF 10V X5R ceramic capacitor; TAMBIENT
= 25°C for efficiency curves and waveforms.
Efficiency
VOUT = 1.8V
Efficiency
VOUT = 1.5V
Figure 12.
Figure 13.
Efficiency
VOUT = 1.2V
Efficiency
VOUT = 0.8V
Figure 14.
Figure 15.
Current Derating
VIN = 5V, θJA = 20°C / W
Current Derating
VIN = 3.3V, θJA = 20°C / W
Figure 16.
Figure 17.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = VEN = 5.0V, CIN is 47 µF 10V X5R ceramic capacitor; TAMBIENT
= 25°C for efficiency curves and waveforms.
Radiated Emissions (EN 55022, Class B)
VIN = 5V, VOUT = 2.5V, IOUT = 5A
Evaluation Board
Startup
VOUT = 2.5V, IOUT = 0A
Figure 18.
Figure 19.
Pre-biased Startup
VOUT = 2.5V, IOUT = 0A
Figure 20.
8
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Block Diagram
DESIGN GUIDELINE AND OPERATING DESCRIPTION
Design Steps
LMZ10505 is fully supported by Webench® and offers the following: component selection, performance,
electrical, and thermal simulations as well as the Build-It board, for a reduced design time. On the other hand, all
external components can be calculated by following the design procedure below.
1. Determine the input voltage and output voltage. Also, make note of the ripple voltage and voltage transient
requirements.
2. Determine the necessary input and output capacitance.
3. Calculate the feedback resistor divider.
4. Select the optimized compensation component values.
5. Estimate the power dissipation and board thermal requirements.
6. Follow the PCB design guideline.
7. Learn about the LMZ10505 features such as enable, input UVLO, soft-start, tracking, pre-biased startup,
current limit, and thermal shutdown.
Design Example
For this example the following application parameters exist.
• VIN = 5V
• VOUT = 2.5V
• IOUT = 5A
• ΔVOUT = 20 mVpk-pk
• ΔVo_tran = ±20 mVpk-pk
Input Capacitor Selection
A 22 µF or 47 µF high quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum input voltage
is typically sufficient. The input capacitor must be placed as close as possible to the VIN pin and GND exposed
pad to substantially eliminate the parasitic effects of any stray inductance or resistance on the PC board and
supply lines.
Neglecting capacitor equivalent series resistance (ESR), the resultant input capacitor AC ripple voltage is a
triangular waveform. The minimum input capacitance for a given peak-to-peak value (ΔVIN) of VIN is specified as
follows:
Cin 8
IOUT x D x (1 - D)
fSW x 'VIN
(1)
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where the PWM duty cycle, D, is given by:
D=
VOUT
VIN
(2)
If ΔVIN is 1% of VIN, this equals to 50 mV and fSW = 1 MHz
2.5V
) x (1 - 2.5V)
5V
5V
8 25 µF
1 MHz x 50 mV
5A x (
Cin 8
(3)
A second criteria before finalizing the Cin bypass capacitor is the RMS current capability. The necessary RMS
current rating of the input capacitor to a buck regulator can be estimated by
ICin(RMS) = IOUT x D(1-D)
(4)
(5)
With this high AC current present in the input capacitor, the RMS current rating becomes an important
parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an
input capacitor rated for at least the maximum calculated ICin(RMS).
Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input
capacitance and parasitic inductance.
Output Capacitor Selection
In general, 22 µF to 100 µF high quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum
output voltage is sufficient given the optimal high frequency characteristics and low ESR of ceramic dielectrics.
Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density.
Two output capacitance equations are required to determine the minimum output capacitance. One equation
determines the output capacitance (CO) based on PWM ripple voltage. The second equation determines CO
based on the load transient characteristics. Select the largest capacitance value of the two.
The minimum capacitance, given the maximum output voltage ripple (ΔVOUT) requirement, is determined by the
following equation:
'COUT =
'iL
8 x fSW x ['VOUT ± ('iL x RESR)]
(6)
Where the peak to peak inductor current ripple (ΔiL) is equal to:
'iL =
(VIN - VOUT) x D
L x fSW
(7)
RESR is the total output capacitor ESR, L is the inductance value of the internal power inductor, where L = 1.5
µH, and fSW = 1 MHz. Therefore, per the design example:
2.5V
5V
= 833 mA
1.5 PH x 1 MHz
(5V ± 2.5V) x
'iL =
(8)
The minimum output capacitance requirement due to the PWM ripple voltage is:
(9)
(10)
Three miliohms is a typical RESR value for ceramic capacitors.
The following equation provides a good first pass capacitance requirement for a load transient:
Co t
Istep x VFB x L x VIN
4 x VOUT x (VIN -VOUT) x 'Vo_tran
(11)
Where Istep is the peak to peak load step (10% to 90% of the maximum load for this example), VFB = 0.8V, and
ΔVo_tran is the maximum output voltage deviation, which is ±20 mV.
Therefore the capacitance requirement for the given design parameters is:
10
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(12)
(13)
In this particular design the output capacitance is determined by the load transient requirements.
Table 1 lists some examples of commercially available capacitors that can be used with the LMZ10505.
Table 1. Recommended Output Filter Capacitors
CO (µF)
Voltage (V), RESR (mΩ)
Make
Manufacturer
Part Number
Case Size
22
6.3, < 5
Ceramic, X5R
TDK
C3216X5R0J226M
1206
47
6.3, < 5
Ceramic, X5R
TDK
C3216X5R0J476M
1206
47
6.3, < 5
Ceramic, X5R
TDK
C3225X5R0J476M
1210
47
10.0, < 5
Ceramic, X5R
TDK
C3225X5R1A476M
1210
100
6.3, < 5
Ceramic, X5R
TDK
C3225X5R0J107M
1210
100
6.3, 50
Tantalum
AVX
TPSD157M006#0050
D, 7.5 x 4.3 x 2.9 mm
100
6.3, 25
Organic Polymer
Sanyo
6TPE100MPB2
B2, 3.5 x 2.8 x 1.9 mm
150
6.3, 18
Organic Polymer
Sanyo
6TPE150MIC2
C2, 6.0 x 3.2 x 1.8 mm
330
6.3, 18
Organic Polymer
Sanyo
6TPE330MIL
D3L, 7.3 x 4.3 x 2.8 mm
470
6.3, 23
Niobium Oxide
AVX
NOME37M006#0023
E, 7.3 x 4.3 x 4.1 mm
Output Voltage Setting
A resistor divider network from VOUT to the FB pin determines the desired output voltage as follows:
VOUT = 0.8V x
Rfbt + Rfbb
Rfbb
(14)
Rfbt is defined based on the voltage loop requirements and Rfbb is then selected for the desired output voltage.
Resistors are normally selected as 0.5% or 1% tolerance. Higher accuracy resistors such as 0.1% are also
available.
The feedback voltage (at VOUT = 2.5V) is accurate to within -2.5% / +2.5% over temperature and over line and
load regulation. Additionally, the LMZ10505 contains error nulling circuitry to substantially eliminate the feedback
voltage variation over temperature as well as the long term aging effects of the internal amplifiers. In addition the
zero nulling circuit dramatically reduces the 1/f noise of the bandgap amplifier and reference. The manifestation
of this circuit action is that the duty cycle will have two slightly different but distinct operating points, each evident
every other switching cycle.
Loop Compensation
The LMZ10505 preserves flexibility by integrating the control components around the internal error amplifier while
utilizing three small external compensation components from VOUT to FB. An integrated type II (two pole, one
zero) voltage-mode compensation network is featured. To ensure stability, an external resistor and small value
capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole,
two zero) compensation network. The compensation components recommended in Table 2 provide type III
compensation at an optimal control loop performance. The typical phase margin is 45° with a bandwidth of 80
kHz. Calculated output capacitance values not listed in Table 2 should be verified before designing into
production. A detailed application note is available to provide verification support, AN-2013 (SNVA417). In
general, calculated output capacitance values below the suggested value will have reduced phase margin and
higher control loop bandwidth. Output capacitance values above the suggested values will experience a lower
bandwidth and increased phase margin. Higher bandwidth is associated with faster system response to sudden
changes such as load transients. Phase margin changes the characteristics of the response. Lower phase
margin is associated with underdamped ringing and higher phase margin is associated with overdamped
response. Losing all phase margin will cause the system to be unstable; an optimized area of operation is 30° to
60° of phase margin, with a bandwidth of 100 kHz ±20 kHz.
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Table 2. LMZ10505 Compensation Component Values
VIN (V)
CO (µF)
5.0
3.3
(1)
ESR (mΩ)
Rfbt (kΩ) (1)
Ccomp (pF) (1)
Rcomp (kΩ) (1)
Min
Max
22
2
20
200
27
1.5
47
2
20
124
56
1.4
100
1
10
82.5
120
1
150
1
5
63.4
180
1.21
150
10
25
63.4
220
16.5
150
26
50
44.2
220
23.7
220
15
30
63.4
220
23.7
220
31
60
76.8
220
57.6
22
2
20
118
39
9.09
47
2
20
76.8
82
8.45
100
1
10
49.9
180
4.12
150
1
5
40.2
330
2.0
150
10
25
43.2
330
11.5
150
26
50
49.9
270
25.5
220
15
30
40.2
390
15.4
220
31
60
48.7
330
35.7
In the special case where the output voltage is 0.8V, it is recommended to remove Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III
compensation.
Estimate Power Dissipation And Board Thermal Requirements
Use the current derating curves in the Typical Performance Characteristics section to obtain an estimate of
power loss (PIC_LOSS). For the design case of VIN = 5V, VOUT = 2.5V, IOUT = 5A, TA(MAX) = 85°C , and TJ(MAX) =
125°C, the device must see a thermal resistance from case to ambient (θCA) of less than:
TJ(MAX) - TA(MAX)
TCA <
PIC_LOSS
- TJC
(15)
(16)
Given the typical thermal resistance from junction to case (θJC) to be 1.9°C/W (typ.). Continuously operating at a
TJ greater than 125°C will have a shorten life span.
To reach θCA = 27.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat,
a good estimate of the required board area covered by 1oz. copper on both the top and bottom metal layers is:
2
Board Area_cm 8
500 . oC x cm2
TCA
W
(17)
(18)
As a result, approximately 18 square cm of 1oz. copper on top and bottom layers is required for the PCB design.
12
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The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 10mils (254
μm) thermal vias spaced 59mils (1.5 mm) apart must connect the top copper to the bottom copper. For an
extended discussion and formulations of thermal rules of thumb, refer to AN-2020 (SNVA419). For an example of
a high thermal performance PCB layout with θJA of 20°C/W, refer to the evaluation board application note AN2022 (SNVA421) and for results of a study of the effects of the PCB designs, refer to AN-2026 (SNVA424).
PC Board Layout Guidelines
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
VIN
LMZ10505
VIN
VOUT
VOUT
High dI
dt
Cin1
CO1
GND
Loop 1
Loop 2
Figure 21. High Current Loops
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current that
does not overlap contains high di/dt, see Figure 21. Therefore physically place input capacitor (Cin1) as close as
possible to the LMZ10505 VIN pin and GND exposed pad to avoid observable high frequency noise on the
output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the
input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad
(EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed only to the GND
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not
properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.
Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, Rfbt and Rfbb, and the compensation components, Rcomp and Ccomp, should be located
close to the FB pin. Since the FB node is high impedance, keep the copper area as small as possible. This is
most important as relatively high value resistors are used to set the output voltage.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer heatspreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 10mils (254 μm)
thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction
temperature below 125°C.
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Additional Features
ENABLE
The LMZ10505 features an enable (EN) pin and associated comparator to allow the user to easily sequence the
LMZ10505 from an external voltage rail, or to manually set the input UVLO threshold. The turn-on or rising
threshold and hysteresis for this comparator are typically 1.23V and 0.15V respectively. The precise reference for
the enable comparator allows the user to ensure that the LMZ10505 will be disabled when the system demands
it to be.
The EN pin should not be left floating. For always-on operation, connect EN to VIN.
ENABLE AND UVLO
Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the
part begins switching can be increased above the normal input UVLO level according to
VIN(UVLO) = 1.23V x
Rtrkb + Rtrkt
Rtrkt
(19)
For example, suppose that the required input UVLO level is 3.69V. Choosing Renb = 10 kΩ, then we calculate
Rent = 20 kΩ.
VIN
VIN
LMZ10505
Rent
Cin1
EN
Renb
GND
Alternatively, the EN pin can be driven from another voltage source to cater to system sequencing requirements
commonly found in FPGA and other multi-rail applications. The following schematic shows an LMZ10505 that is
sequenced to start based on the voltage level of a master system rail (VOUT1).
Master Power Supply
VOUT1
VIN
VIN
VOUT2
VOUT
Rent
Cin1
LMZ10505
CO1
EN
Renb
GND
SOFT-START
The LMZ10505 begins to operate when both the VIN and EN, voltages exceed the rising UVLO and enable
thresholds, respectively. A controlled soft-start eliminates inrush currents during startup and allows the user more
control and flexibility when sequencing the LMZ10505 with other power supplies.
In the event of either VIN or EN decreasing below the falling UVLO or enable threshold respectively, the voltage
on the soft-start pin is collapsed by discharging the soft-start capacitor by a 14 µA (typ.) current sink to ground.
SOFT-START CAPACITOR
Determine the soft-start capacitance with the following relationship
CSS =
14
tSS x ISS
VREF
(20)
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where VFB is the internal reference voltage (nominally 0.8V), ISS is the soft-start charging current (nominally 2 µA)
and CSS is the external soft-start capacitance.
Thus, the required soft-start capacitor per unit output voltage startup time is given by
CSS = 2.5 nF / ms
(21)
For example, a 4 ms soft-start time will yield a 10 nF capacitance. The minimum soft-start capacitance is 680 pF.
TRACKING
The LMZ10505 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS pin. In this way, the output voltage slew rate of the LMZ10505 will be controlled by a master supply for
loads that require precise sequencing. When the tracking function is used, a small value soft-start capacitor
should be connected to the SS pin to alleviate output voltage overshoot when recovering from a current limit
fault.
Master Power
Supply
VOUT1
VIN
VIN
VOUT2
VOUT
Rtrkt
Cin1
EN
LMZ10505
CO1
SS
VSS
Rtrkb
GND
TRACKING - EQUAL SOFT-START TIME
One way to use the tracking feature is to design the tracking resistor divider so that the master supply output
voltage, VOUT1, and the LMZ10505 output voltage, VOUT2, both rise together and reach their target values at the
same time. This is termed ratiometric startup. For this case, the equation governing the values of tracking divider
resistors Rtrkb and Rtrkt is given by
Rtrkb =
Rtrkt
VOUT1 -1.0V
(22)
The above equation includes an offset voltage, of 200 mV, to ensure that the final value of the SS pin voltage
exceeds the reference voltage of the LMZ10505. This offset will cause the LMZ10505 output voltage to reach
regulation slightly before the master supply. A value of 33 kΩ 1% is recommended for Rtrkt as a compromise
between high precision and low quiescent current through the divider while minimizing the effect of the 2 µA softstart current source.
For example, if the master supply voltage VOUT1 is 3.3V and the LMZ10505 output voltage was 1.8V, then the
value of Rtrkb needed to give the two supplies identical soft-start times would be 14.3 kΩ. A timing diagram for
this example, the equal soft-start time case, is shown below.
RATIOMETRIC STARTUP
VOUT1
VOLTAGE
VOUT2
EN
TIME
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TRACKING - EQUAL SLEW RATES
Alternatively, the tracking feature can be used to have similar output voltage ramp rates. This is referred to as
simultaneous startup. In this case, the tracking resistors can be determined based on the following equation
Rtrkb =
0.8V
x Rtrkt
VOUT2 - 0.8V
(23)
and to ensure proper overdrive of the SS pin
VOUT2 < 0.8 x V OUT1
(24)
For the example case of VOUT1 = 5V and VOUT2 = 2.5V, with Rtrkt set to 33 kΩ as before, Rtrkb is calculated from
the above equation to be 15.5 kΩ. A timing diagram for the case of equal slew rates is shown below.
SIMULTANEOUS STARTUP
VOUT1
VOLTAGE
VOUT2
EN
TIME
PRE-BIAS STARTUP CAPABILITY
At startup, the LMZ10505 is in a pre-biased state when the output voltage is greater than zero. This often occurs
in many multi-rail applications such as when powering an ASIC, FPGA, or DSP. The output can be pre-biased in
these applications through parasitic conduction paths from one supply rail to another. Even though the
LMZ10505 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. The
LMZ10505 will not sink current during startup until the soft-start voltage exceeds the voltage on the FB pin. Since
the device does not sink current it protects the load from damage that might otherwise occur if current is
conducted through the parasitic paths of the load.
CURRENT LIMIT
When a current greater than the output current limit (IOCL) is sensed, the on-time is immediately terminated and
the low side MOSFET is activated. The low side MOSFET stays on for the entire next four switching cycles.
During these skipped pulses, the voltage on the soft-start pin is reduced by discharging the soft-start capacitor by
a current sink on the soft-start pin of nominally 14 µA. Subsequent over-current events will drain more and more
charge from the soft-start capacitor, effectively decreasing the reference voltage as the output droops due to the
pulse skipping. Reactivation of the soft-start circuitry ensures that when the over-current situation is removed, the
part will resume normal operation smoothly.
OVER-TEMPERATURE PROTECTION
When the LMZ10505 senses a junction temperature greater than 145°C (typ.), both switching MOSFETs are
turned off and the part enters a standby state. Upon sensing a junction temperature below 135°C (typ.), the part
will re-initiate the soft-start sequence and begin switching once again.
LMZ10505 Application Circuit Schematic and BOMs
This section provides several application solutions with an associated bill of materials. The compensation for
each solution was optimized to work over the full input range. Many applications have a fixed input voltage rail. It
is possible to modify the compensation to obtain a faster transient response for a given input voltage operating
point.
16
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U1
VIN
1
2
VOUT
6, 7
VOUT
VIN
CO1
LMZ10505
EN
5
FB
Cin1
SS
3
GND
4, EP
Rfbt
CSS
Rcomp
Ccomp
Rfbb
Figure 22.
Table 3. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 5A,
Optimized for Electrolytic Input and Output Capacitance
Designator
Description
Case Size
Manufacturer
Manufacturer P/N
Quantity
U1
SIMPLE SWITCHER ®
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1
150 µF, 6.3V, 18 mΩ
C2, 6.0 x 3.2 x 1.8 mm
Sanyo
6TPE150MIC2
1
CO1
330 µF, 6.3V, 18 mΩ
D3L, 7.3 x 4.3 x 2.8
mm
Sanyo
6TPE330MIL
1
Rfbt
100 kΩ
0603
Vishay Dale
CRCW0603100KFKEA
1
Rfbb
47.5 kΩ
0603
Vishay Dale
CRCW060347K5FKEA
1
Rcomp
15 kΩ
0603
Vishay Dale
CRCW060315K0FKEA
1
Ccomp
330 pF, ±5%, C0G, 50V
0603
TDK
C1608C0G1H331J
1
CSS
10 nF, ±10%, X7R, 16V
0603
Murata
GRM188R71C103KA01
1
Table 4. Bill of Materials, VIN = 3.3V, VOUT = 0.8V, IOUT (MAX) = 5A,
Optimized for Solution Size and Transient Response
Designator
Description
Case Size
Manufacturer
Manufacturer P/N
Quantity
U1
SIMPLE SWITCHER ®
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1, CO1
47 µF, X5R, 6.3V
1206
TDK
C3216X5R0J476M
2
Rfbt
110 kΩ
0402
Vishay Dale
CRCW0402100KFKED
1
Rcomp
1.0 kΩ
0402
Vishay Dale
CRCW04021K00FKED
1
Ccomp
27 pF, ±5%, C0G, 50V
0402
Murata
GRM1555C1H270JZ01
1
CSS
10 nF, ±10%, X7R, 16V
0402
Murata
GRM155R71C103KA01
1
U1
Optional
VIN
1
2
Cin2
+
VOUT
VIN
EN
CO1
LMZ10505
Cin1
Ccomp
FB
Optional
5
CO2
CO3
Rfbt
GND
4, EP
SS
3
VOUT
6, 7
Rcomp
CSS
Rfbb
Figure 23.
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Table 5. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 5A,
Optimized for Low Input and Output Ripple Voltage and Fast Transient Response
Designator
Description
Case Size
Manufacturer
Manufacturer P/N
Quantity
1
U1
SIMPLE SWITCHER®
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
Cin1
22 µF, X5R, 10V
1210
AVX
1210ZD226MAT
2
Cin2
220 µF, 10V, AL-Elec
E
Panasonic
EEE1AA221AP
1*
CO1
4.7 µF, X5R, 10V
0805
AVX
0805ZD475MAT
1*
CO2
22 µF, X5R, 6.3V
1206
AVX
12066D226MAT
1*
CO3
100 µF, X5R, 6.3V
1812
AVX
18126D107MAT
1
Rfbt
75 kΩ
0402
Vishay Dale
CRCW040275K0FKED
1
Rfbb
34.8 kΩ
0402
Vishay Dale
CRCW040234K8FKED
1
Rcomp
1.0 kΩ
0402
Vishay Dale
CRCW04021K00FKED
1
Ccomp
100 pF, ±5%, C0G, 50V
0402
Murata
GRM1555C1H101JZ01
1
CSS
10 nF, ±10%, X7R, 16V
0402
Murata
GRM155R71C103KA01
1
Table 6. Output Voltage Setting (Rfbt = 75 kΩ)
VOUT
Rfbb
2.5 V
34.8 kΩ
1.8 V
59 kΩ
1.5 V
84.5 kΩ
1.2 V
150 kΩ
0.9 V
590 kΩ
U1
VIN
1
VOUT
VIN
+
Cin4
Cin3
Cin2
Cin1
CO1
LMZ10505
Ren1
Cin5
VOUT
6, 7
2
FB
EN
SS
3
CO2
CO3
5
GND
4, EP
Rfbt
CSS
Rcomp
3
Ccomp
Rfbb
Figure 24.
18
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Table 7. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 5A
Designator
Description
Case Size
Manufacturer
Manufacturer P/N
Quantity
U1
SIMPLE SWITCHER®
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1
1 µF, X7R, 16V
0805
TDK
C2012X7R1C105K
1
Cin2, CO1
4.7 µF, X5R, 6.3V
0805
TDK
C2012X5R0J475K
2
Cin3, CO2
22 µF, X5R, 16V
1210
TDK
C3225X5R1C226M
2
Cin4
47 µF, X5R, 6.3V
1210
TDK
C3225X5R0J476M
1
Cin5
220 µF, 10V, AL-Elec
E
Panasonic
EEE1AA221AP
1
CO3
100 µF, X5R, 6.3V
1812
TDK
C4532X5R0J107M
1
Rfbt
75 kΩ
0805
Vishay Dale
CRCW080575K0FKEA
1
Rfbb
34.8 kΩ
0805
Vishay Dale
CRCW080534K8FKEA
1
Rcomp
1.1 kΩ
0805
Vishay Dale
CRCW08051K10FKEA
1
Ccomp
180 pF, ±5%, C0G, 50V
0603
TDK
C1608C0G1H181J
1
Ren1
100 kΩ
0805
Vishay Dale
CRCW0805100KFKEA
1
CSS
10 nF, ±5%, C0G, 50V
0805
TDK
C2012C0G1H103J
1
Table 8. Output Voltage Setting (Rfbt = 75 kΩ)
VOUT
Rfbb
2.5 V
34.8 kΩ
1.8 V
59 kΩ
1.5 V
84.5 kΩ
1.2 V
150 kΩ
0.9 V
590 kΩ
Figure 25.
Table 9. Bill of Materials, VIN = 5V, VOUT = 2.5V, IOUT (MAX) = 5A,
Complies with EN55022 Class B Radiated Emissions
Designator
Description
Case Size
Manufacturer
Manufacturer P/N
Quantity
U1
SIMPLE SWITCHER®
PFM-7
Texas Instruments
LMZ10505TZ-ADJ
1
Cin1
1 µF, X7R, 16V
0805
TDK
C2012X7R1C105K
1
Cin2
4.7 µF, X5R, 6.3V
0805
TDK
C2012X5R0J475K
1
Cin3
47 µF, X5R, 6.3V
1210
TDK
C3225X5R0J476M
1
CO1
100 µF, X5R, 6.3V
1812
TDK
C4532X5R0J107M
1
Rfbt
75 kΩ
0805
Vishay Dale
CRCW080575K0FKEA
1
Rfbb
34.8 kΩ
0805
Vishay Dale
CRCW080534K8FKEA
1
Rcomp
1.1 kΩ
0805
Vishay Dale
CRCW08051K10FKEA
1
Ccomp
180 pF, ±5%, C0G, 50V
0603
TDK
C1608C0G1H181J
1
CSS
10 nF, ±5%, C0G, 50V
0805
TDK
C2012C0G1H103J
1
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Table 10. Output Voltage Setting (Rfbt = 75 kΩ)
VOUT
Rfbb
3.3 V
23.7 kΩ
2.5 V
34.8 kΩ
1.8 V
59 kΩ
1.5 V
84.5 kΩ
1.2 V
150 kΩ
0.9 V
590 kΩ
PCB Layout Diagrams
The PCB design is available in the LMZ10505 product folder at www.ti.com.
Figure 26. Top Copper
Figure 27. Internal Layer 1 (Ground)
20
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Figure 28. Internal Layer 2 (Ground and Signal Traces)
Figure 29. Bottom Copper
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REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
•
22
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 21
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LMZ10505TZ-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 85
LMZ10505
TZ-ADJ
LMZ10505TZE-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
45
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 85
LMZ10505
TZ-ADJ
LMZ10505TZX-ADJ/NOPB
ACTIVE
TO-PMOD
NDW
7
500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 85
LMZ10505
TZ-ADJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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16-Aug-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMZ10505TZ-ADJ/NOPB
LMZ10505TZX-ADJ/NOP
B
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TOPMOD
NDW
7
250
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
TOPMOD
NDW
7
500
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ10505TZ-ADJ/NOPB
TO-PMOD
NDW
7
250
367.0
367.0
45.0
LMZ10505TZX-ADJ/NOPB
TO-PMOD
NDW
7
500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
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