CSD25481F4 SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 CSD25481F4, 20 V P-Channel FemtoFET™ MOSFET 1 Features • • • • 1 • • • • . Product Summary Ultra-Low On Resistance Ultra-Low Qg and Qgd High Operating Drain Current Ultra-Small Footprint (0402 Case Size) – 1.0 mm x 0.6 mm Ultra-Low Profile – 0.35 mm Max Height Integrated ESD Protection Diode – Rated > 4 kV HBM – Rated > 2 kV CDM Lead and Halogen Free RoHS Compliant VDS Drain-to-Source Voltage –20 V Qg Gate Charge Total (–4.5 V) 913 pC Qgd Gate Charge Gate to Drain RDS(on) VGS(th) • • Drain-to-Source On Resistance pC 395 mΩ VGS = –2.5 V 145 mΩ VGS = –4.5 V 90 mΩ Threshold Voltage –0.95 V Ordering Information Device CSD25481F4 CSD25481F4T 2 Applications • • 153 VGS = –1.8 V Qty Media 3000 7-Inch Reel 250 7-Inch Reel Package Ship Femto(0402) 1.0 mm x 0.6 mm Land Grid Array (LGA) Tape and Reel Absolute Maximum Ratings TA = 25°C unless otherwise stated Optimized for Load Switch Applications Optimized for General Purpose Switching Applications Battery Applications Handheld and Mobile Applications VALUE UNIT VDS Drain-to-Source Voltage –20 V VGS Gate-to-Source Voltage –12 V ID Continuous Drain Current(1) –2.5 A IDM Pulsed Drain Current(2) –10 A Continuous Gate Clamp Current –35 Pulsed Gate Clamp Current(2) –350 Power Dissipation(1) 500 mW 4 kV 2 kV –55 to 150 °C IG 3 Description This 90 mΩ, 20 V P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing at least a 60% reduction in footprint size. . PD Human Body Model (HBM) ESD Rating Charged Device Model (CDM) TJ, TSTG Operating Junction and Storage Temperature Range mA (1) Typical RθJA = 85°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤ 300 μs, duty cycle ≤ 2% Top View Typical Part Dimensions m D 60 1. 0. 00 m m 5m 0.3 m m G S . 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD25481F4 SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 4 Specifications 4.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –100 nA –50 nA Static Characteristics BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = –250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = –16 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –12 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = –250 μA RDS(on) gfs Drain-to-Source On Resistance Transconductance –20 –0.70 V –0.95 –1.20 VGS = –1.8 V, IDS = –0.1 A 395 800 mΩ V VGS = –2.5 V, IDS = –0.5 A 145 174 mΩ VGS = –4.5 V, IDS = –0.5 A 90 105 mΩ VGS = –8 V, IDS = –0.5 A 75 88 mΩ VDS = –10 V, IDS = –0.5 A 3.3 S 189 pF 78 pF pF Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance 5.5 RG Series Gate Resistance 20 Ω Qg Gate Charge Total (4.5 V) 913 pC Qgd Gate Charge Gate to Drain 153 pC Qgs Gate Charge Gate to Source 240 pC Qg(th) Gate Charge at Vth 116 pC Qoss Output Charge 1030 pC td(on) Turn On Delay Time 4.1 ns tr Rise Time 3.6 ns td(off) Turn Off Delay Time 16.9 ns tf Fall Time 6.7 ns –0.75 V 1010 pC 7.5 ns VGS = 0 V, VDS = –10 V, f = 1 MHz VDS = –10 V, IDS = –0.5 A VDS = –10 V, VGS = 0 V VDS = 0 V, VGS = –4.5 V, IDS = –0.5 A,RG = 2 Ω Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = –0.5 A, VGS = 0 V VDS= –10 V, IF = –0.5 A, di/dt = 100 A/μs 4.2 Thermal Characteristics (TA = 25°C unless otherwise stated) PARAMETER RθJA (1) (2) 2 Junction-to-Ambient Thermal Resistance Typical Values (1) Junction-to-Ambient Thermal Resistance (2) 2 UNIT 85 °C/W 245 °C/W 2 Device mounted on FR4 material with 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 5 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 10 VGS = −8V VGS = −4.5V VGS = −2.5V VGS = −1.8V 9 8 7 − IDS - Drain-to-Source Current (A) − IDS - Drain-to-Source Current (A) 10 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 − VDS - Drain-to-Source Voltage (V) 1.8 2 VDS = −5V 9 8 7 6 5 4 3 TC = 125°C TC = 25°C TC = −55°C 2 1 0 0 G001 Figure 2. Saturation Characteristics 0.5 1 1.5 2 2.5 3 − VGS - Gate-to-Source Voltage (V) 3.5 Product Folder Links: CSD25481F4 G001 Figure 3. Transfer Characteristics Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated 4 3 CSD25481F4 SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 200 ID = −0.5A VDS = −10V 7 180 160 6 C − Capacitance (nF) − VGS - Gate-to-Source Voltage (V) 8 5 4 3 2 120 100 80 60 40 1 0 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 140 20 0 0.2 0.4 0.6 0.8 1 1.2 Qg - Gate Charge (nC) 1.4 0 1.6 0 2 4 6 8 10 12 14 16 − VDS - Drain-to-Source Voltage (V) G001 Figure 4. Gate Charge RDS(on) - On-State Resistance (mΩ) − VGS(th) - Threshold Voltage (V) G001 400 ID = −250uA 1.15 1.05 0.95 0.85 0.75 0.65 0.55 0.45 −75 −25 25 75 125 TC - Case Temperature (ºC) 320 280 240 200 160 120 80 40 0 2 G001 4 6 8 10 − VGS - Gate-to- Source Voltage (V) 12 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage 1.4 10 − ISD − Source-to-Drain Current (A) VGS = −4.5V, ID = −0.5A 1.3 1.2 1.1 1 0.9 0.8 0.7 −75 TC = 25°C, I D = −0.5A TC = 125°C, I D = −0.5A 360 0 175 Figure 6. Threshold Voltage vs Temperature Normalized On-State Resistance 20 Figure 5. Capacitance 1.25 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 − VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs Temperature 4 18 1 G001 Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 4.0 1ms 10ms 100ms 1s DC − IDS - Drain- to- Source Current (A) − IDS - Drain-to-Source Current (A) 100 10 1 0.1 Single Pulse Typical RthetaJA =245ºC/W(min Cu) 0.01 0.01 0.1 1 10 − VDS - Drain-to-Source Voltage (V) Figure 10. Maximum Safe Operating Area 50 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Typical RthetaJA = 85ºC/W(max Cu) 0.0 −50 G001 −25 0 25 50 75 100 125 TA - AmbientTemperature (ºC) 150 175 G001 Figure 11. Maximum Drain Current vs Temperature Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD25481F4 5 CSD25481F4 SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 www.ti.com 6 Mechanical Data 6.1 0402 Mechanical Dimensions (1) All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). (2) This drawing is subject to change without notice. (3) This package is a PB-free solder land design. Pin Configuration Position 6 Designation Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 6.2 Recommended Minimum PCB Layout (1) All dimensions are in millimeters. 6.3 Recommended Stencil Pattern (1) All dimensions are in millimeters. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD25481F4 7 CSD25481F4 SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 www.ti.com 6.4 CSD25481F4 Embossed Carrier Tape Dimensions (1) 8 Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket holes. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420B – SEPTEMBER 2013 – REVISED FEBRUARY 2014 7 Trademarks FemtoFET is a trademark of Texas Instruments. 8 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2013) to Revision B Page • Added Part Number to Title ................................................................................................................................................... 1 • Updated lead and halogen free in features ........................................................................................................................... 1 • Added IG parameter ............................................................................................................................................................... 1 • Lowered IDSS limit .................................................................................................................................................................. 2 • Lowered IGSS limit .................................................................................................................................................................. 2 Changes from Original (September 2013) to Revision A Page • Updated title .......................................................................................................................................................................... 1 • Took out jumbo reel info and added small reel info .............................................................................................................. 1 • Removed UIS graph .............................................................................................................................................................. 4 • Corrected device name ......................................................................................................................................................... 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD25481F4 9 PACKAGE OPTION ADDENDUM www.ti.com 30-Jan-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD25481F4 ACTIVE PICOSTAR YJC 3 3000 Green (RoHS & no Sb/Br) Call TI Level-1-250C-UNLIM -40 to 85 CSD25481F4R PREVIEW PICOSTAR YJC 3 18000 TBD Call TI Call TI -40 to 85 CS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD25481F4 Package Package Pins Type Drawing SPQ PICOST AR 3000 YJC 3 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 8.4 Pack Materials-Page 1 0.7 B0 (mm) K0 (mm) P1 (mm) 1.1 0.46 4.0 W Pin1 (mm) Quadrant 8.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD25481F4 PICOSTAR YJC 3 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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