LM5113 5A, 100V Half-Bridge Gate Driver for

LM5113
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SNVS725F – JUNE 2011 – REVISED APRIL 2013
LM5113 5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs
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FEATURES
1
•
2
•
•
•
•
•
•
•
•
•
Independent High-Side and Low-Side TTL
Logic Inputs
1.2A/5A Peak Source/Sink Current
High-Side Floating Bias Voltage Rail Operates
up to 100VDC
Internal Bootstrap Supply Voltage Clamping
Split Outputs for Adjustable Turn-on/Turn-off
Strength
0.6Ω /2.1Ω Pull-down/Pull-up Resistance
Fast Propagation Times (28ns Typical)
Excellent Propagation Delay Matching (1.5ns
Typical)
Supply Rail Under-Voltage Lockout
Low Power Consumption
TYPICAL APPLICATIONS
•
•
•
•
•
Current Fed Push-Pull converters
Half and Full-Bridge converters
Synchronous Buck converters
Two-switch Forward converters
Forward with Active Clamp converters
DESCRIPTION
The LM5113 is designed to drive both the high-side
and the low-side enhancement mode Gallium Nitride
(GaN) FETs in a synchronous buck or a half bridge
configuration. The floating high-side driver is capable
of driving a high-side enhancement mode GaN FET
operating up to 100V. The high-side bias voltage is
generated using a bootstrap technique and is
internally clamped at 5.2V, which prevents the gate
voltage from exceeding the maximum gate-source
voltage rating of enhancement mode GaN FETs. The
inputs of the LM5113 are TTL logic compatible, and
can withstand input voltages up to 14V regardless of
the VDD voltage. The LM5113 has split gate outputs,
providing flexibility to adjust the turn-on and turn-off
strength independently.
In addition, the strong sink capability of the LM5113
maintains the gate in the low state, preventing
unintended turn-on during switching. The LM5113
can operate up to several MHz. The LM5113 is
available in a standard WSON-10 pin package and a
12-bump DSBGA package. The WSON-10 pin
package contains an exposed pad to aid power
dissipation. The DSBGA package offers a compact
footprint and minimized package inductance.
PACKAGES
•
•
WSON-10 (4 mm x 4 mm)
DSBGA (2 mm x 2 mm)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LM5113
SNVS725F – JUNE 2011 – REVISED APRIL 2013
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Typical Application
HB
UVLO
& CLAMP
HOH
LEVEL
SHIFT
HOL
HS
HI
VDD
UVLO
LOH
LOL
LI
VSS
Figure 1.
Truth Table
2
HI
LI
HOH
HOL
LOH
L
L
Open
L
Open
L
L
H
Open
L
H
Open
H
L
H
Open
Open
L
H
H
H
Open
H
Open
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LOL
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Connection Diagram
VDD
1
10
LOH
HB
2
9
LOL
HOH
3
8
VSS
HOL
4
7
LI
HS
5
6
HI
Exposed Pad
Figure 2. WSON Package
Package Number DPR0010A
A
LOL
B
LOL
A
HI
LOH
B
VDD
VDD
HS
C
HB
HS
HS
HB
HOH
HOL
D
3
4
4
3
2
1
LI
LI
LOH
HI
C
HS
D
HOL
HOH
1
2
VSS
VDD
VDD
VSS
Bump Side
Top View
DSBGA Package
Package Number YFX0012FLA
PIN DESCRIPTIONS
Pin Number
(1)
Name
DSBGA
WSON-10
A3, C4 (1)
1
VDD
D3
2
HB
D2
3
D1
Description
Applications Information
5V Positive gate drive supply
Locally decouple to VSS using low ESR/ESL
capacitor located as close to the IC as possible.
High-side gate driver bootstrap
rail
Connect the positive terminal of the bootstrap
capacitor to HB and the negative terminal to HS.
The bootstrap capacitor should be placed as
close to the IC as possible.
HOH
High-side gate driver turn-on
output
Connect to the gate of high-side GaN FET with a
short, low inductance path. A gate resistor can be
used to adjust the turn-on speed.
4
HOL
High-side gate driver turn-off
output
Connect to the gate of high-side GaN FET with a
short, low inductance path. A gate resistor can be
used to adjust the turn-off speed.
C1, D4 (1)
5
HS
High-side GaN FET source
connection
Connect to the bootstrap capacitor negative
terminal and the source of the high-side GaN
FET.
B4
6
HI
High-side driver control input
The LM5113 inputs have TTL type thresholds.
Unused inputs should be tied to ground and not
left open.
A4
7
LI
Low-side driver control input
The LM5113 inputs have TTL type thresholds.
Unused inputs should be tied to ground and not
left open.
A3 and C4, C1 and D4 are internally connected.
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PIN DESCRIPTIONS (continued)
Pin Number
Name
Description
Applications Information
DSBGA
WSON-10
A2
8
VSS
Ground return
All signals are referenced to this ground.
A1
9
LOL
Low-side gate driver sink-current
output
Connect to the gate of the low-side GaN FET with
a short, low inductance path. A gate resistor can
be used to adjust the turn-off speed.
B1
10
LOH
Low-side gate driver sourcecurrent output
Connect to the gate of high-side GaN FET with a
short, low inductance path. A gate resistor can be
used to adjust the turn-on speed.
Exposed Pad
It is recommended that the exposed pad on the
bottom of the package be soldered to ground
plane on the PC board to aid thermal dissipation.
EP
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
−0.3V to 7V
VDD to VSS
−0.3V to 7V
HB to HS
−0.3V to 15V
LI or HI Input
−0.3V to VDD +0.3V
LOH, LOL Output
VHS −0.3V to VHB +0.3V
HOH, HOL Output
HS to VSS
−5V to +100V
HB to VSS
0 to 107V
HB to VDD
0 to 100V
Junction Temperature
+150°C
−55°C to +150°C
Storage Temperature Range
ESD Rating HBM
(1)
2 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
Recommended Operating Conditions
VDD
+4.5V to +5.5V
LI or HI Input
0V to +14V
HS
−5V to 100V
HB
VHS +4V to VHS +5.5V
HS Slew Rate
<50 V/ns
−40°C to +125°C
Junction Temperature
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 5V, VSS = VHS = 0V, No Load on LOL and HOL or HOH and HOL (1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
LI = HI = 0V
0.07
0.1
mA
IDDO
VDD Operating Current
f = 500 kHz
2.0
3.0
mA
IHB
Total HB Quiescent Current
LI = HI = 0V
0.08
0.1
mA
(1)
4
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 5V, VSS = VHS = 0V, No Load on LOL and HOL or HOH and HOL(1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
mA
IHBO
Total HB Operating Current
f = 500 kHz
1.5
2.5
IHBS
HB to VSS Current, Quiescent
HS = HB = 100V
0.1
8
µA
IHBSO
HB to VSS Current, Operating
f = 500 kHz
0.4
1.0
mA
INPUT PINS
VIR
Input Voltage Threshold
Rising Edge
1.89
2.06
2.18
V
VIF
Input Voltage Threshold
Falling Edge
1.48
1.66
1.76
V
VIHYS
Input Voltage Hysteresis
RI
Input Pulldown Resistance
400
mV
100
200
300
kΩ
3.2
3.8
4.5
V
UNDER VOLTAGE PROTECTION
VDDR
VDD Rising Threshold
VDDH
VDD Threshold Hysteresis
VHBR
HB Rising Threshold
VHBH
HB Threshold Hysteresis
0.2
2.5
V
3.2
3.9
V
0.2
V
BOOTSTRAP DIODE
VDL
Low-Current Forward Voltage
IVDD-HB = 100 µA
0.45
0.65
V
VDH
High-Current Forward Voltage
IVDD-HB = 100 mA
0.90
1.00
V
RD
Dynamic Resistance
IVDD-HB = 100 mA
1.85
3.60
Ω
HB-HS Clamp
Regulation Voltage
5.2
5.45
V
4.7
LOW & HIGH SIDE GATE DRIVER
VOL
Low-Level Output Voltage
IHOL = ILOL = 100 mA
0.06
0.10
V
VOH
High-Level Output Voltage
VOH = VDD – LOH or VOH = HB – HOH
IHOH = ILOH = 100 mA
0.21
0.31
V
IOHL
Peak Source Current
HOH, LOH = 0V
1.2
IOLL
Peak Sink Current
HOL, LOL = 5V
5
IOHLK
High-Level Output Leakage Current
HOH, LOH = 0V
1.5
µA
IOLLK
Low-Level Output Leakage Current
HOL, LOL = 5V
1.5
µA
A
A
THERMAL RESISTANCE
Junction to Ambient (2)
θJA
(2)
WSON-10
40
°C/W
12-bump DSBGA
80
°C/W
Four layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187 SNOA401.
Switching Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 5V, VSS = VHS = 0V, No Load on LOL and LOH or HOL and HOH (1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLPHL
LO Turn-Off Propagation Delay
LI Falling to LOL Falling
26.5
45.0
ns
tLPLH
LO Turn-On Propagation Delay
LI Rising to LOH Rising
28.0
45.0
ns
tHPHL
HO Turn-Off Propagation Delay
HI Falling to HOL Falling
26.5
45.0
ns
tHPLH
HO Turn-On Propagation Delay
HI Rising to HOH Rising
28.0
45.0
ns
tMON
Delay Matching: LO on & HO off
1.5
8.0
ns
(1)
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Switching Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 5V, VSS = VHS = 0V, No Load on LOL and LOH or HOL and HOH(1).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1.5
8.0
ns
tMOFF
Delay Matching: LO off & HO on
tHRC
HO Rise Time (0.5V - 4.5V)
CL = 1000 pF
7.0
ns
tLRC
LO Rise Time (0.5V – 4.5V)
CL = 1000 pF
7.0
ns
tHFC
HO Fall Time (0.5V - 4.5V)
CL = 1000 pF
1.5
ns
tLFC
LO Fall Time (0.5V - 4.5V)
CL = 1000 pF
1.5
ns
tPW
Minimum Input Pulse Width that Changes
the Output
10
ns
tBS
Bootstrap Diode Reverse Recovery Time
40
ns
IF = 100mA,
IR = 100mA
Timing Diagram
LI
LI
HI
HI
tHPLH
tLPLH
tHPHL
tLPHL
LO
LO
HO
HO
tMON
tMOFF
Figure 3. Timing Diagram
6
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Typical Performance Characteristics
Peak Source Current
vs Output Voltage
Peak Sink Current
vs Output Voltage
Figure 4.
Figure 5.
IDDO
vs Frequency
IHBO
vs Frequency
Figure 6.
Figure 7.
IDD
vs Temperature
IHB
vs Temperature
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
8
UVLO Rising Thresholds
vs Temperature
UVLO Falling Thresholds
vs Temperature
Figure 10.
Figure 11.
Input Thresholds
vs Temperature
Input Threshold Hysteresis
vs Temperature
Figure 12.
Figure 13.
Bootstrap Diode Forward Voltage
Propagation Delay
vs Temperature
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
(1)
LO&HO Gate Drive — High/Low Level Output Voltage
vs Temperature
HB Regulation Voltage
vs Temperature
Figure 16.
Figure 17.
Note Unless otherwise specified, VDD = VHB = 5V, VSS = VHS = 0V.
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Detailed Operating Description
The LM5113 is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride FETs in
a synchronous buck or a half-bridge configuration. The outputs of the LM5113 are independently controlled with
TTL input thresholds. The inputs of the LM5113 can withstand voltages up to 14V regardless of the VDD voltage,
and can be directly connected to the outputs of PWM controllers.
The high side driver uses the floating bootstrap capacitor voltage to drive the high-side FET. As shown in
Figure 1, the bootstrap capacitor is recharged through an internal bootstrap diode each cycle when the HS pin is
pulled below the VDD voltage. For inductive load applications the HS node will fall to a negative potential,
clamped by the low side FET.
Due to the intrinsic feature of enhancement mode GaN FETs the source-to-drain voltage, when the gate is pulled
low, is usually higher than a diode forward voltage drop. This can lead to an excessive bootstrap voltage that can
damage the high-side GaN FET. The LM5113 solves this problem with an internal clamping circuit that prevents
the bootstrap voltage from exceeding 5.2V typical.
The output pull-down and pull-up resistance of LM5113 is optimized for enhancement mode GaN FETs to
achieve high frequency, efficient operation. The 0.6Ω pull-down resistance provides a robust low impedance turnoff path necessary to eliminate undesired turn-on induced by high dv/dt or high di/dt. The 2.1Ω pull-up resistance
helps reduce the ringing and over-shoot of the switch node voltage. The split outputs of the LM5113 offer
flexibility to adjust the turn-on and turn-off speed by independently adding additional impedance in either the turnon path and/or the turn-off path.
The LM5113 has an Under-voltage Lockout (UVLO) on both the VDD and bootstrap supplies. When the VDD
voltage is below the threshold voltage of 3.8V, both the HI and LI inputs are ignored, to prevent the GaN FETs
from being partially turned on. Also if there is sufficient VDD voltage, the UVLO will actively pull the LOL and
HOL low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2V, only HOL is pulled low.
Both UVLO threshold voltages have 200mV of hysteresis to avoid chattering.
Bypass Capacitor
The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated as follows:
(1)
QgH and QgL are gate charge of the high-side and low-side transistors respectively. Qrr is the reverse recovery
charge of the bootstrap diode, which is typically around 4nC. ΔV is the maximum allowable voltage drop across
the bypass capacitor. A 0.1uF or larger value, good quality, ceramic capacitor is recommended. The bypass
capacitor should be placed as close to the pins of the IC as possible to minimize the parasitic inductance.
Bootstrap Capacitor
The bootstrap capacitor provides the gate charge for the high-side switch, dc bias power for HB under-voltage
lockout circuit, and the reverse recovery charge of the bootstrap diode. The required bypass capacitance can be
calculated as follows:
(2)
IHB is the quiescent current of the high-side driver. ton is the maximum on-time period of the high-side transistor.
A good quality, ceramic capacitor should be used for the bootstrap capacitor. It is recommended to place the
bootstrap capacitor as close to the HB and HS pins as possible.
Power Dissipation
The power consumption of the driver is an important measure that determines the maximum achievable
operating frequency of the driver. It should be kept below the maximum power dissipation limit of the package at
the operating temperature. The total power dissipation of the LM5113 is the sum of the gate driver losses and the
bootstrap diode power loss.
The gate driver losses are incurred by charge and discharge of the capacitive load. It can be approximated as
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(3)
CLoadH and CLoadL are the high-side and the low-side capacitive loads respectively. It can also be calculated with
the total input gate charge of the high-side and the low-side transistors as
(4)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equations. This plot can be used to
approximate the power losses due to the gate drivers.
Gate Driver Power Dissipation (LO+HO)
VDD=+5V
Figure 18. Neglecting Bootstrap Diode Losses
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to the operating frequency. Larger
capacitive loads require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input
voltages (VIN) to the half bridge also result in higher reverse recovery losses.
The following two plots illustrate the forward bias power loss and the reverse bias power loss of the bootstrap
diode respectively. The plots are generated based on calculations and lab measurements of the diode reverse
time and current under several operating conditions. The plots can be used to predict the bootstrap diode power
loss under different operating conditions.
The Load of High-Side Driver is a GaN FET
with Total Gate Charge of 10nC
Figure 19. Forward Bias Power Loss of
Bootstrap Diode VIN=50V
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The Load of High-Side Driver is a GaN FET
with Total Gate Charge of 10nC
Figure 20. Reverse Recovery Power Loss of
Bootstrap Diode VIN=50V
The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as
(TJ - TA)
P=
TJA
(5)
Layout Considerations
Small gate capacitance and miller capacitance enable enhancement mode GaN FETs to operate with fast
switching speed. The induced high dv/dt and di/dt, coupled with a low gate threshold voltage and limited
headroom of enhancement mode GaN FETs gate voltage, make the circuit layout crucial to the optimum
performance. Following are some hints.
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and
discharge the GaN FETs gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the GaN FETs. The GaN FETs should be placed close to the
driver.
2. The second high current path includes the bootstrap capacitor, the local ground referenced VDD bypass
capacitor and low-side GaN FET. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the
bootstrap diode from the ground referenced VDD capacitor. The recharging occurs in a short time interval
and involves high peak current. Minimizing this loop length and area on the circuit board is important to
ensure reliable operation.
3. The parasitic inductance in series with the source of the high-side FET and the low-side FET can impose
excessive negative voltage transients on the driver. It is recommended to connect HS pin and VSS pin to the
respective source of the high-side and low-side transistors with a short and low-inductance path.
4. The parasitic source inductance, along with the gate capacitor and the driver pull-down path, can form a LCR
resonant tank, resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp
the ringing.
5. Low ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak current being drawn from VDD during turn-on of the FETs. It is
most desirable to place the VDD decoupling capacitor and the HB to HS bootstrap capacitor on the same
side of the PC board as the driver. The inductance of vias can impose excessive ringing on the IC pins.
6. To prevent excessive ringing on the input power bus, good decoupling practices are required by placing low
ESR ceramic capacitors adjacent to the GaN FETs.
The following figures show recommended layout patterns for WSON-10 package and DSBGA package
respectively. Two cases are considered: (1) Without any gate resistors; (2) With an optional turn-on gate resistor.
It should be noted that 0402 DSBGA package is assumed for the passive components in the drawings. For
information on DSBGA package assembly, refer to Application Note AN-1112 SNVA009.
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Bootstrap
Capacitor
HO
To Hi-Side FET
HS
To Hi-Side FET
2
3
4
5
VDD 1
HB
HS
2
3
4
5
VDD 1
HB
HS
HO
HS
HOL
Bootstrap
Capacitor
HOH
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Bypass
Capacitor
Bypass
Capacitor
9
10
LOL
LOH
LI
To Low-Side FET
8 VSS
7
HI
LOH
6
10
LOL
LI
9
7
HI
8 VSS
6
LO
GND
LO
To Low-Side FET
GND
Figure 21. WSON-10
Without Gate Resistors
Bootstrap
Capacitor
HO
HS
Figure 22. WSON-10
With HOH and LOH Gate Resistors
Bootstrap
Capacitor
HO
To Hi-Side FET
D
HS
HOL
D
HS
C
VDD
HS
C
VDD
HS
B
HI
LOH
B
HI
LOH
A
LI
VDD
VSS
LOL
A
LI
VDD
VSS
4
3
2
4
3
2
HB
HOH
1
LO
Bypass
Capacitor
To Hi-Side FET
HS
To Low-Side FET
Bypass
Capacitor
GND
Figure 23. DSBGA
Without Gate Resistors
HB
HOH
HOL
LOL
1
LO
GND
To Low-Side FET
Figure 24. DSBGA
With HOH and LOH Gate Resistors
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
•
14
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 13
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM5113
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5113SD/NOPB
ACTIVE
WSON
DPR
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5113
LM5113SDE/NOPB
ACTIVE
WSON
DPR
10
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5113
LM5113SDX/NOPB
ACTIVE
WSON
DPR
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L5113
LM5113TME/NOPB
ACTIVE
DSBGA
YFX
12
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
5113
LM5113TMX/NOPB
ACTIVE
DSBGA
YFX
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
5113
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Feb-2014
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LM5113SD/NOPB
WSON
DPR
10
LM5113SDE/NOPB
WSON
DPR
LM5113SDX/NOPB
WSON
DPR
LM5113TME/NOPB
DSBGA
LM5113TMX/NOPB
DSBGA
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
10
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
10
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
YFX
12
250
178.0
8.4
1.85
2.01
0.76
4.0
8.0
Q1
YFX
12
3000
178.0
8.4
1.85
2.01
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5113SD/NOPB
WSON
DPR
10
1000
210.0
185.0
35.0
LM5113SDE/NOPB
WSON
DPR
10
250
210.0
185.0
35.0
LM5113SDX/NOPB
WSON
DPR
10
4500
367.0
367.0
35.0
LM5113TME/NOPB
DSBGA
YFX
12
250
210.0
185.0
35.0
LM5113TMX/NOPB
DSBGA
YFX
12
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
www.ti.com
MECHANICAL DATA
YFX0012xxx
D
0.600
±0.075
E
TOP SIDE OF PACKAGE
BOTTOM SIDE OF PACKAGE
TMP12XXX (Rev A)
D: Max = 1.905 mm, Min =1.845 mm
E: Max = 1.756 mm, Min =1.695 mm
4215094/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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