TI SM72295MA-NOPB

SM72295
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SNVS688E – OCTOBER 2010 – REVISED APRIL 2013
SM72295 Photovoltaic Full Bridge Driver
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FEATURES
DESCRIPTION
•
•
•
•
•
The SM72295 is designed to drive 4 discrete N type
MOSFET’s in a full bridge configuration. The drivers
provide 3A of peak current for fast efficient switching
and integrated high speed bootstrap diodes. Current
sensing is provided by 2 transconductance amplifiers
with externally programmable gain and filtering to
remove ripple current to provide average current
information to the control circuit. The current sense
amplifiers have buffered outputs available to provide
a low impedance interface to an A/D converter if
needed. An externally programmable input over
voltage comparator is also included to shutdown all
outputs. Under voltage lockout with a PGOOD
indicator prevents the drivers from operating if VCC is
too low.
1
2
•
•
•
Renewable Energy Grade
Dual Half Bridge MOSFET Drivers
Integrated 100V Bootstrap Diodes
Independent High and Low Driver Logic Inputs
Bootstrap Supply Voltage Range up to 115V
DC
Two Current Sense Amplifiers with Externally
Programmable Gain and Buffered Outputs
Programmable Over Voltage Protection
Supply Rail Under-Voltage Lockouts with
Power Good Indicator
PACKAGE
•
SOIC-28
Typical Application Circuit
+
R16
10m
R15
10m
+
R10
R12
R11
PV
Vout
Vin
-
C5
0.47 uF
C6
1
uF
C1
R9
10k
R13 R14
-
C4
0.47 uF
C3
1
uF
5V
HSB
VDD
OVS
OVP
IOUT
SOB
SIB
HOB
PGOOD
BOUT
HBB
LIB
LOB
VCCB
R6
500
R5
500
AGND
SM72295
HIB
PGND
LIA
HBA
VCCA
BIN
HIA
HOA
SOA
IIN
LOA
HSA
SIA
10V
R7
500
C10
10n
C8
10 nF
optional
optional
C7
R3
40k
C2
R8
500
R4
40k
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
SM72295
SNVS688E – OCTOBER 2010 – REVISED APRIL 2013
www.ti.com
Connection Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SIA
HSA
SOA
HOA
IIN
HBA
BIN
AGND
LIA
HIA
SM72295
28
27
26
VCCA
25
LOA
24
PGND
23
LOB
22
21
HIB
VCCB
LIB
HBB
20
PGOOD
HOB
19
BOUT
HSB
IOUT
VDD
SOB
OVS
SIB
OVP
18
17
16
15
Figure 1. Top View
SOIC-28
PIN DESCRIPTIONS
2
Pin
Name
Description
1
Application Information
SIA
Sense high input for input current
sense transconductance amplifier
Tie to positive side of the current sense resistor through an external gain
programming resistor (RI). Amplifier transconductance is 1/RI.
2
S0A
Sense low input for input current
sense transconductance amplifier
Tie to negative side of the current sense resistor through an external gain
programming resistor. Amplifier transconductance is 1/RI.
3
IIN
Output for current sense
transconductance amplifier
Output of the input current sense amplifier. Requires an external resistor to
ground (RL). Gain is RL/RI, where RI is the external resistor in series with the
SIA pin.
4
BIN
Buffered IIN
Buffered IIN.
Analog ground
Ground return for the analog circuitry. Tie to the ground plane under the IC
5
AGND
6, 9
LIA, LIB
Low side driver control input
The inputs have TTL type thresholds. Unused inputs should be tied to ground
and not left open.
7, 8
HIA, HIB High side driver control input
The inputs have TTL type thresholds. Unused inputs should be tied to ground
and not left open.
10
PGOOD
Power good indicator output
Open drain output with an internal pull-up resistor to VDD indicating VCC is in
regulation. PGOOD low implies VCC is out of regulation.
11
BOUT
Buffered IOUT
Buffered IOUT.
12
IOUT
Output for current sense
comparator.
Output of the output current sense amplifier. Requires an external resistor to
ground (RL). Gain is RL/RI, where RI is the external resistor in series with the
SIB pin.
13
S0B
Sense low input for output current
sense amplifier
Tie to negative side of the current sense resistor through an external gain
programming resistor. Amplifier transconductance is 1/RI.
14
SIB
Sense high input for output current
sense amplifier
Tie to positive side of the current sense resistor through an external gain
programming resistor (RI). Amplifier transconductance is 1/RI.
15
OVP
Over voltage indicator output
Open drain output with an internal pull-up resistor to VDD indicating OVS >VDD.
OVP is low when OVS>VDD.
16
OVS
Sense input for over voltage
Requires an external resistor divider. VDD is the reference voltage.
17
VDD
3.3V or 5V regulator output
Bypass with 0.1uF. Reference for over voltage shutdown and IOUT/IIN clamp
18, 28
HSA,
HSB
High side MOSFET source
connection
Connect to bootstrap capacitor negative terminal and the source of the high side
MOSFET.
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PIN DESCRIPTIONS (continued)
Pin
Name
Description
Application Information
19, 27
HOA,
HOB
High side gate driver output
Connect to gate of high side MOSFET with a short low inductance path.
20,26
HBA,
HBB
High side gate driver bootstrap rail. Connect the positive terminal of the bootstrap capacitor to HB and the negative
terminal to HS. The bootstrap capacitor should be placed as close to IC as
possible.
21,25
VCCA,
VCCB
22, 24
23
Positive gate drive supply
Locally decouple to PGND using low ESR/ESL capacitor located as close to IC
as possible.
LOA,
LOB
Low side gate driver output
Connect to the gate of the low side MOSFET with a short low inductance path.
PGND
Power ground return
Ground return for the LO drivers. Tie to the ground plane under the IC
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
VCCA, VCCB
-0.3 to 14V
VDD
-0.3 to 7V
HBA to HSA, HBB to HSB
-0.3 to 15V
LIA,LIB,HIA,HIB,OVS
-0.3 to 7V
LOA,LOB
-0.3 to VCC+ 0.3V
HOA,HOB
HS–0.3 to HB + 0.3V
SIA,SOA,SIB,SOB
-0.3 to 100V
SIA to SOA, SIB to SOB
-0.8 to 0.8V
HSA,HSB (3)
-5 to 100V
HBA, HBB
115V
PGOOD, OVP
-0.3 to VDD
IIN, IOUT
-0.3 to VDD
BIN, BOUT
-0.3 to VDD
Junction Temperature
150°C
Storage Temperatue Range
ESD Rating (4)
(1)
(2)
(3)
(4)
-55°C to +150°C
Human Body Model
2 kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
In the application the HS nodes are clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally
not exceed –1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur, the HS voltage must never be more negative than VCC-15V. For example if VCC = 10V,
the negative transients at HS must not exceed –5V.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV for all pins except HB, HO & HS
which are rated at 1000V.
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SM72295
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Recommended Operating Conditions
VCCA,VCCB
+8V to +14V
VDD
+3V to 7V
SI, SO common mode
VDD+1V to 100V
HS (1)
-1V to 100V
HBA, HBB
HS+7V to HS+14V
HS Slew Rate
<50V/ns
Junction Temperature
(1)
-40°C to +125°C
In the application the HS nodes are clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally
not exceed –1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur, the HS voltage must never be more negative than VCC-15V. For example if VCC = 10V,
the negative transients at HS must not exceed –5V.
Electrical Characteristics (1)
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. No load on LO & HO, VCC = 10V, VDD = 5V, HB-HS = 10V, OVS = 0V unless otherwise indicated.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
SIA = SOB, SIB = SOB.
25
40
μA
ICC
VCC Quiescent Current
(ICCA+ICCB)
All outputs off
500
800
μA
ICCO
VCC Operating Current
(ICCA+ICCB)
LOA & LOB switching at 200kHz
2.2
3
mA
IHB
HBA, HBB Quiescent Current
All outputs off
55
200
μA
IHBO
HBA, HBB Operating Current
HOA & HOB switching at 200kHz
700
1000
μA
IHBS
HBA & HBB to VSS Current,
Quiescent
HS = 100V, HB = 110V
0.1
10
μA
IHBSO
HBA and HBB to VSS Current,
Operating
f = 200kHz
130
μA
PGOOD, OVB OUTPUTs
VOL
Output Low RDS
25
50
Ω
RPU
VDD pull up resistor
50
90
kΩ
1.8
2.3
LI ,HI INPUT PINS
VIL
Input Voltage Threshold
VIHYS
Input Voltage Hysteresis
RI
LI, HI Pull down Resistance
1.3
50
V
mV
100
200
400
VDD-50mV
VDD
VDD+50mV
kΩ
OVER VOLTAGE SHUTDOWN
VOVR
OVS Rising Threshold
VOVH
OVS threshold Hysteresis
IOVS
OVS input bias current
OVS<VDD
V
5%
VDD
1
nA
UNDER VOLTAGE SHUTDOWN
VCCR
VCC Rising Threshold
VCCH
VCC threshold Hysteresis
VHBR
HB-HS Rising Threshold
VHBH
HB-HS Threshold Hysteresis
6
6.9
7.4
0.5
5.7
6.6
V
V
7.1
0.4
V
V
BOOT STRAP DIODE
VDH
High-Current Forward Voltage
IVCC-HB = 100mA
0.8
1
V
RD
Dynamic Resistance
IVCC-HB = 100mA
1
1.65
Ω
(1)
4
Min and Max limits are 100% production tested at 25ºC. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics(1) (continued)
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. No load on LO & HO, VCC = 10V, VDD = 5V, HB-HS = 10V, OVS = 0V unless otherwise indicated.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LO & HO GATE DRIVER
VOL
Low-Level Output Voltage
ILO = 100mA
VOL = LO-PGND or HO-HS
0.16
0.4
V
VOH
High-Level Output Voltage
ILO = -100mA
VOH = VCC-LO or VCC-HO
0.28
0.6
V
IOHL
Peak Pullup Current
HO, LO = 12V
3
IOLL
Peak Pulldown Current
HO, LO = 0V
3
A
tLPHL
LO Turn-Off Propagation Delay
LI Falling to LO Falling
22
ns
tLPLH
LO Turn-On Propagation Delay
LI Rising to LO Rising
26
ns
tHPHL
HO Turn-Off Propagation Delay
HI Falling to HO Falling
22
ns
tHPLH
LO Turn-On Propagation Delay
HI Rising to HO Rising
26
ns
tMON
Delay Matching: LO on & HO
off
1
ns
tMOFF
Delay Matching: LO off & HO
on
1
ns
tRC, tFC
Either Output Rise/Fall Time
8
ns
tPW
Minimum Input Pulse Width that
Changes the Output
50
ns
tBS
Bootstrap Diode Turn-On or
Turn-Off Time
37
ns
CL = 1000pF
IF = 100mA/ IR = 100mA
A
CURRENT SENSE AMPLIFIER
VOS
Offset voltage
RSI = RSO = 500, 10mV sense
resistor voltage
Gain 5mV
Gain is programmed with
external resistors
IOUT, IIN =(RL/RSI )* (SI-SO)
5mV sense resistor voltage
RSI = RSO = 1000, RL = 75K
390
mV
Gain
50mV
Gain is programmed with
external resistors
IOUT, IIN =(RL/RSI )* (SI-SO)
50mV sense resistor voltage
RSI = RSO = 1000, RL = 75K
3.85
V
Vclamp
Output Clamp
0.1V sense resistor voltage
RSI = RSO = 1000, RL = 75K
VDD
V
-2
2
mV
CURRENT SENSE BUFFER
Offset voltage (BIN-IIN),
(BOUT-IOUT)
IIN = 2.5V
Output low voltage BOUT,BIN
IIN, IOUT = 0
Output high voltage BOUT,BIN
IIN, IOUT = VDD
-60
0
VDD-100mV
VDD-30mV
60
mV
50
mV
VDD
mV
THERMAL RESISTANCE
θJA
(2)
Junction to Ambient
SOIC-28 (2)
60
°C/W
2 layer board with 2 oz Cu using JEDEC JESD51 thermal board.
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HIB
LIB
HIA
LIA
Block Diagram
HBB
VCCB
VDD
UVLO
HOB
3V
DRIVER
LEVEL
SHIFT
3V
200k
HSB
HBA
VCCA
UVLO
VDD
PGOOD
50k
VCC
UVLO
HOA
DRIVER
LEVEL
SHIFT
3V
HSA
VCCA
3V
VDD
LOB
DRIVER
50k
PGND
OVP
VCCB
3V
OVS
LOA
DRIVER
+
PGND
VDD 3.3V/5V
-
SIA
SIB
SOA
SOB
+
+
_
_
IIN
IOUT
+
_
+
_
VDD
CLAMP
AGND
VDD
CLAMP
BOUT
BIN
Figure 2. Block Diagram
6
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Typical Performance Characteristics
Operating Current
vs Temperature
VCC Undervoltage Rising Threshold
vs Temperature
Figure 3.
Figure 4.
VCC Quiescent Current
vs Temperature
VCC Undervoltage Threshold Hysteresis
vs Temperature
Figure 5.
Figure 6.
VDD Quiescent Current
vs Temperature
Gate Drive High Level Output Voltage
vs Temperature
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
8
Gate Drive Low level Output Voltage
vs Temperature
Bootstrap Diode Forward Voltage
vs Temperature
Figure 9.
Figure 10.
Current Sense Amplifier Input Offset Voltage
vs Temperature
Current Sense Amplifier Output Buffer Offset Voltage
vs Temperature
Figure 11.
Figure 12.
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Timing Diagram
LI
LI
HI
tHPLH
tLPLH
HI
tHPHL
tLPHL
LO
LO
HO
HO
tMON
tMOFF
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
PDGATES = 2 • f • CL • VDD2
(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation. This plot can be used to
approximate the power losses due to the gate drivers.
Figure 13. Gate Driver Power Dissipation (LO + HO)
VCC = 12V, Neglecting Diode Losses
1.000
CL = 4400 pF
POWER (W)
0.100
CL = 1000 pF
0.010
CL = 0 pF
0.001
0.1
1.0
10.0
100.0
1000.0
SWITCHING FREQUENCY (kHz)
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the diode power dissipation. The total IC power dissipation can be estimated from the
previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application.
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Figure 14. Diode Power Dissipation VIN = 50V
0.100
POWER (W)
CL = 4400 pF
CL = 0 pF
0.010
0.001
1
10
100
1000
SWITCHING FREQUENCY (kHz)
Layout Considerations
The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
(a) The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
(b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
10
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SNVS688E – OCTOBER 2010 – REVISED APRIL 2013
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SM72295MA/NOPB
ACTIVE
SOIC
DW
28
26
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
S72295
SM72295MAE/NOPB
ACTIVE
SOIC
DW
28
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
S72295
SM72295MAX/NOPB
ACTIVE
SOIC
DW
28
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
S72295
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SM72295MAE/NOPB
SOIC
DW
28
250
178.0
24.4
10.8
18.4
3.2
12.0
24.0
Q1
SM72295MAX/NOPB
SOIC
DW
28
1000
330.0
24.4
10.8
18.4
3.2
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SM72295MAE/NOPB
SOIC
DW
SM72295MAX/NOPB
SOIC
DW
28
250
213.0
191.0
55.0
28
1000
367.0
367.0
45.0
Pack Materials-Page 2
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