2-Bit Bidirectional Voltage-Level Translator

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TXB0102
SCES641C – MAY 2007 – REVISED DECEMBER 2014
TXB0102 2-Bit Bidirectional Voltage-Level Translator With Auto Direction Sensing and
±15-kV ESD Protection
1 Features
3 Description
•
This 2-bit noninverting translator uses two separate
configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply
voltage from 1.2 V to 3.6 V. The B port is designed to
track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2-V,
1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
VCCA should not exceed VCCB.
1
•
•
•
•
•
•
•
Available in the Texas Instruments NanoFree™
Packages
1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V On
B Port (VCCA ≤ VCCB)
VCC Isolation Feature – If Either VCC Input Is at
GND, All Outputs Are in the High-Impedance
State
OE Input Circuit Referenced to VCCA
Low Power Consumption, 4-μA Max ICC
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– A Port
– 2500-V Human-Body Model (A114-B)
– 200-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
– B Port
– 15-kV Human-Body Model (A114-B)
– 200-V Machine Model (A115-A)
– 1500-V Charged-Device Model (C101)
When the output-enable (OE) input is low, all outputs
are placed in the high-impedance state.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
To ensure the high-impedance state during power up
or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
NanoFree™ technology is a major breakthrough in IC
packaging concepts, using the die as the package.
Device Information(1)
PART NUMBER
2 Applications
•
•
•
•
TXB0102
Handsets
Smartphones
Tablets
Desktop PCs
PACKAGE
BODY SIZE (NOM)
SSOP (8)
2.95 mm × 2.80 mm
VSSOP (8)
2.30 mm × 2.00 mm
DSBGA (8)
0.90 mm × 1.80 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Operating Circuit
VCCB
Processor
Peripheral
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TXB0102
SCES641C – MAY 2007 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
Handling Ratings....................................................... 4
Recommended Operating Conditions ...................... 4
Thermal Information .................................................. 5
Electrical Characteristics .......................................... 5
Operating Characteristics.......................................... 6
VCCA = 1.2 V Timing Requirements .......................... 6
VCCA = 1.5 V ± 0.1 V Timing Requirements ............. 6
VCCA = 1.8 V ± 0.15 V Timing Requirements ........... 6
VCCA = 2.5 V ± 0.2 V Timing Requirements ........... 7
VCCA = 3.3 V ± 0.3 V Timing Requirements ........... 7
VCCA = 1.2 V Switching Characteristics .................. 7
VCCA = 1.5 V ± 0.1 V Switching Characteristics ..... 8
VCCA = 1.8 V ± 0.15 V Switching Characteristics ... 8
VCCA = 2.5 V ± 0.2 V Switching Characteristics ..... 9
VCCA = 3.3 V ± 0.3 V Switching Characteristics ..... 9
6.17 Typical Characteristics .......................................... 10
7
8
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2012) to Revision C
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
Changes from Revision A (January 2011) to Revision B
•
2
Page
Added notes to pin out graphics............................................................................................................................................. 3
Changes from Original (May 2007) to Revision A
•
Page
Page
Added ball labels to the YZP Package. .................................................................................................................................. 3
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Product Folder Links: TXB0102
TXB0102
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SCES641C – MAY 2007 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
YZP PACKAGE
(BOTTOM VIEW)
DCT OR DCU PACKAGE
(TOP VIEW)
8 B1
B2 1
GND 2
7 VCCB
VCCA 3
6 OE
A2 4
5 A1
A2
D1
4 5 D2
A1
VCCA
C1
3 6 C2
GND
B1
2 7 B2
OE
VCCB
B2
A1
1 8 A2
B1
A.
Pullup resistors are not required on both sides for Logic I/O.
B.
If pullup or pulldown resistors are needed, the resistor value must be over 50 kΩ.
C.
50 kΩ is a safe recommended value, if the customer can accept higher Vol or lower VCCOUT, smaller pullup or
pulldown resistor is allowed, the draft estimation is VOL = VCCOUT × 4.5k/(4.5k + Rpu) and VOH = VCCOUT × Rdw/(4.5k
+ Rdw).
D.
If pullup resistors are needed, please refer to the TXS0102 or contact TI.
E.
For detailed information, please refer to application note SCEA043.
Pin Functions: YZP
PIN
TYPE (1)
DESCRIPTION
BALL
NO.
NAME
A1
1
B2
I/O
Input/output B. Referenced to VCCB.
A2
5
B1
I/O
Input/output A1. Referenced to VCCA.
B1
2
GND
S
Ground
B2
6
VCCB
I
3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
C1
3
VCCA
S
A-port supply voltage. 1.1 V ≤ VCCA ≤ 3.6 V, VCCA ≤ VCCB
C2
7
OE
S
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V
D1
4
A2
I/O
Input/output A2. Referenced to VCCA.
D2
8
A1
I/O
Input/output B1. Referenced to VCCB.
(1)
(1) I = input, O = output, I/O = input and output, S = power supply
Pin Functions: DCT or DCU
PIN
NO.
(1)
NAME
TYPE (1)
DESCRIPTION
1
B2
I/O
2
GND
S
Input/output B. Referenced to VCCB.
Ground
3
VCCA
S
A-port supply voltage. 1.1 V ≤ VCCA ≤ 3.6 V, VCCA ≤ VCCB
4
A2
I/O
Input/output A2. Referenced to VCCA.
5
A1
I/O
Input/output A1. Referenced to VCCA.
6
OE
I
3-state output-mode enable. Pull OE low to place all outputs in 3-state mode. Referenced to VCCA.
7
VCCB
S
B-port supply voltage. 1.65 V ≤ VCCB ≤ 5.5 V
8
B1
I/O
Input/output B1. Referenced to VCCB.
(1) I = input, O = output, I/O = input and output, S = power supply
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SCES641C – MAY 2007 – REVISED DECEMBER 2014
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCCA
Supply voltage range
–0.5
4.6
VCCB
Supply voltage range
–0.5
6.5
VI
Input voltage range (2)
A port
–0.5
4.6
B port
–0.5
6.5
VO
Voltage range applied to any output in the high-impedance or
power-off state (2)
A port
–0.5
4.6
B port
–0.5
6.5
VO
Voltage range applied to any output in the high or low state (2)
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCCA, VCCB, or GND
±100
mA
(1)
(2)
(3)
(3)
UNIT
V
V
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 Handling Ratings
Tstg
Storage temperature range
MIN
MAX
UNIT
–65
150
°C
2500
V
15
kV
Human body model (HBM), per ANSI/ESDA/JEDEC JS001, all pins (1), A Port
Human body model (HBM), per ANSI/ESDA/JEDEC JS001, all pins (1), B Port
V(ESD)
(1)
(2)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2), A Port
1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2), B Port
1500
Machine model (MM,A115-A), A Port
200
Machine model (MM,A115-A), B Port
200
(2)
VCCA
VCCA
VCCB
VCCB
Supply voltage
MIN
MAX
1.2
3.6
1.65
5.5
Data inputs
1.2 V to 3.6 V
1.65 V to 5.5 V
VCCI × 0.65 (3)
VCCI
OE input
1.2 V to 3.6 V
1.65 V to 5.5 V
VCCA × 0.65
5.5
Data inputs
1.2 V to 5.5 V
1.65 V to 5.5 V
0
VCCI × 0.35 (3)
OE input
1.2 V to 3.6 V
1.65 V to 5.5 V
0
VCCA × 0.35
0
3.6
1.2 V to 3.6 V
1.65 V to 5.5 V
0
5.5
VIH
High-level input voltage
VIL
Low-level input voltage
VO
Voltage range applied to any A port
output in the high-impedance
B port
or power-off state
4
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions (1)
(1)
(2)
(3)
–15
UNIT
V
V
V
V
The A and B sides of an unused data I/O pair must be held in the same state, i.e., both at VCCI or both at GND.
VCCA must be less than or equal to VCCB and must not exceed 3.6 V.
VCCI is the supply voltage associated with the input port.
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SCES641C – MAY 2007 – REVISED DECEMBER 2014
Recommended Operating Conditions(1) (2) (continued)
Δt/Δv
Input transition rise or fall
rate
TA
Operating free-air temperature
VCCA
VCCB
A port inputs
1.2 V to 3.6 V
1.65 V to 5.5 V
MIN
MAX
40
B port inputs
1.2 V to 3.6 V
1.65 V to 1.95 V
40
4.5 V to 5.5 V
UNIT
ns/V
30
–40
85
°C
6.4 Thermal Information
TXB0102
THERMAL METRIC (1)
DCT
DCU
YZP
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
168.7
199.1
RθJC(top)
Junction-to-case (top) thermal resistance
111.7
72.4
1.6
RθJB
Junction-to-board thermal resistance
78.1
77.8
10.8
ψJT
Junction-to-top characterization parameter
45.0
6.2
3.1
ψJB
Junction-to-board characterization parameter
77.5
77.4
10.9
(1)
105.8
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics (1)
(2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VCCA
VCCB
1.2 V
IOH = –20 μA
VOLA
IOL = 20 μA
VOHB
IOH = –20 μA
1.65 V to 5.5 V
VOLB
IOL = 20 μA
1.65 V to 5.5 V
–40°C to 85°C
MAX
MIN
MAX
1.4 V to 3.6 V
1.2 V
0.3
1.4 V to 3.6 V
0.4
VCCB – 0.4
V
V
μA
1.2 V to 3.6 V
1.65 V to 5.5 V
±1
±2
A port
VI or VO = 0 to 3.6
V
0V
0 V to 5.5 V
±1
±2
B port
VI or VO = 0 to 5.5
V
0 V to 3.6 V
0V
±1
±2
A or B port
OE = GND
1.2 V to 3.6 V
1.65 V to 5.5 V
±1
±2
1.2 V
1.65 V to 5.5 V
1.4 V to 3.6 V
1.65 V to 5.5 V
3
3.6 V
0V
2
VI = VCCI or GND,
IO = 0
μA
0V
5.5 V
1.65 V to 5.5 V
VI = VCCI or GND,
IO = 0
1.4 V to 3.6 V
1.65 V to 5.5 V
5
3.6 V
0V
–2
0V
5.5 V
ICCA + ICCB
VI = VCCI or GND,
IO = 0
1.2 V
1.65 V to 5.5 V
1.4 V to 3.6 V
1.65 V to 5.5 V
VI = VCCI or GND,
IO = 0,
OE = GND
1.2 V
1.65 V to 5.5 V
ICCZA
1.4 V to 3.6 V
1.65 V to 5.5 V
(1)
(2)
μA
0.06
1.2 V
ICCB
V
0.4
VI = VCCI or GND
ICCA
UNIT
V
VCCA – 0.4
OE
Ioff
IOZ
TYP
1.1
VOHA
II
TA = 25°C
MIN
μA
–2
3.4
μA
2
3.5
8
μA
0.05
3
μA
VCCI is the supply voltage associated with the input port.
VCCO is the supply voltage associated with the output port.
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Electrical Characteristics(1) (2) (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VI = VCCI or GND,
IO = 0,
OE = GND
ICCZB
Ci
Cio
TEST
CONDITIONS
OE
A port
VCCB
1.2 V
1.65 V to 5.5 V
1.4 V to 3.6 V
1.65 V to 5.5 V
1.2 V to 3.6 V
1.65 V to 5.5 V
1.2 V to 3.6 V
B port
TA = 25°C
VCCA
MIN
TYP
–40°C to 85°C
MAX
MIN
UNIT
MAX
3.3
μA
5
1.65 V to 5.5 V
2.5
3
5
6
11
14
pF
pF
6.6 Operating Characteristics
TA = 25°C
VCCA
1.2 V
1.2 V
1.5 V
1.8 V
2.5 V
2.5 V
3.3 V
2.5 V
5V
3.3 V
to
5V
VCCB
PARAMETER
TEST CONDITIONS
5V
CpdA
CpdB
CpdA
CpdB
A port input, B port output
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = VCCA
(outputs enabled)
B port input, A port output
A port input, B port output
B port input, A port output
A port input, B port output
CL = 0, f = 10 MHz,
tr = tf = 1 ns,
OE = GND
(outputs disabled)
B port input, A port output
A port input, B port output
B port input, A port output
1.8 V
1.8 V
1.8 V
UNIT
TYP
TYP
TYP
TYP
TYP
TYP
7.8
8
8
7
7
8
TYP
8
12
11
11
11
11
11
11
38.1
29
29
29
29
30
30
25.4
19
18
18
18
21
21
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.01
0.02
0.01
0.01
0.01
0.01
0.01
0.02
0.03
pF
pF
6.7 VCCA = 1.2 V Timing Requirements
TA = 25°C, VCCA = 1.2 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
20
20
20
20
Mbps
50
50
50
50
ns
Data rate
tw
Pulse duration
Data inputs
UNIT
6.8 VCCA = 1.5 V ± 0.1 V Timing Requirements
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
Data rate
tw
Pulse duration
MAX
VCCB = 2.5 V
± 0.2 V
MIN
40
Data inputs
MAX
VCCB = 3.3 V
± 0.3 V
MIN
40
25
25
MAX
VCCB = 5 V
± 0.5 V
MIN
40
25
UNIT
MAX
40
25
Mbps
ns
6.9 VCCA = 1.8 V ± 0.15 V Timing Requirements
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
Data rate
6
MAX
VCCB = 2.5 V
± 0.2 V
MIN
60
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MAX
60
VCCB = 3.3 V
± 0.3 V
MIN
MAX
60
VCCB = 5 V
± 0.5 V
MIN
UNIT
MAX
60
Mbps
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VCCA = 1.8 V ± 0.15 V Timing Requirements (continued)
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
tw
Pulse duration
Data inputs
VCCB = 2.5 V
± 0.2 V
MAX
MIN
17
MAX
VCCB = 3.3 V
± 0.3 V
MIN
17
VCCB = 5 V
± 0.5 V
MAX
MIN
17
UNIT
MAX
17
ns
6.10 VCCA = 2.5 V ± 0.2 V Timing Requirements
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
VCCB = 2.5 V
± 0.2 V
MIN
Data rate
tw
VCCB = 3.3 V
± 0.3 V
MAX
MIN
MAX
100
Pulse duration
Data inputs
VCCB = 5 V
± 0.5 V
MIN
100
10
UNIT
MAX
100
10
10
Mbps
ns
6.11 VCCA = 3.3 V ± 0.3 V Timing Requirements
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
VCCB = 3.3 V
± 0.3 V
MIN
Data rate
tw
VCCB = 5 V
± 0.5 V
MAX
MIN
100
Pulse duration
Data inputs
10
UNIT
MAX
100
10
Mbps
ns
6.12 VCCA = 1.2 V Switching Characteristics
TA = 25°C, VCCA = 1.2 V
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
TYP
TYP
TYP
TYP
A
B
6.9
5.7
5.3
5.5
B
A
7.4
6.4
6
5.8
A
1
1
1
1
B
1
1
1
1
A
18
15
14
14
B
20
17
16
16
ten
OE
tdis
OE
UNIT
ns
μs
ns
trA
A port rise time
4.2
4.2
4.2
4.2
ns
tfA
A port fall times
4.2
4.2
4.2
4.2
ns
trB
B port rise times
2.1
1.5
1.2
1.1
ns
tfB
B port fall times
2.1
1.5
1.2
1.1
ns
tsk(o)
Channel-to-channel
0.5
0.5
0.5
1.4
ns
20
20
20
20
Mbps
Max data rate
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6.13 VCCA = 1.5 V ± 0.1 V Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
B
1.4
12.9
1.2
10.1
A
0.9
14.2
0.7
12
VCCB = 5 V
± 0.5 V
UNIT
MAX
MIN
MAX
1.1
10
0.8
9.9
0.4
11.7
0.3
13.7
A
1
1
1
1
B
1
1
1
1
A
5.9
31
5.7
25.9
5.6
23
5.7
22.4
B
5.4
30.3
4.9
22.8
4.8
20
4.9
19.5
ns
μs
ns
trA
A port rise times
1.4
5.1
1.4
5.1
1.4
5.1
1.4
5.1
ns
tfA
A port fall times
1.4
5.1
1.4
5.1
1.4
5.1
1.4
5.1
ns
trB
B port rise times
0.9
4.5
0.6
3.2
0.5
2.8
0.4
2.7
ns
tfB
B port fall times
0.9
4.5
0.6
3.2
0.5
2.8
0.4
2.7
ns
tsk(o)
Channel-to-channel
0.5
Max data rate
0.5
40
40
0.5
40
0.5
40
ns
Mbps
6.14 VCCA = 1.8 V ± 0.15 V Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.6
11
1.4
7.7
1.3
6.8
1.2
6.5
A
1.5
12
1.3
8.4
1
7.6
0.9
7.1
A
1
1
1
1
B
1
1
1
1
A
5.9
31
5.1
21.3
5
19.3
5
17.4
B
5.4
30.3
4.4
20.8
4.2
17.9
4.3
16.3
ns
μs
ns
trA
A port rise times
1
4.2
1.1
4.1
1.1
4.1
1.1
4.1
ns
tfA
A port fall times
1
4.2
1.1
4.1
1.1
4.1
1.1
4.1
ns
trB
B port rise times
0.9
4.5
0.6
3.2
0.5
2.8
0.4
2.7
ns
tfB
B port fall times
0.9
4.5
0.6
3.2
0.5
2.8
0.4
2.7
ns
tsk(o)
Channel-to-channel
0.5
ns
Max data rate
8
VCCB = 1.8 V
± 0.15 V
0.5
60
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60
0.5
60
60
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6.15 VCCA = 2.5 V ± 0.2 V Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
B
1.1
A
1.2
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
6.3
1
5.2
0.9
4.7
6.6
1.1
5.1
0.9
4.4
A
1
1
1
B
1
1
1
A
5.1
21.3
4.6
15.2
4.6
13.2
B
4.4
20.8
3.8
16
3.9
13.9
ns
μs
ns
trA
A port rise times
0.8
3
0.8
3
0.8
3
ns
tfA
A port fall times
0.8
3
0.8
3
0.8
3
ns
trB
B port rise times
0.7
3
0.5
2.8
0.4
2.7
ns
tfB
B port fall times
0.7
3
0.5
2.8
0.4
2.7
ns
tsk(o)
Channel-to-channel
0.5
Max data rate
0.5
100
0.5
100
100
ns
Mbps
6.16 VCCA = 3.3 V ± 0.3 V Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
B
ten
OE
tdis
OE
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
B
0.9
4.7
0.8
4
A
1
4.9
0.9
4.5
A
1
1
B
1
1
A
4.6
15.2
4.3
12.1
B
3.8
16
3.4
13.2
ns
μs
ns
trA
A port rise times
0.7
2.5
0.7
2.5
ns
tfA
A port fall times
0.7
2.5
0.7
2.5
ns
trB
B port rise times
0.5
2.3
0.4
2.7
ns
tfB
B port fall times
0.5
2.3
0.4
2.7
ns
tsk(o)
Channel-to-channel
0.5
ns
Max data rate
0.5
100
100
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6.17 Typical Characteristics
6
25°C (Room Temp)
-40°C
85°C
5
A Port I/O Capacitance (pF)
OE Pin Input Capacitance (pF)
6
4
3
2
1
5
4
3
2
25°C (Room Temp)
-40°C
85°C
1
0
0
0
0.5
1
1.5
2
2.5
3
3.5
0
4
VCCA (V)
0.5
1
1.5
D001
VCCB = 3.3 V
2
2.5
VCCA (V)
3
3.5
4
D002
VCCB = 3.3 V
Figure 1. Input Capacitance for OE pin (CI) vs Power Supply
(VCCA)
Figure 2. Capacitance for A Port I/O Pins (CiO) vs Power
Supply (VCCA)
B Port I/O Capacitance (pF)
12
10
8
6
4
25°C (Room Temp)
-40°C
85°C
2
0
0
0.5
1
1.5
2
2.5
3
VCCB (V)
3.5
4
4.5
5
5.5
D003
VCCA = 1.8 V
Figure 3. Capacitance for B Port I/O Pins (CiO) vs Power Supply (VCCB)
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7 Parameter Measurement Information
2 × VCCO
From Output
Under Test
15 pF
15 pF
1M
Open
50 k
LOAD CIRCUIT FOR
ENABLE/DISABLE
TIME MEASUREMENT
LOAD CIRCUIT FOR MAX DATA RATE,
PULSE DURATION PROPAGATION
DELAY OUTPUT RISE AND FALL TIME
MEASUREMENT
S1
50 k
From Output
Under Test
TEST
S1
tPZL/tPLZ
tPHZ/tPZH
2 × VCCO
Open
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
tPHL
tw
Output
VCCO/2
0.9
VCCO
0.1
VCCO
tr
VOH
VCCI
VCCO/2
tf
VOL
Input
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
A.
B.
C.
D.
E.
F.
G.
VCCI/2
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
VCCI is the VCC associated with the input port.
V CCO is the VCC associated with the output port.
All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuits And Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TXB0102 device is a 4-bit directionless voltage-level translator specifically designed for translating logic
voltage levels. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept
I/O voltages from 1.65V to 5.5V. The device is a buffered architecture with edge rate accelerators (one shots) to
improve the overall data rate. This device can only translate push-pull CMOS logic outputs. If for open drain
signal translation, please refer to TI TXS010X products.
8.2 Functional Block Diagram
VccA
VccB
OE
One
Shot
A1
B1
4 kO
One
Shot
4 kO
One
Shot
B2
A2
4 kO
One
Shot
4 kO
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8.3 Feature Description
8.3.1 Architecture
The TXB0102 architecture (see Figure 5) does not require a direction-control signal to control the direction of
data flow from A to B or from B to A. In a dc state, the output drivers of the TXB0102 can maintain a high or low,
but are designed to be weak, so that they can be overdriven by an external driver when data on the bus starts
flowing the opposite direction. The output one shots detect rising or falling edges on the A or B ports. During a
rising edge, the one shot turns on the PMOS transistors (T1, T3) for a short duration, which speeds up the lowto-high transition. Similarly, during a falling edge, the one shot turns on the NMOS transistors (T2, T4) for a short
duration, which speeds up the high-to-low transition. The typical output impedance during output transition is 70
Ω at VCCO = 1.2 V to 1.8 V, 50 Ω at VCCO = 1.8 V to 3.3 V and 40 Ω at VCCO = 3.3 V to 5 V.
VCCA
VCCB
One
Shot
T1
4k
One
Shot
T2
A
B
One
Shot
T3
4k
T4
One
Shot
Figure 5. Architecture Of TXB0102 I/O Cell
8.3.2 Input Driver Requirements
Figure 6 shows the typical IIN vs VIN characteristics of the TXB0102. For proper operation, the device driving the
data I/Os of the TXB0102 must have drive strength of at least ±2 mA.
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Feature Description (continued)
IIN
VT/4 kΩ
VIN
–(VD – VT)/4 kΩ
A. VT is the input threshold voltage of the TXB0102 (typically VCCI/2.
B. VD is the supply voltage of the external driver.
Figure 6. Typical IIN vs VIN Curve
8.3.3 Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 10 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TXB0102 output sees, so it is recommended that this lumped-load capacitance be
considered to avoid O.S. retriggering, bus contention, output signal oscillations, or other adverse system-level
affects.
8.3.4 Enable and Disable
The TXB0102 has an OE input that is used to disable the device by setting OE = low, which places all I/Os in the
high-impedance (Hi-Z) state. The disable time (tdis) indicates the delay between when OE goes low and when the
outputs actually get disabled (Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the
one-shot circuitry to become operational after OE is taken high.
8.3.5 Pullp or Pulldown Resistors on I/O Lines
The TXB0102 is designed to drive capacitive loads of up to 70 pF. The output drivers of the TXB0102 have low
dc drive strength. If pullup or pulldown resistors are connected externally to the data I/Os, their values must be
kept higher than 50 kΩ to ensure that they do not contend with the output drivers of the TXB0102.
For the same reason, the TXB0102 should not be used in applications such as I2C or 1-Wire where an opendrain driver is connected on the bidirectional data I/O. For these applications, use a device from the TI TXS01xx
series of level translators.
8.4 Device Functional Modes
The TXB0102 device has two functional modes, enabled and disabled. To disable the device set the OE input
low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device.
14
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TXB0102 can be used in level-translation applications for interfacing devices or systems operating at
different interface voltages with one another. It can only translate push-pull CMOS logic outputs. If for open drain
signal translation, please refer to TI TXS010X products. Any external pulldown or pullup resistors are
recommended larger than 50 kΩ.
9.2 Typical Application
1.8V
3.3V
0.1 µF
VccA
0.1 µF
VccB
OE
1.8V
System Controller
3.3V
System
TXB0102
A1
A2
Data
B1
B2
Data
GND
Figure 7. Typical Operating Circuit
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1. And make sure that VCCA ≤ VCCB.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.2 V to 3.6 V
Output voltage range
1.65 V to 5.5 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the TXB0102 device to determine the input voltage
range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value
must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the TXB0102 device is driving to determine the output voltage
range.
– Don’t recommend to have the external pullup or pulldown resistors. If mandatory, it is recommended the
value should be larger than 50 kΩ.
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•
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An external pulldown or pullup resistor decreases the output VOH and VOL. Use Equation 1 and Equation 2 to
draft estimate the VOH and VOL as a result of an external pulldown and pullup resistor.
VOH = VCCx × RPD / (RPD + 4.5 kΩ)
VOL = VCCx × 4.5 kΩ / (RPU + 4.5 kΩ)
(1)
where
•
•
•
•
VCCx is the output port supply voltage on either VCCA or VCCB
RPD is the value of the external pulldown resistor
RPU is the value of the external pullup resistor
4.5 kΩ is the counting the variation of the serial resistor 4 kΩ in the I/O line.
(2)
9.2.3 Application Curve
2 V/div
200 ns/div
VCCA = 1.8 V
VCCB = 3.3 V
Figure 8. Level-Translation of a 2.5-MHz Signal
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10 Power Supply Recommendations
During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not
damage the device, so any power supply can be ramped up first. The TXB0102 has circuitry that disables all
output ports when either VCC is switched off (VCCA/B = 0 V). The output-enable (OE) input circuit is designed so
that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the high-impedance state. To
ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to
GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully ramped and stable. The
minimum value of the pulldown resistor to ground is determined by the current-sourcing capability of the driver.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
• Bypass capacitors should be used on power supplies. And should be placed as close as possible to the VCCA,
VCCB pin and GND pin.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one shot duration, approximately 10 ns, ensuring that any reflection encounters low impedance at the
source driver.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane (Inner Layer)
TXB0102DCTR
To system
To Controller
1
B1
8
B2
2
GND
VCCB
7
3
VCCA
OE
6
4
A2
A1
5
0.1uF
0.1uF
Bypass capacitor
Bypass capacitor
0.1uF
0.1uF
To Controller
Keep OE low until VCCA and
VCCB are powered up
To system
Figure 9. TXB0102 Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
A Guide to Voltage Translation With TXB-Type Translators, SCEA043
12.2 Trademarks
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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17-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TXB0102DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(FD ~ NFDQ ~ NFDR)
NZ
TXB0102DCURG4
ACTIVE
VSSOP
DCU
8
3000
TBD
Call TI
Call TI
-40 to 85
(FD ~ NFDQ ~ NFDR)
NZ
TXB0102DCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(FD ~ NFDQ ~ NFDR)
NZ
TXB0102DCUTG4
ACTIVE
VSSOP
DCU
8
250
TBD
Call TI
Call TI
-40 to 85
(FD ~ NFDQ ~ NFDR)
NZ
TXB0102YZPR
ACTIVE
DSBGA
YZP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(2E ~ 2E2 ~ 2E7 ~
2EN)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TXB0102DCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
TXB0102YZPR
DSBGA
YZP
8
3000
180.0
8.4
1.02
2.02
0.63
4.0
8.0
Q1
TXB0102YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TXB0102DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
TXB0102YZPR
DSBGA
YZP
8
3000
182.0
182.0
20.0
TXB0102YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
D: Max = 1.918 mm, Min =1.858 mm
E: Max = 0.918 mm, Min =0.858 mm
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