Sample & Buy Product Folder Support & Community Tools & Software Technical Documents SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 SN74LVC8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and 3-State Outputs 1 Features 3 Description • This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245 is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes. 1 • • • • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage VCC Isolation Feature – If Either VCC Input Is at GND, All Are in the High-Impedance State Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 4000-V Human-Body Model (A114-A) – 100-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 2 Applications • • • • Personal Electronic Industrial Enterprise Telecom The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by VCCA. Device Information(1) PART NUMBER SN74LVC8T245 PACKAGE BODY SIZE (NOM) SSOP (24) 8.20 mm x 5.30 mm SSOP (24) 8.65 mm x 3.90 mm TSSOP (24) 7.80 mm x 4.40 mm TVSOP (24) 5.00 mm x 4.40 mm VQFN (24) 5.50 mm x 3.50 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Logic Diagram (Positive Logic) DIR 2 22 OE A1 3 21 B1 To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Logic Diagram (Positive Logic) ............................ Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 1 1 1 1 2 3 4 5 Absolute Maximum Ratings ..................................... 5 Handling Ratings ...................................................... 5 Recommended Operating Conditions ...................... 6 Thermal Information DB, DBQ and DGV .................. 7 Thermal Information PW and RHL............................ 7 Electrical Characteristics ......................................... 8 Switching Characteristics, VCCA = 1.8 V ± 0.15 V ... 9 Switching Characteristics, VCCA = 2.5 V ± 0.2 V ..... 9 Switching Characteristics, VCCA = 3.3 V ± 0.3 V ... 10 Switching Characteristics, VCCA = 5 V ± 0.5 V .... 10 Operating Characteristics .................................... 10 8.12 Typical Characteristics .......................................... 11 9 Parameter Measurement Information ................ 12 10 Detailed Description ........................................... 13 10.1 10.2 10.3 10.4 Overview ............................................................... Functional Block Diagram ..................................... Feature Description............................................... Device Functional Modes...................................... 13 13 13 13 11 Application and Implementation........................ 14 11.1 Application Information.......................................... 14 11.2 Typical Application ............................................... 14 12 Power Supply Recommendations ..................... 15 13 Layout................................................................... 16 13.1 Layout Guidelines ................................................. 16 13.2 Layout Example .................................................... 16 14 Device and Documentation Support ................. 17 14.1 Trademarks ........................................................... 17 14.2 Electrostatic Discharge Caution ............................ 17 14.3 Glossary ................................................................ 17 15 Mechanical, Packaging, and Orderable Information ........................................................... 17 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (June 2005) to Revision B Page • Added the list of Application, Pin Functions table, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................................................................................................................................................................. 1 • Changed Feature From: 200-V Machine Model (A115-A) To: 100-V Machine Model (A115-A) ........................................... 1 Changes from Original (June 2005) to Revision A • 2 Page Changed the device From: Product Preview To: Production ................................................................................................. 1 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 6 Description (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, all outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 3 SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 www.ti.com 7 Pin Configuration and Functions 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCCB VCCB OE B1 B2 B3 B4 B5 B6 B7 B8 GND DIR A1 A2 A3 A4 A5 A6 A7 A8 GND VCCB 1 1 24 23 VCCB 22 OE 21 B1 2 3 4 6 20 B2 19 B3 7 8 18 B4 17 B5 9 10 16 B6 15 B7 5 14 B8 11 GND 12 13 GND VCCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND VCCA RHL PACKAGE (TOP VIEW) DB, DBQ, DGV, OR PW PACKAGE (TOP VIEW) Pin Functions PIN NAME NO. I/O DESCRIPTION A1 3 I/O Input/output A1. Referenced to VCCA. A2 4 I/O Input/output A2. Referenced to VCCA. A3 5 I/O Input/output A3. Referenced to VCCA. A4 6 I/O Input/output A4. Referenced to VCCA. A5 7 I/O Input/output A5. Referenced to VCCA. A6 8 I/O Input/output A6. Referenced to VCCA. A7 9 I/O Input/output A7. Referenced to VCCA. A8 10 I/O Input/output A8. Referenced to VCCA. B1 21 I/O Input/output B1. Referenced to VCCB. B2 20 I/O Input/output B2. Referenced to VCCB. B3 19 I/O Input/output B3. Referenced to VCCB. B4 18 I/O Input/output B4. Referenced to VCCB. B5 17 I/O Input/output B5. Referenced to VCCB. B6 16 I/O Input/output B6. Referenced to VCCB. B7 15 I/O Input/output B7. Referenced to VCCB. B8 14 I/O Input/output B8. Referenced to VCCB. DIR 2 I Direction-control signal. GND 11, 12, 13 G Ground 22 I 3-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referenced to VCCA. VCCA 1 P A-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V VCCB 23, 24 P B-port supply voltage. 1.65 V ≤ VCCA ≤ 5.5 V OE 4 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 8 Specifications 8.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX –0.5 6.5 I/O ports (A port) –0.5 6.5 I/O ports (B port) –0.5 6.5 Control inputs –0.5 6.5 A port –0.5 6.5 B port –0.5 6.5 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 Supply voltage range, VCCA, VCCB Input voltage range (2) VI UNIT V V VO Voltage range applied to any output in the high-impedance or power-off state (2) VO Voltage range applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA (3) Continuous current through each VCCA, VCCB, and GND (1) (2) (3) V V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed. 8.2 Handling Ratings MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) –4000 4000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) –1000 1000 Tstg Storage temperature range V(ESD) Electrostatic discharge (1) (2) V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 5 SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 www.ti.com 8.3 Recommended Operating Conditions (1) (2) (3) (4) VCCI VCCA VCCB VCCO Supply voltage 1.65 V to 1.95 V High-level input voltage VIH MAX 5.5 1.65 5.5 1.7 3 V to 3.6 V VCCI × 0.7 1.65 V to 1.95 V VIL Data inputs (5) VCCI × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 4.5 V to 5.5 V High-level input voltage Control inputs (referenced to VCCA) (6) V VCCI × 0.3 1.65 V to 1.95 V VIH V V 2 4.5 V to 5.5 V Low-level input voltage UNIT VCCI × 0.65 2.3 V to 2.7 V Data inputs (5) MIN 1.65 VCCA × 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V V 2 4.5 V to 5.5 V VCCA × 0.7 1.65 V to 1.95 V VCCA × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 VIL Low-level input voltage Control inputs (referenced to VCCA) (6) VI Input voltage Control inputs 0 5.5 V VI/O Input/output voltage Active state 0 VCCO V 3-State 0 5.5 V 4.5 V to 5.5 V IOH High-level output current VCCA × 0.3 1.65 V to 1.95 V –4 2.3 V to 2.7 V –8 3 V to 3.6 V –24 4.5 V to 5.5 V –32 1.65 V to 1.95 V IOL Low-level output current Δt/Δv TA (1) (2) (3) (4) (5) (6) 6 Input transition rise or fall rate Data inputs V 4 2.3 V to 2.7 V 8 3 V to 3.6 V 24 4.5 V to 5.5 V 32 1.65 V to 1.95 V 20 2.3 V to 2.7 V 20 3 V to 3.6 V 10 4.5 V to 5.5 V 5 Operating free-air temperature mA –40 85 mA ns/V °C VCCI is the VCC associated with the data input port. VCCO is the VCC associated with the output port. All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. All unused control inputs must be held at VCCA or GND to ensure proper device operation and minimize power comsumption. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 8.4 Thermal Information DB, DBQ and DGV THERMAL METRIC (1) DB DBQ DGV 24 PINS 24 PINS 24 PINS RθJA Junction-to-ambient thermal resistance 88.5 81.2 91.1 RθJC(top) Junction-to-case (top) thermal resistance 48.7 44.8 23.7 RθJB Junction-to-board thermal resistance 44.1 34.5 44.5 ψJT Junction-to-top characterization parameter 12.8 9.5 0.6 ψJB Junction-to-board characterization parameter 43.6 37.2 44.1 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 8.5 Thermal Information PW and RHL THERMAL METRIC (1) PW RHL 24 PINS 24 PINS RθJA Junction-to-ambient thermal resistance 90.6 37.4 RθJC(top) Junction-to-case (top) thermal resistance 27.6 38.1 RθJB Junction-to-board thermal resistance 45.3 15.2 ψJT Junction-to-top characterization parameter 1.3 0.7 ψJB Junction-to-board characterization parameter 44.8 15.2 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 4.3 (1) UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 7 SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 Electrical Characteristics (1) 8.6 www.ti.com (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL VCCA VCCB IOH = –100 μA, TEST CONDITIONS VI = VIH 1.65 V to 4.5 V 1.65 V to 4.5 V IOH = –4 mA, VI = VIH 1.65 V 1.65 V 1.2 IOH = –8 mA, VI = VIH 2.3 V 2.3 V 1.9 IOH = –24 mA, VI = VIH 3V 3V 2.4 IOH = –32 mA, VI = VIH 4.5 V 4.5 V 3.8 IOL = 100 μA, VI = VIL 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 IOL = 4 mA, VI = VIL 1.65 V 1.65 V 0.45 IOL = 8 mA, VI = VIL 2.3 V 2.3 V 0.3 IOL = 24 mA, VI = VIL 3V 3V 0.55 IOL = 32 mA, VI = VIL 4.5 V 4.5 V 0.55 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 0V 0 to 5.5 V ±1 ±2 0 to 5.5 V 0V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V 15 5V 0V 15 0V 5V –2 1.65 V to 5.5 V 1.65 V to 5.5 V 15 5V 0V –2 0V 5V 15 1.65 V to 5.5 V 1.65 V to 5.5 V 25 II DIR Ioff A or B port VI or VO = 0 to 5.5 V IOZ A or B port VO = VCCO or GND, OE = VIH ICCA VI = VCCA or GND VI = VCCI or GND, ICCB VI = VCCI or GND, ICCA + ICCB VI = VCCI or GND, IO = 0 IO = 0 IO = 0 A port One A port at VCCA – 0.6 V, DIR at VCCA, B port = open DIR DIR at VCCA – 0.6 V, B port = open, A port at VCCA or GND ΔICCB B port One B port at VCCB – 0.6 V, DIR at GND, A port = open Ci Control inputs Cio A or B port ΔICCA (1) (2) 8 MIN TYP MAX MIN MAX UNIT VCCO – 0.1 V V μA μA μA μA μA μA 50 3 V to 5.5 V μA 3 V to 5.5 V 50 3 V to 5.5 V 3 V to 5.5 V VI = VCCA or GND 3.3 V 3.3 V VO = VCCA/B or GND 3.3 V 3.3 V 50 μA 4 5 pF 8.5 10 pF VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com 8.7 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 Switching Characteristics, VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL 8.8 VCCB = 1.8 V ± 0.15 V FROM (INPUT) TO (OUTPUT) A B 1.7 B A OE MIN MAX VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX 21.9 1.3 9.2 1 7.4 0.8 7.1 ns 0.9 23.8 0.8 23.6 0.7 23.4 0.7 23.4 ns A 1.5 29.6 1.5 29.4 1.5 29.3 1.4 29.2 ns OE B 2.4 32.2 1.9 13.1 1.7 12 1.3 10.3 ns OE A 0.4 24 0.4 23.8 0.4 23.7 0.4 23.7 ns OE B 1.8 32 1.5 16 1.2 12.6 0.9 10.8 ns Switching Characteristics, VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL FROM (INPUT) TO (OUTPUT) A VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX B 1.5 21.4 1.2 9 0.8 6.2 0.6 4.8 ns B A 1.2 9.3 1 9.1 1 8.9 0.9 8.8 ns OE A 1.4 9 1.4 9 1.4 9 1.4 9 ns OE B 2.3 29.6 1.8 11 1.7 9.3 0.9 6.9 ns OE A 1 10.9 1 10.9 1 10.9 1 10.9 ns OE B 1.7 28.2 1.5 12.9 1.2 9.4 1 6.9 ns Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 9 SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 8.9 www.ti.com Switching Characteristics, VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL 8.10 VCCB = 1.8 V ± 0.15 V FROM (INPUT) TO (OUTPUT) A B 1.5 B A OE VCCB = 2.5 V ± 0.2 V MIN MAX VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX 21.2 1.1 8.8 0.8 6.3 0.5 4.4 ns 0.8 7.2 0.8 6.2 0.7 6.1 0.6 6 ns A 1.6 8.2 1.6 8.2 1.6 8.2 1.6 8.2 ns OE B 2.1 29 1.7 10.3 1.5 8.6 0.8 6.3 ns OE A 0.8 8.1 0.8 8.1 0.8 8.1 0.8 8.1 ns OE B 1.8 27.7 1.4 12.4 1.1 8.5 0.9 6.4 ns Switching Characteristics, VCCA = 5 V ± 0.5 V over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL 8.11 FROM (INPUT) TO (OUTPUT) A VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX UNIT MIN MAX MIN MAX MIN MAX B 1.5 21.4 1 8.8 0.7 6 0.4 4.2 ns B A 0.7 7 0.4 4.8 0.3 4.5 0.3 4.3 ns OE A 0.3 5.4 0.3 5.4 0.3 5.4 0.3 5.4 ns OE B 2 28.7 1.6 9.7 1.4 8 0.7 5.7 ns OE A 0.7 6.4 0.7 6.4 0.7 6.4 0.7 6.4 ns OE B 1.5 27.6 1.3 11.4 1 8.1 0.9 6 ns Operating Characteristics TA = 25°C PARAMETER CpdA CpdB (1) 10 (1) A-port input, B-port output B-port input, A-port output (1) TEST CONDITIONS A-port input, B-port output CL = 0, f = 10 MHz, tr = tf = 1 ns B-port input, A-port output VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V VCCA = VCCB = 5 V TYP TYP TYP TYP 2 2 2 3 12 13 13 16 13 13 14 16 2 2 2 3 UNIT pF Power dissipation capacitance per transceiver Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 1.4 5.6 1.2 5.4 1.0 5.2 VOH Voltage (V) VOL Voltage (V) 8.12 Typical Characteristics 0.8 0.6 0.4 4.8 4.6 o -40 C o 25 C 0.2 5.0 o -40 C o 25 C 4.4 o o 85 C 85 C 4.2 0 0 20 40 60 80 100 0 -20 -40 -60 -80 IOL Current (mA) IOH Current (mA) Figure 1. Voltage vs Current Figure 2. Voltage vs Current -100 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 11 SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 www.ti.com 9 Parameter Measurement Information 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 10 Detailed Description 10.1 Overview The SN74LVC8T245 is an 8-bit, dual supply non-inverting voltage level translation. Pin Ax and direction control pin are support by VCCA and pin Bx is support by VCCB. The A port is able to accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A. 10.2 Functional Block Diagram DIR 2 22 OE A1 3 21 B1 To Seven Other Channels Figure 4. Logic Diagram (Positive Logic) 10.3 Feature Description 10.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5 V making the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V, 3.3 V and 5 V). 10.3.2 Ioff Supports Partial-Power-Down Mode Operation Ioff prevents backflow current by disabling I/O output circuits when device is in partial-power-down mode. 10.4 Device Functional Modes The SN74LVC8T245 is voltage level translator that can operate from 1.65 V to 5.5 V (VCCA) and 1.65 V to 5.5 V (VCCB). The signal translation between 1.65 V and 5.5 V requires direction control and output enable control. When OE is low and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data transmission is from B to A. When OE is high, both output ports will be high-impedance. Table 1. Function Table (1) (Each 8-Bit Section) CONTROL INPUTS (1) OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os are always active. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 13 SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 www.ti.com 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 11.1 Application Information The SN74LVC8T245 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The maximum output current can be up to 32 mA when device is powered by 5 V. 11.2 Typical Application 1.8V 5V 0.1 F 0.1 F VCCA 1 µF VCCB DIR OE 1.8V Controller Data GND 5V System SN74LVC8T245 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 Data GND GND Figure 5. Typical Application Circuit 14 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 Typical Application (continued) 11.2.1 Design Requirements For this design example, use the parameters listed in Table 2. Table 2. Design Parameters PARAMETERS VALUES Input voltage range 1.65 V to 5.5 V Output voltage 1.65 V to 5.5 V 11.2.2 Detailed Design Procedure To begin the design process, determine the following: • Input voltage range – Use the supply voltage of the device that is driving the SN74LVC8T245 device to determine the input voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the value must be less than the VIL of the input port. • Output voltage range – Use the supply voltage of the device that the SN74LVC8T245 device is driving to determine the output voltage range. 11.2.3 Application Curve Voltage (V) Output (5 V) Input (1.8 V) Time (200 ns/div) Figure 6. Translation Up (1.8 V to 5 V) at 2.5 MHz 12 Power Supply Recommendations The SN74LVC8T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.65 V to 5.5 V and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port and B port are designed to track VCCA and VCCB respectively allowing for low-voltage bidirectional translation between any of the 1.8-V, 2.5 -V, 3.3-V and 5-V voltage nodes. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 15 SN74LVC8T245 SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 www.ti.com 13 Layout 13.1 Layout Guidelines To • • • ensure reliability of the device, following common printed-circuit board layout guidelines is recommended. Bypass capacitors should be used on power supplies. Short trace lengths should be used to avoid excessive loading. Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of signals depending on the system requirements. 13.2 Layout Example LEGEND VIA to Power Plane Polygonal Copper Pour VIA to GND Plane (Inner Layer) VCCB VCCA Bypass Capacitor Bypass Capacitor VCCA 1 VCCA VCCB 16 2 DIR VCCB 15 From Controller 3 A1 OE 14 From Controller 4 A2 B1 13 To System From Controller 5 A3 B2 12 To System From Controller 6 A4 B3 11 To System From Controller 7 A5 B4 10 To System From Controller 8 A6 B5 12 To System From Controller 9 A7 B6 11 To System From Controller 10 A8 B7 10 To System 11 GND B8 10 To System 12 GND GND 13 Keep OE high until VCCA and VCCB are powered up SN74LVC8T245 Figure 7. SN74LVC8T245 Layout 16 Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 SN74LVC8T245 www.ti.com SCES584B – JUNE 2005 – REVISED NOVEMBER 2014 14 Device and Documentation Support 14.1 Trademarks All trademarks are the property of their respective owners. 14.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 14.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2005–2014, Texas Instruments Incorporated Product Folder Links: SN74LVC8T245 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 74LVC8T245DBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC8T245 74LVC8T245RHLRG4 ACTIVE VQFN RHL 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 NH245 SN74LVC8T245DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LVC8T245 SN74LVC8T245DBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245DBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC8T245 SN74LVC8T245DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC8T245 SN74LVC8T245NSR ACTIVE SO NS 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC8T245 SN74LVC8T245PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NH245 SN74LVC8T245RHLR ACTIVE VQFN RHL 24 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 NH245 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVC8T245 : • Automotive: SN74LVC8T245-Q1 • Enhanced Product: SN74LVC8T245-EP Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVC8T245DBQR Package Package Pins Type Drawing SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVC8T245DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74LVC8T245DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74LVC8T245DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74LVC8T245RHLR VQFN RHL 24 1000 180.0 12.4 3.8 5.8 1.2 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC8T245DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 SN74LVC8T245DBR SSOP DB 24 2000 367.0 367.0 38.0 SN74LVC8T245DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74LVC8T245DWR SOIC DW 24 2000 367.0 367.0 45.0 SN74LVC8T245RHLR VQFN RHL 24 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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