CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 1/12 5V/12V Synchronous Buck PWM Controller EM5303/A General Description EM5303/A is a synchronous rectified PWM controller operating with 5V or 12V supply voltage. This device operates at 200/300 kHz and provides an optimal level of integration to reduce size and cost of the power supply. This part includes internal soft start, internal compensation networks, over current protection, under voltage protection, and shutdown function. This part is available in PSOP-8 package. Features z z z z z z z z z z z Operate from 5V to 12V Voltage Supply 0.6V VREF with 1.5% Accuracy Voltage Mode PWM Control 200kHz or 300kHz Fixed Frequency Oscillator 0% to 80% Duty Cycle Internal Soft Start Over Current Protection Integrated Bootstrap Diode Adaptive Non-Overlapping Gate Driver Under Voltage Protection Over Voltage Protection Applications z z z Notebook & Netbook Graphic Cards & MB Low Voltage Logic Supplies Ordering Information Part Number Package Frequency EM5303QP PSOP-8 200kHz EM5303AQP PSOP-8 300kHz EM5303QP CYStek Product Specification CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 2/12 Pin Configuration Typical Application Circuit Pin Assignment Pin Pin No. Name BOOT 1 UGATE 2 GND 3 EM5303QP Pin Function Bootstrap Supply for the floating upper gate driver. Connect the bootstrap capacitor C BOOT between BOOT pin and the PHASE pin to form a bootstrap circuit. The bootstrap capacitor provides the charge to turn on the upper MOSFET. Typical values for C BOOT range from 0.1uF to 0.47uF. Ensure that C BOOT is placed near the IC. Upper Gate Driver Output. Connect this pin to the gate of upper MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. Signal and Power Ground for the IC. All voltages levels are measured with respect to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. CYStek Product Specification Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 3/12 CYStech Electronics Corp. LGATE 4 VCC 5 FB 6 EN 7 PHASE 8 Lower Gate Driver Output. Connect this pin to the gate of lower MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turn off. Supply Voltage. This pin provides the bias supply for the EM5303/A and the lower gate driver. The supply voltage is internally regulated to 4VDD for internal control circuit. Connect a well-decoupled 4.5V to 13.2V supply voltage to this pin. Ensure that a decoupling capacitor is placed near the IC. Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from the output to GND is used to set the regulation voltage. Enable Pin. Pulling this pin lower than 0.3V disables the controller and causes the oscillator to stop, the UGATE and LGATE outputs to be held low. PHASE Switch Node. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is used as the sink for the UGATE driver, and to monitor the voltage drop across the lower MOSFET for over current protection. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. A Schottky diode between this pin and ground is recommended to reduce negative transient voltage which is common in a power supply system. Function Block Diagram VCC 5 Internal regulator Soft Start POR - 6 PWM - EA + BOOT 2 UGATE 8 PHASE OTP FB 1 Ramp Gate control logic VOCP VCC VCC Reference Oscillator 17V 4 LGATE 75% Vref EN 7 Enable 0.3V FB 3 GND FB 130% Vref EM5303QP CYStek Product Specification Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 4/12 CYStech Electronics Corp. Absolute Maximum Ratings (Note 1) z Supply voltage, VCC--------------------------------------------------------- -0.3V to 16V z PHASE to GND z z z z z z z z z z z DC------------------------------------------------------------------------------- -5V to 16V <200nS------------------------------------------------------------------------- -10V to 32V BOOT to PHASE------------------------------------------------------------------------ 16V BOOT to GND DC--------------------------------------------------------------------- -0.3V to PHASE+16V <200nS------------------------------------------------------------------------- -0.3V to 42V UGATE------------------------------------------------------- PHASE – 0.3V to BOOT + 0.3V LGATE----------------------------------------------------------------- -0.3V to VCC + 0.3V EN & FB-------------------------------------------------------------------------- -0.3V to 6V Power Dissipation, PD @ TA = 25°C, PSOP-8 -------------------------------------- 0.625W Package Thermal Resistance, ΘJA, PSOP-8 (Note 2)-------------------------- 160°C/W Junction Temperature--------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.)-------------------------------------------- 260°C Storage Temperature Range----------------------------------------------- 65°C to 150°C ESD susceptibility (Note3) HBM (Human Body Mode)------------------------------------------------------------ 2KV MM (Machine Mode)----------------------------------------------------------------- 200V Recommended Operating Conditions (Note5) z Supply Voltage, VCC ------------------------------------------------------- 4.5V to 13.2V z Junction Temperature --------------------------------------------------- -40°C to 125°C z Ambient Temperature ---------------------------------------------------- -40°C to 85°C Electrical Characteristics VCC=12V, TA=25℃, unless otherwise specified Parameter Symbol Test Conditions Pin Min Typ Max Units 13.2 V Supply Input Section Supply Voltage VCC Supply Current ICC Quiescent Supply Current Power on Reset Threshold Power on Reset Hysteresis Internal Oscillator ICCQ VCCRTH VCCHYS Free Running Frequency FSW Ramp Amplitude Error Amplifier Open Loop DC Gain Gain-Bandwidth Product Slew Rate Trans-conductance △VOSC EM5303QP AO GBW SR gm 5 LGATE, UGATE open, Switching. No Switching. 4.5 5 5 5 5 3 2 4.2 0.2 4 EM5303 EM5303A 170 255 200 300 1 Guaranteed by Design Guaranteed by Design Guaranteed by Design Guaranteed by Design 55 70 10 6 0.2 3 mA 4.4 230 345 0.7 mA V V KHz KHz Vp-p dB MHz V/uS mS CYStek Product Specification CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 5/12 PWM Controller Gate Drivers Upper Gate Sourcing Current IUG_SRC Upper Gate Sinking Current IUG_SNK Upper Gate RDS(ON) Sinking RUG_SNK VBOOT - VPHASE = 12V, VBOOT - VUGATE = 6V VBOOT - VPHASE = 12V, VUGATE – VPHASE = 6V VBOOT - VPHASE = 12V, VUGATE – VPHASE = 0.1V VCC – VLGATE = 6V VLGATE = 6V VLGATE = 0.1V VCC = 12V; VPHASE < 1.2V to VLGATE > 1.2V VCC = 12V; VLGATE < 1.2V to (VUGATE - VPHASE) > 1.2V Lower Gate Sourcing Current ILG_SRC Lower Gate Sinking Current ILG_SNK Lower Gate RDS(ON) Sinking RLG_SNK PHASE Falling to LGATE Rising Delay LGATE Falling to UGATE Rising Delay Reference Voltage Nominal Feedback Voltage VFB Enable Voltage EN Enable Threshold VEN Protection section FB Under Voltage Protection VFB_UVP FB falling FB Over Voltage Protection VFB_OVP FB rising VCC Over Voltage Protection VCC_OVP Over Current Threshold VOCP Soft-Start Interval TSS Temperature Shutdown TSD Guaranteed by Design Note 1. Note 2. Note 3. Note 4. Note 5. 2 -1 A 2 1.5 A 2 2 4 4 4 6 0.591 7 6 6 5 55 115 16 -425 2.4 150 4 Ω -1 1.5 2 4 A A Ω 30 90 nS 30 90 ns 0.6 0.609 V 0.3 0.35 V 65 130 17 -375 3.6 165 75 145 18 -325 5.4 % % V mV mS ℃ Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. θJA is measured in the natural convection at TA=25oC on a 4-layers high effective thermal conductivity test board with minimum copper area of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for PSOP-8 package. θJA PSOP-8 packages is 52°C /W on JEDEC 51-7 (4 layers,2S2P) thermal test board with 50mm2 copper area. Devices are ESD sensitive. Handling precaution is recommended. The device is not guaranteed to function outside its operating conditions. EM5303QP CYStek Product Specification CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 6/12 Typical Operating Characteristics Power On Waveform Turn On from EN VIN VEN VOUT VOUT Phase Phase ILx ILx VIN=12V，VOUT=1.2V，COUT=1000uF，No Load. VIN=12V，VOUT=1.2V，COUT=1000uF，No Load. Turn Off from EN Switching Waveforms: UGATE Turn On VOUT UGATE VEN PHASE Phase UGATE - PHASE ILx LGATE VIN=12V，VOUT=1.2V，COUT=1000uF，IOUT=6A. VIN=12V，IOUT=10A Switching Waveforms: UGATE Turn Off Power Sequencing Operation UGATE VIN PHASE VOUT Phase LGATE Phase VIN=12V，IOUT=10A EM5303QP VCC =12V Ready，VOUT = 1.2V, COUT = 1000uF, No Load. CYStek Product Specification CYStech Electronics Corp. Load Transient Response Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 7/12 Over Current Protection IOUT Phase VOUT VOUT Phase IOUT VIN=12V, VOUT=1.2V, COUT=1000uF. Output short Ground Over Current Protection Load Regulation Output Voltage Deviation (%) VIN=12V，VOUT=1.2V，COUT=1000uF. Phase VOUT IOUT VIN=12V, VOUT=1.2V, COUT=1000uF. Turn On to Short Circuit Output current (A) Output Voltage Deviation (%) Input Voltage (V) EM5303QP Switching Frequency vs. Input Voltage Switching Frequency Deviation (%) Line Regulation Input Voltage (V) CYStek Product Specification CYStech Electronics Corp. Junction Temperature (℃) EM5303QP Output Voltage vs. Junction Temperature Output Voltage Deviation (%) Switching Frequency Deviation (%) Switching Frequency vs. Junction Temperature Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 8/12 Junction Temperature (℃) CYStek Product Specification CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 9/12 Functional Description EM5303/A is a voltage mode synchronous buck PWM controller. The compensation circuit is implemented internally to minimize the external component count. This device provides complete protection function such as over current protection, under voltage protection and over voltage protection. Supply Voltage The VCC pin provides the bias supply of EM5303/A control circuit, as well as lower MOSFET’s gate and the BOOT voltage for the upper MOSFET’s gate. A minimum 0.1uF ceramic capacitor is recommended to bypass the supply voltage. Power ON Reset To let EM5303/A start to operation, VCC voltage must be higher than its POR voltage even when EN voltage is pulled higher than enable high voltage. Typical POR voltage is 4.2V. Enable To let EM5303/A start to operation, EN voltage must be higher than its enable voltage. Typical enable voltage is 0.3V. Soft Start EM5303/A provides soft start function internally. The FB voltage will track the internal soft start signal, which ramps up from zero during soft start period. OCP, Over Current Protection The over current function protects the converter from a shorted output by using lower MOSFET’s on-resistance to monitor the current. The OCP level can be calculated as the following equation: IOCP = − VOCP RDS(ON) When OCP is triggered, EM5303/A will shut down the converter and cycles the soft start function in a hiccup mode. If over current condition still exist after 3 times of hiccup, EM5303/A will shut down the controller and latch. UVP, Under Voltage Protection The FB voltage is monitored for under voltage protection. The UVP threshold is typical 0.4V. When UVP is triggered, EM5303/A will shut down the converter and cycles the soft start function in a hiccup mode. OVP, Over Voltage Protection The FB voltage is monitored for over voltage protection. The OVP threshold is typical 0.8V. When OVP is triggered, EM5303/A will turn off upper MOSFET and turn on lower MOSFET. Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the response time to the load transient. The inductor value determines the current ripple and voltage ripple. The ripple current is approximately the following equation: ΔIL = VIN − VOUT V ∗ OUT L VIN * FSW EM5303QP CYStek Product Specification CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 10/12 Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient. The selection of output capacitor depends on the output ripple voltage. The output ripple voltage is approximately bounded by the following equation: Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFET. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper MOSFET turn on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of the upper MOSFET and the source of the lower MOSFET. The important parameters of the input capacitor are the voltage rating and the RMS current rating. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement can be expressed as the following equation: IRMS = IOUT D(1- D) For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can also be used but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. Power MOSFET Selection The EM5303/A requires two N-Channel power MOSFETs. These should be selected based upon on-resistance, breakdown voltage, gate supply requirement, and thermal management requirements. In high current applications, the MOSFET power dissipation, package selection and heat sink are the dominate design factor. The power dissipation includes two loss components: conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The power dissipations in the two MOSFETs are approximately the following equation: PDUPPER= I2OUT* RDS(ON)* D + 0.5 * IOUT * VIN * FSW * t SW PDLOWER= I2OUT * RDS(ON)* (1 - D) Where D is the duty cycle, tSW is the combined switch ON and OFF time. EM5303QP CYStek Product Specification CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 11/12 Recommended wave soldering condition Product Pb-free devices Peak Temperature 260 +0/-5 °C Soldering Time 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Average ramp-up rate (Tsmax to Tp) Preheat −Temperature Min(TS min) −Temperature Max(TS max) −Time(ts min to ts max) Time maintained above: −Temperature (TL) − Time (tL) Peak Temperature(TP) Time within 5°C of actual peak temperature(tp) Ramp down rate Time 25 °C to peak temperature Sn-Pb eutectic Assembly Pb-free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 240 +0/-5 °C 217°C 60-150 seconds 260 +0/-5 °C 10-30 seconds 20-40 seconds 6°C/second max. 6 minutes max. 6°C/second max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface. EM5303QP CYStek Product Specification CYStech Electronics Corp. Spec. No. : C551QP Issued Date : 2010.10.25 Revised Date : Page No. : 12/12 PSOP-8 Dimension Marking: Device Name Date Code Device Name Date Code 8-Lead PSOP-8 Plastic Surface Mounted Package CYStek Package Code: QP *:Typical Inches Min. Max. 0.1850 0.2008 0.1457 0.1614 0.2283 0.2441 0.0130 0.0200 0.05* 0.0472 0.0638 0.0032 0.0110 DIM A B C D E F G Millimeters Min. Max. 4.70 5.10 3.70 4.10 5.80 6.20 0.33 0.51 1.27 * 1.20 1.62 0.08 0.28 DIM H I J K M N Inches Min. Max. 0.0157 0.0327 0.0075 0.0102 0.0098 0.0197 0° 8° 0.0764 0.0980 0.0764 0.0980 Millimeters Min. Max. 0.40 0.83 0.19 0.26 0.25 0.50 0° 8° 1.94 2.49 1.94 2.49 Notes : 1.Controlling dimension : millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material : • Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0 Important Notice: • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek. • CYStek reserves the right to make changes to its products without notice. • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems. • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. EM5303QP CYStek Product Specification