APW8722/A/B/C/D 5V to 12V Single Buck Voltage Mode PWM Controller Features General Description • Wide 5V to 12V Supply Voltage The APW8722 is a voltage mode, fixed 200kHz/300kHz/ • Power-On-Reset Monitoring on VCC • Excellent Output Voltage Regulations 600kHz switching frequency, synchronous buck converter. The APW8722 allows wide input voltage that is either a single 5~12V or two supply voltage(s) for various applications. A power-on-reset (POR) circuit monitors the - 0.6V Internal Reference for APW8722/A/D - 0.8V Internal Reference for APW8722B/C - ±0.6% Over-Temperature Range • Integrated Soft-Start • Voltage Mode PWM Operation with External VCC supply voltage to prevent wrong logic controls. A builtin soft-start circuit prevents the output voltages from overshoot as well as limits the input current. An internal 0.6V temperature-compensated reference voltage with high Compensation • Up to 90% Duty Ratio for Fast Transient Response • Constant Switching Frequency accuracy is designed to meet the requirement of low output voltage applications. The APW8722 provides excellent output voltage regulations against load current variation. The controller’s over-current protection monitors the out- - 300kHz ±10% for APW8722/B - 200kHz ±10% for APW8722C - 600kHz ±10% for APW8722A/D • Integrated Bootstrap Forward P-CH MOSFET • 50% Under-Voltage Protection • 125% Over-Voltage Protection • Adjustable Over-Current Protection Threshold put current by using the voltage drop across the RDS (ON) of low-side MOSFET, eliminating the need for a current sensing resistor that features high efficiency and low cost. In addition, the APW8722 also integrates excellent protection functions. The over-voltage protection (OVP) , under-voltage protection (UVP). OVP circuit which moni- - Using the RDS(ON) of Low-Side MOSFET • Shutdown Control by COMP • SOP-8P Package • Lead Free and Green Devices Available tors the FB voltage to prevent the PWM output from over voltage, and UVP circuit which monitors the FB voltage to prevent the PWM output from under voltage or short circuit. The APW8722 is available in SOP-8P packages (RoHS Compliant) Applications • • DSL, Switch HUB • Wireless Lan • Notebook Computer Graphic Cards • Mother Board • LCD Monitor/TV ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 1 www.anpec.com.tw APW8722/A/B/C/D Simplified Application Circuit VVCC VIN 5 7 OFF BOOT VCC COMP UGATE APW8722 ON PHASE LGATE 6 1 2 VOUT 8 4 FB GND 3 Ordering and Marking Information APW8722/A/B/C/D Assembly Material Handling Code Temperature Range Package Code APW8722/A/B/C/D APW8722X XXXXX KA : X – A/B/C/D Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration APW8722A APW8722/B/C/D BOOT 1 UGATE 2 GND 3 LGATE/OCSET 4 9 GND 8 7 6 5 BOOT 1 UGATE 2 OCSET 3 LGATE 4 PHASE COMP FB VCC PHASE COMP FB VCC SOP-8P (top view) SOP-8P (top view) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 9 GND 8 7 6 5 2 www.anpec.com.tw APW8722/A/B/C/D Absolute Maximum Ratings (Note 1) Symbol VVCC VBOOT Rating Unit VCC Supply Voltage (VCC to GND) Parameter -0.3 ~ 16 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 16 V BOOT Supply Voltage (BOOT to GND) -0.3 ~ 32 V VUGATE UGATE Voltage (UGATE to PHASE) VLGATE LGATE Voltage (LGATE to GND) VPHASE PHASE Voltage (PHASE to GND) > 20ns -0.3 ~ VBOOT+0.3 V < 20ns -5 ~ VBOOT+5 V > 20ns -0.3 ~ VVCC+0.3 V < 20ns -5 ~ VVCC+5 V > 20ns -0.3 ~ 16 V < 20ns -5 ~ 25 V FB ,COMP to GND POK to GND TJ Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds -0.3 ~ 7 V -0.3~VCC+0.3 V 150 °C -65 ~ 150 °C 260 °C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Thermal Resistance -Junction to Ambient Typical Value Unit (Note 2) SOP-8P °C/W 60 Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol Range Unit 4.5 ~ 13.2 V Converter Output Voltage for APW8722/A/D 0.6 ~ 5 V Converter Output Voltage for APW8722B/C 0.8 ~ 5 V VIN Converter Input Voltage 3~13.2 V IOUT Converter Output Current 0 ~ 25 A TA Ambient Temperature -40 ~ 85 °C TJ Junction Temperature -40 ~ 125 °C VVCC VOUT Parameter VCC Supply Voltage (VCC to GND) Note 3: Refer to the application circuit for further information. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 3 www.anpec.com.tw APW8722/A/B/C/D Electrical Characteristics Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise noted. Typical values are at TA = 25°C. Symbol Parameter APW8722 Test Conditions Unit Min. Typ. Max. INPUT SUPPLY VOLTAGE AND CURRENT IVCC VCC Supply Current (Shutdown Mode) UGATE and LGATE open; COMP=GND - - 550 µA VCC Supply Current UGATE and LGATE open - 2.5 10 mA Rising VCC POR Threshold 3.8 4.1 4.4 V VCC POR Hysteresis 0.3 0.5 0.6 V For APW8722/B 270 300 330 For APW8722C 180 200 220 For APW8722A/D 540 600 660 (1.2V~2.7V typical) - 1.5 - V - - 90 % POWER-ON-RESET(POR) OSCILLATOR FOSC Oscillator Frequency ∆VOSC Oscillator Sawtooth Amplitude DMAX Maximum Duty Cycle (Note 4) kHz REFERENCE VREF APW8722/A/D Reference Voltage TA = -40 ~ 85°C 0.596 0.6 0.604 APW8722B/C Reference Voltage TA = -40 ~ 85°C 0.795 0.8 0.805 V ERROR AMPLIFIER Open-Loop GAIN (Note 4) RL = 10kΩ, CL = 10pF - 90 - dB Open-Loop Bandwidth (Note 4) RL = 10kΩ, CL = 10pF - 20 - MHz FB Input Leakage Current VFB = 0.6V - - 0.1 µA High-side Gate Driver Source Current VBOOT= 12V, VUGATE-PHASE = 6V - 1.0 - High-side Gate Driver Sink Current VBOOT= 12V, VUGATE-PHASE = 6V - 1.1 - Low-side Gate Driver Source Current VVCC = 12V, VLGATE-GND = 6V - 1.8 - Low-side Gate Driver Sink Current VVCC = 12V, VLGATE-GND = 6V - 2.0 - - 30 - GATE DRIVERS TD Dead-time (Note 4) A ns PROTECTIONS VFB_UV VFB_OV 45 50 55 % Under-Voltage Debounce Interval FB Under-Voltage Protection Trip Point Percentage of VREF - 2 - µs Under-Voltage Protection Enable Delay - 1.5 - ms FB Over-Voltage Protection Rising Threshold VFB rising 120 125 130 % FB Over-Voltage Protection Falling Threshold VFB falling 100 105 110 % - 2 - µs Built-in Maximum OCP Voltage - 1200 - mV OCSET Current Source 9 10 11 µA Over-Voltage Debounce Interval VOCP_MAX IOCSET Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 4 www.anpec.com.tw APW8722/A/B/C/D Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise noted. Typical values are at TA = 25°C. Symbol Parameter APW8722 Test Conditions Min. Unit Typ. Max. SOFT-START VDISABLE TSS Shutdown Threshold of VCOMP - - 0.4 V Internal Soft-Start Interval (Note 4) - 1.5 - ms Note 4: Guaranteed by design, not production tested. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 5 www.anpec.com.tw APW8722/A/B/C/D Typical Operating Characteristics Efficiency vs. Load Current FSW=300KHz, VOUT=1.2V Reference Voltage vs. Junction Temperature 0.61 90 0.605 Efficiency (%) Reference Voltage (V) VCC = 12V 0.6 85 80 75 70 0.595 VIN=12V H-Side: APW3109x1 L-Side: APW3116x1 65 0.59 -20 0 20 40 60 80 100 60 0.1 120 1 Junction Temperature (oC) 20.0 Switching Frequency vs. Junction Temperature 350 650 340 640 330 Switching Frequency (kHz) Switching Frequency (kHz) Switching Frequency vs. Junction Temperature 320 310 300 290 280 270 260 630 620 610 600 590 580 570 560 250 550 -20 0 20 40 60 80 100 120 -20 0 o 20 40 60 80 100 120 Junction Temperature (oC) Junction Temperature ( C) IOCSET vs. Junction Temperature Load Regulation 0.3 11.4 0.2 11 OCSET Current Source (uA) Output Voltage Variation (%) 10.0 Output Current (A) 0.1 0 -0.1 -0.2 -0.3 10.6 10.2 9.8 9.2 8.8 8.2 0 2 4 6 8 10 -20 Output Current (A) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 0 20 40 60 80 100 120 Junction Temperature (oC) 6 www.anpec.com.tw APW8722/A/B/C/D Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Power On Power Off VIN VIN 1 1 VOUT VOUT 2 2 VUGATE VUGATE 3 3 CH1: VIN, 5V/Div CH2: VOUT, 500mV/Div CH3: VUGATE, 10V/Div TIME: 1ms/Div CH1: VIN, 5V/Div CH2: VOUT, 500mV/Div CH3: VUGATE, 10V/Div TIME: 50ms/Div Enable Shutdown RLOAD =12Ω VCOMP 1 1 VCOMP VOUT VOUT 2 2 VPHASE VPHASE 3 3 CH1: VEN, 5V/Div, DC CH2: VOUT, 500mV/Div, DC CH3: VPHASE, 10V/Div, DC TIME: 1ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 CH1: VCOMP, 1V/Div CH2: VOUT, 500mV/Div CH3: VPHASE, 10V/Div TIME: 10ms/Div 7 www.anpec.com.tw APW8722/A/B/C/D Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Over-Current Protection Under-Voltage Protection R OCSET =open ,R DS (low Side )=12.5mΩ VOUT UVP UVP VFB UVP 1 1 VPHASE OCP 2 IL IL 3 2 CH1: VOUT, 500mV/Div CH2: IL,10A/Div TIME: 20ms/Div CH1: VFB, 200mV/Div CH2: VPHASE,10V/Div CH3: IL,10A/Div TIME: 10us/Div UGATE Falling UGATE Rising V UGATE 1 VUGATE 1 V LGATE 2 3 V PHASE 23 3 VLGATE 3 CH1: VUGATE, 20V/Div CH2: VLGATE, 10V/Div CH3: VPHASE, 10V/Div TIME: 20ns/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 V PHASE CH1: VUGATE, 20V/Div CH2: VLGATE, 10V/Div CH3: VPHASE, 10V/Div TIME: 20ns/Div 8 www.anpec.com.tw APW8722/A/B/C/D Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Load Transient VOUT 1 I OUT 32 CH1: VOUT, 50mV/Div,AC CH2: IOUT, 5A/Div TIME: 200us/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 9 www.anpec.com.tw APW8722/A/B/C/D Pin Description PIN No. APW8722A Function Description Name APW8722/B/C/D 1 1 BOOT This pin provides the bootstrap voltage to the high-side gate driver for driving the N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal switch generates the bootstrap voltage for the high-side gate driver (UGATE). 2 2 UGATE High-side Gate Driver Output. This pin is the gate driver for high-side MOSFET. - 3 GND Signal and Power ground. Connecting this pin to system ground. 3 - OCSET Current-Limit Threshold Setting Pin. There is an internal source current 10uA through a resistor from OCSET pin to GND. This pin is used to monitor the voltage drop across the Drain and Source of the low-side MOSFET for current-limit 4 - LGATE Output of The Low-side MOSFET Driver. Connect this pin to the low-side MOSFET. - 4 LGATE/ OCSET Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for low-side MOSFET. It also used to set the maximum inductor current. Refer to the section in “Function Description” for detail. 5 5 VCC Power Supply Input. Connect a nominal 5V to 12V power supply voltage to this pin. A power-on reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. 6 6 FB Feedback Input of Converter. The converter senses feedback voltage via FB and regulates the FB voltage at 0.6V/0.8V. Connecting FB with a resistor-divider from the output sets the output voltage of the converter. This is a multiplexed pin. During soft-start and normal converter operation, this pin represents the output of the error amplifier. It is used to compensate the regulation control loop in combination with the FB pin. 7 7 COMP Pulling COMP low (VDISABLE = 0.4V max.) will shut down the controller. When the pull-down device is released, the COMP pin will start to rise. When the COMP pin rises above the VDISABLE trip point, the APW8722 will begin a new initialization and soft-start cycle. 8 8 PHASE This pin is the return path for the high-side gate driver. Connecting this pin to the high-side MOSFET source and connect a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor the voltage drop across the low-side MOSFET for over-current protection. 9 (Exposed Pad) 9 (Exposed Pad) GND Thermal Pad. Connect this pad to the system ground plan for good thermal conductivity. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 10 www.anpec.com.tw APW8722/A/B/C/D Block Diagram VCC Regulator IOCSET (10 µA typical) Sample and Hold Power-On Reset BOOT Sense Low Side V REF UGATE VROCSET (0 .6V /0.8V typical) To LGATE PHASE UVP Comparator 0.5 VROCSET Soft Start and Fault Logic IZCMP VCC 1.25 Inhibit OVP Comparator Gate Control LGATE Soft-start PWM Comparator Error Amplifier VREF Oscillator 0 .4V FB Disable GND COMP Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 11 www.anpec.com.tw APW8722/A/B/C/D Typical Application Circuit For APW8722/B/C/D VCC Supply (5~12V) C4 1µF R4 2R2 5 Q3 2N7002 C1 100pF BOOT VCC 7 OFF ON VIN COMP UGATE APW8722 C2 100nF PHASE 1 C3 0.1µF C IN1 C IN2 1µF 220µF x 2 Q1 APM 2510 L1 2 8 VOUT 0.5µH R2 4.7kΩ LGATE/ 4 OCSET 6 FB Q2 APM 2556 R OCSET GND 3 C OUT 1000 µF x 2 R1 1kΩ R2 1kΩ R3 1kΩ C3 22 nF For APW8722A VCC Supply (5~12V) C4 1 µF R4 2R2 Q3 2N7002 APW8722(SOP-8OP) 5 7 OFF ON C1 100pF VIN VCC COMP C2 100nF BOOT UGATE PHASE R2 4.7kΩ 1 2 FB C IN1 C IN2 1µF 220µF x 2 Q1 APM 251 0 L1 8 LGATE 4 6 C3 0.1µF 0.5µH Q2 APM 255 6 VOUT C OUT 1000µF x 2 OCSET 3 R OCSET R1 1kΩ R3 1kΩ C3 22nF Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 R3 1kΩ 12 www.anpec.com.tw APW8722/A/B/C/D Function Description Power-On-Reset (POR) A resistor (ROCSET), connected from the LGATE/OCSET to The Power-On-Reset (POR) function of APW8722 con- GND, programs the over-current trip level. Before the IC initiates a soft-start process, an internal current source, tinually monitors the input supply voltage (VCC) and ensures that the IC has sufficient supply voltage and can IOCSET (10µA typical), flowing through the ROCSET develops a voltage (VROCSET) across the ROCSET. The device holds work well. The POR function initiates a soft-start process while the VCC voltage just exceeds the POR threshold; VROCSET and stops the current source IOCSET during normal operation. When the voltage across the low-side MOSFET the POR function also inhibits the operations of the IC while the VCC voltage falls below the POR threshold. exceeds the VROCSET, the APW8722 turns off the high-side and low-side MOSFET,and the device will enters hiccup Soft-Start mode until the over-current phenomenon is released. The APW8722 builds in a soft-start function about 1.5ms (Typ.) interval, which controls the output voltage rising as For avoid large inductor current occurring in short circuit before power on, the controller reduces internal current source, Iocset, to half during soft start time. It means that well as limiting the current surge at the start-up. During soft-start, an internal ramp voltage connected to the one when APW8722 is in soft start interval, the internal current source, Iocset, is only 5µA (typical). of the positive inputs of the error amplifier replaces the reference voltage (0.6V typical) until the ramp voltage The APW8722 has an internal OCP voltage, VOCP_MAX, and the value is 1.2V (typical). When the ROCSET x IOCSET exceed reaches the reference voltage. The soft-start circuit interval is shown as figure 1. 1.2V or the ROCSET is floating or not connected, the VROCSET will be the default value 1.2V. The over current threshold would be 1.2V across low-side MOSFET. The threshold of the valley inductor current-limit is therefore given by: Voltage(V) POK Delay Time VVCC OCSET count completed OCSET count start (OCSET duratiom, t2-t1, less than 0.9ms) ILIMIT = VPOK 0.9xVREF t0 t1 t2 VOUT t3 t4 2 × IOCSET × ROCSET RDS(ON) (low − side) For the over-current is never occurred in the normal operating load range, the variation of all parameters in the above equation should be considered: - The RDS(ON) of low-side MOSFET is varied by tempera- Time ture and gate to source voltage. Users should determine the maximum RDS(ON) by using the manufacturer’s Figure 1. Soft-Start Interval datasheet. - The minimum IOCSET (9µA) and minimum ROCSET should Over-Current Protection of the PWM Converter be used in the above equation. - Note that the ILIMIT is the current flow through the low- The over-current function protects the switching converter against over-current or short-circuit conditions. The controller senses the inductor current by detecting the drain- side MOSFET; ILIMIT must be greater than valley inductor current which is output current minus the half of induc- to-source voltage which is the product of the inductor’s current and the on-resistance of the low-side MOSFET tor ripple current. during it’s on-state. This method enhances the converter’s efficiency and reduces cost by eliminating a current sens- ILIMIT > IOUT(MAX ) − ing resistor required. ∆I 2 Where ∆I = output inductor ripple current - The overshoot and transient peak current also should be considered. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 13 www.anpec.com.tw APW8722/A/B/C/D Function Description (Cont.) Adaptive Shoot-Through Protection of the PWM Con- Under-Voltage Protection The under-voltage function monitors the voltage on FB (VFB) by Under-Voltage (UV) comparator to protect the PWM verter The gate drivers incorporate an adaptive shoot-through protection to prevent high-side and low-side MOSFETs converter against short-circuit conditions. When the VFB falls below the falling UVP threshold (50% VREF), a fault from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate signal is internally generated and the device turns off highside and low-side MOSFETs. The device will enters hic- has turned off one MOSFET before the other is allowed to rise. cup mode until the under-voltage phenomenon is released. During turn-off the low-side MOSFET, the LGATE voltage is monitored until it is below 1.5V threshold, at which Over-Voltage Protection (OVP) of the PWM Converter time the UGATE is released to rise after a constant delay. During turn-off of the high-side MOSFET, the UGATE-toPHASE voltage is also monitored until it is below 1.5V threshold, at which time the LGATE is released to rise The over-voltage protection monitors the FB voltage to prevent the output from over-voltage condition. When the after a constant delay. output voltage rises above 125% of the nominal output voltage, the APW8722 turns off the high-side MOSFET and turns on the low-side MOSFET until the output voltage falls below the falling below 105%, the OVP comparator is disengaged and both high-side and low-side drivers turn off. This OVP scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise activated with a continuously high output from low-side MOSFET driver. It’s a common problem for OVP schemes with a latch. Once an over-voltage fault condition is set, it can be reset by releasing COMP or toggling VCC poweron-reset signal. Shutdown and Enable The APW8722 can be shut down or enabled by pulling low the voltage on COMP. The COMP is a dual-function pin. During normal operation, this pin represents the output of the error amplifier. It is used to compensate the regulation control loop in combination with the FB pin. Pulling the COMP low (VDISABLE = 0.4V maximum) places the controller into shutdown mode which UGATE and LGATE are pulled to PHASE and GND respectively. When the pull-down device is released, the COMP voltage will start to rise. When the COMP voltage rises above the VDISABLE threshold, the APW8722 will begin a new initialization and soft-start process. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 14 www.anpec.com.tw APW8722/A/B/C/D Application Information Output Voltage Selection lower output ripple voltage. The ripple current and ripple The output voltage can be programmed with a resistive voltage can be approximated by: IRIPPLE = divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the VIN − VOUT VOUT × FSW × L VIN where Fs is the switching frequency of the regulator. error amplifier, and the reference voltage is 0.6V. The output voltage is determined by: ∆VOUT = IRIPPLE x ESR R VOUT = 0.6 × 1 + 1 R 2 A tradeoff exists between the inductor’s ripple current and the regulator load transient response time. A smaller in- R2 is the resistor connected from FB to the GND. ductor will give the regulator a faster load transient response at the expense of higher ripple current and vice Output Capacitor Selection versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the Where R1 is the resistor connected from VOUT to FB and ripple current to be approximately 30% of the maximum output current. The selection of COUT is determined by the required effective series resistance (ESR) and voltage rating rather than the actual capacitance requirement. Therefore, selecting Once the inductance value has been chosen, selecting an inductor is capable of carrying the required peak cur- high performance low ESR capacitors is intended for switching regulator applications. In some applications, rent without going into saturation. In some types of inductors, especially core that is make of ferrite, the ripple multiple capacitors have to be paralleled to achieve the desired ESR value. If tantalum capacitors are used, make current will increase abruptly when it saturates. This will result in a larger output ripple voltage. sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. PWM Compensation Input Capacitor Selection The output LC filter of a step down converter introduces a The input capacitor is chosen based on the voltage rat- double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A ing and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times compensation network among COMP, FB, and V OUT should be added. The compensation network is shown in higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2 Figure 5. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. filter is given by: If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the ca- FESR = pacitors manufacturer. For high frequency decoupling, a ceramic capacitor be- 1 2 × π × ESR × COUT The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. tween 0.1µF to 1µF can connect between VCC and ground pin. V PHASE L V OUT Inductor Selection The inductance of the inductor is determined by the out- C OUT put voltage requirement. The larger the inductance, the lower the inductor’s current ripple. This will translate into ESR Figure 2. The Output LC Filter Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 15 www.anpec.com.tw APW8722/A/B/C/D Application Information(Cont.) The poles and zeros of the transfer function are: 1 FZ1 = 2 × π × R2 × C2 1 FZ2 = 2 × π × (R1 + R3) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 FLC GAIN (dB) -40dB/dec FESR FP2 = -20dB/dec 1 2 × π × R3 × C3 C1 R3 C3 R2 C2 V OUT Frequency(Hz) R1 Figure 3. The LC Filter GAIN and Frequency FB V COMP V REF The PWM modulator is shown in Figure 4. The input is Figure 5. Compensation Network the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator The closed loop gain of the converter can be written as: is given by: GAINPWM = GAINLC X GAINPWM X GAINAMP VIN ∆VOSC Figure 6. shows the asymptotic plot of the closed loop V IN OSC ΔV OSC converter gain, and the following guidelines will help to design the compensation network. Using the below Driver guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade PWM Comparator slope and a phase margin greater than 45 degree. PHASE Output of Error Amplifier 1. Choose a value for R1, usually between 1K and 5K. 2. Select the desired zero crossover frequency Driver FO: (1/5 ~ 1/10) X FS >FO>FESR Figure 4. The PWM Modulator Use the following equation to calculate R2: ∆VOSC FO R2 = × × R1 VIN FLC The compensation network is shown in Figure 5. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: GAINAMP 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. 1 1 // R2 + VCOMP sC2 sC1 = = 1 VOUT R1// R3 + sC3 FZ1 = 0.75 X FLC Calculate the C2 by the equation: 1 C2 = 2 × π × R2 × FLC × 0.75 1 1 s + ×s + R2 × C2 R1 + R3) × C3 ( R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 C1 C2 R3 C3 × × × Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 16 www.anpec.com.tw APW8722/A/B/C/D Application Information(Cont.) MOSFET Selection 4. Set the pole at the ESR zero frequency FESR: The selection of the N-channel power MOSFETs is deter- FP1 = FESR mined by the RDS(ON), reverse transfer capacitance (CRSS), and maximum output current requirement.The losses in Calculate the C1 by the equation: C2 C1 = 2 × π × R2 × C2 × FESR − 1 the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following equations: 5. Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC PUPPER = IOUT2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the PLOWER = IOUT2 (1+ TC)(RDS(ON))(1-D) compensation gain at FP2 with the capabilities of the error amplifier. where IOUT is the load current TC is the temperature dependency of RDS(ON) FSW is the switching frequency FP2 = 0.5 X FS FZ2 = FLC tsw is the switching interval D is the duty cycle Combine the two equations will get the following component calculations: 1 + s × ESR × COUT GAINLC = 2 s × L × COUT + s × ESR × COUT + 1 Note that both MOSFETs have conduction losses while the upper MOSFET includes an additional transition loss. The switching internal, tsw, is the function of the reverse transfer capacitance CRSS. Figure 7 illustrates the switch- The poles and zero of this transfer functions are: 2 × π × L × COUT of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. R1 R3 = FS −1 2 × FLC 1 π × R3 × FS GAIN (dB) FZ1 FZ2 FP1 Voltage across C3 = VDS FP2 Compensation Gain 20log (R2/R1) 20log (VIN/ΔVOSC) drain and source of MOSFET FLC = ing waveform internal of the MOSFET. The (1+TC) term factors in the temperature dependency 1 tsw FLC FESR PWM & Filter Gain Time Figure 7. Switching Waveform Across MOSFET Converter Gain Frequency(Hz) Figure 6. Converter Gain and Frequency Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 17 www.anpec.com.tw APW8722/A/B/C/D Application Information (Cont.) Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the - The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. regulator. With power devices switching at 300kHz,the resulting current transient will cause voltage spike across - The ROCSET resistance should be placed near the IC as close as possible. the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition APW8722 of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of VCC the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed BOOT circuit traces should minimize interconnecting imped UGATE ances and the magnitude of voltage spike. And signal PHASE and power grounds are to be kept separate till combined using ground plane construction or single point LGATE grounding. Figure 8. illustrates the layout, with bold lines indicating high current paths; these traces must be short VIN L O A D ROCSET VOUT Close to IC and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: Figure 8. Layout Guidelines - Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG and LG) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, and boot capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 18 www.anpec.com.tw APW8722/A/B/C/D Package Information SOP-8P -T- SEATING PLANE < 4 mils D SEE VIEW A h X 45o E E1 THERMAL PAD E2 D1 c 0.25 A1 A2 A b e NX aaa c GAUGE PLANE SEATING PLANE L VIEW A S Y M B O L A SOP-8P INCHES MILLIMETERS MAX. MIN. MIN. MAX. 1.60 0.063 0.000 0.15 0.006 A1 0.00 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 0.049 D1 2.50 3.50 0.098 0.138 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 0.118 0.50 0.010 0.020 0.016 0.050 0oC 8oC e h 1.27 BSC 0.25 0.050 BSC L 0.40 1.27 ° 0oC 8oC aaa 0.10 0.004 Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 19 www.anpec.com.tw APW8722/A/B/C/D Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H T1 C d D 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 SOP-8P W E1 12.0±0.30 1.75±0.10 A0 B0 6.40±0.20 5.20±0.20 F 5.5±0.05 K0 2.10±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOP-8P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 20 www.anpec.com.tw APW8722/A/B/C/D Taping Direction Information SOP-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 21 www.anpec.com.tw APW8722/A/B/C/D Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 22 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW8722/A/B/C/D Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 23 www.anpec.com.tw