APW7073 Synchronous Buck PWM Controller Features General Description • • • • The APW7073 is voltage mode, synchronous PWM • • • • • • Single 12V Power Supply Required controller which drives dual N-channel MOSFETs. The 0.6V Reference with 1% Accurate device integrates all of the control, monitoring and Shutdown and Soft-start Function protecting functions into a single package, provides Programmable Frequency Range one controlled power output with under-voltage and from 50 kHz to 1000kHz over-current protections. Voltage Mode PWM Control Design The APW 7073 provides excellent regulation for Up to 100% Duty Cycle output load variation. The internal 0.6V temperature- Under-Voltage Protection compensated reference voltage is designed to meet the requirement of low output voltage applications. Over-Current Protection The device includes a 200kHz free-running triangle-wave SOP-14, QFN-16 Packages oscillator that is adjustable from 50kHz to 1000kHz. Lead Free Available (RoHS Compliant) The APW7073 with excellent protection functions: POR, OCP and UVP. The Power-On-Reset (POR) Applications circuit can monitor the VCC, EN, and OCSET voltage to make sure the supply voltage exceeds their • threshold voltage while the controller is running. Graphic Cards The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the upper and lower MOSFET’s RDS(ON). When the output current reaches the trip point, the controller will run the softstart function until the fault events are removed. The Under-Voltage Protection (UVP) monitors the voltage at FB pin (VFB) for short-circuit protection, when the VFB is less than 50% of VREF, the controller will shutdown the IC directly. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 1 www.anpec.com.tw APW7073 OCSET RT VCC 16 15 14 13 1 4 5 6 7 8 UGATE EN PHASE FB 3 GND COMP 2 Metal GND Pad (Bottom) REFIN SS SSDONE Pin Outs 12 PVCC 11 LGATE 10 GND 9 BOOT RT 1 14 VCC OCSET 2 13 PVCC SS 3 12 LGATE COMP 4 11 PGND FB 5 10 BOOT EN 6 9 UGATE GND 7 8 PHASE SOP-14 TOP VIEW QFN-16 TOP VIEW Ordering and Marking Information Package Code K : SOP - 14 Q : QFN - 16 Temp. Range E : -20 to 70 °C Handling Code TU : Tube TR : Tape & Reel TY : Tray (for QFN only) Lead Free Code L : Lead Free Device Blank : Original Device APW7073 Lead Free Code Handling Code Temp. Range Package Code APW7073 K : APW7073 Q : APW7073 XXXXX XXXXX - Date Code XXXXX - Date Code APW7073 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 2 www.anpec.com.tw APW7073 Block Diagram VCC OCSET GND Power-On Reset EN IOCSET 200uA BOOT O.C.P Comparator SSDONE (QFN ONLY) UGATE ISS 30uA 0.27V Soft Start O.C.P Comparator SS VREF PHASE U.V.P Comparator 50%VREF :2 REFIN PVCC (QFN ONLY) PWM Comparator Gate Control LGATE Error Amp PGND Oscillator FB Sawtooth Wave RT COMP Absolute Maximum Ratings Symbol VCC, PVCC BOOT UGATE, LGATE PHASE Parameter Rating Unit VCC, PVCC to GND -0.3 to +16 V BOOT to PHASE -0.3 to +16 V -5 to BOOT+5 -0.3 to BOOT +0.3 V -5 to PVCC+5 -0.3 to PVCC +0.3 V -5 to +21 -0.3 to 16 V UGATE to PHASE <400ns pulse width >400ns pulse width LGATE to PGND <400ns pulse width >400ns pulse width PHASE to GND Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 <400ns pulse width >400ns pulse width 3 www.anpec.com.tw APW7073 Absolute Maximum Ratings (Cont.) Symbol Rating Unit VCC+0.3 V -0.3 to 7 V PGND to GND -0.3 to +0.3 V Junction Temperature Range -20 to 150 °C TSTG Storage Temperature -65 to 150 °C TSDR Soldering Temperature (10 Seconds) 300 °C VESD Minimum ESD Rating ±2 KV RT, OCSET, SSDONE Parameter RT, OCSET, SSDONE to GND FB, COMP, REFIN FB, COMP, REFIN to GND PGND TJ NOTE 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE 2: The device is ESD sensitive. Handling precautions are recommended. Recommended Operating Conditions Symbol Parameter VCC, PVCC VIN Rating Unit IC Supply Voltage 10.8 to 13.2 V Converter Input Voltage 2.2 to 13.2 V VOUT Converter Output Voltage 0.6 to 5 V IOUT Converter Output Current 0 to 25 A TA Ambient Temperature Range -20 to 70 °C TJ Junction Temperature Range -20 to 125 °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7073 Min Unit Typ Max 0.5 1 mA 5 10 mA INPUT SUPPLY CURRENT ICC VCC Supply Current (Shutdown mode) UGATE, LGATE and EN = GND VCC Supply Current UGATE and LGATE Open POWER-ON RESET Rising VCC Threshold 9 9.5 10.0 V Falling VCC Threshold 7.5 8 8.5 V Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 4 www.anpec.com.tw APW7073 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7073 Min Typ Max Unit POWER-ON RESET (Cont.) Rising VOCSET Threshold 1.3 V VOCSET Hysteresis Voltage 0.1 V Rising EN threshold Voltage 1.3 V EN Hysteresis Voltage 0.1 V OSCILLATOR Accuracy FOSC -15 Free Running Frequency RT = open Adjustment Range RT pin: resistor to GND; resistor to VCC VOSC Ramp Amplitude (nominal 1.35V to 2.95V) Duty Duty Cycle Range +15 200 50 kHz 1000 1.6 0 % kHz V 100 % REFERENCE VREF Reference Voltage 0.60 Reference Voltage Tolerance -1 V +1 % PWM ERROR AMPLIFIER Gain Open Loop Gain RL = 10k, CL = 10pF (NOTE3) 88 dB RL = 10k, CL = 10pF (NOTE3) 15 MHz Slew Rate RL = 10k, CL = 10pF (NOTE3) 6 V/us FB Input Current VFB = 0.6V GBWP Open Loop Bandwidth SR 0.1 1 uA VCOPM COMP High Voltage 5.5 V VCOPM COMP Low Voltage 0 V ICOMP COMP Source Current COMP = 2V 5 mA ICOMP COMP Sink Current COMP = 2V 5 mA GATE DRIVERS IUGATE Upper Gate Source Current BOOT = 12V, VUGATE -VPHASE = 2V 2.6 A IUGATE Upper Gate Sink Current BOOT = 12V, VUGATE -VPHASE = 2V 1.05 A ILGATE Lower Gate Source Current PVCC = 12V, VLGATE = 2V 4.9 A ILGATE Lower Gate Sink Current PVCC = 12V, VLGATE = 2V 1.4 A RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A RUGATE Upper Gate Sink Impedance Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 BOOT = 12V, IUGATE = 0.1A 5 2 3 Ω 1.6 2.4 Ω www.anpec.com.tw APW7073 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter APW7073 Test Conditions Min Typ Max Unit GATE DRIVERS (Cont.) RLGATE RLGATE TD Lower Gate Source Impedance PVCC = 12V, ILGATE = 0.1A 1.3 1.95 Ω Lower Gate Sink Impedance PVCC = 12V, ILGATE = 0.1A 1.25 1.88 Ω 20 Dead Time nS PROTECTION FB Under Voltage Level Percent of VREF 45 50 55 % IOCSET OCSET Source Current VOCSET = 11.5V 150 200 250 uA VOCP OCP Voltage 230 270 310 mV 24 30 36 uA 0.25 0.35 V ENABLE/SOFT START ISS Soft-Start Charge Current SSDONE Low Voltage ISSDONE = 5mA (NOTE4) NOTE 3: Guaranteed by design NOTE 4: QFN Only Typical Application Circuit 1uF 12V VIN 1N4148 PVCC VCC SSDONE RT 1uH 1nF OCSET 2.37K 1uF 470uFx2 BOOT ON 0.1uF UGATE EN APM2509 2.2uH VOUT PHASE OFF SS 22nF 470uF 1.5nF APM2506 REFIN LGATE SCD24 1000uFx2 7.5 COMP 8.2nF 33nF PGND FB GND 2.7K 1K 2K 18 68nF Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 6 www.anpec.com.tw APW7073 Function Pin Descriptions UGATE VCC Power supply input pin. Connect a nominal 12V power This pin is the gate driver for the upper MOSFET of supply to this pin. The power-on reset function PWM output. monitors the input voltage by this pin. It is recommended LGATE that a decoupling capacitor (1 to 10uF) be connected This pin is the gate driver for the lower MOSFET of to GND for noise decoupling. PWM output. PVCC SS This pin provides a supply voltage for the lower gate Connect a capacitor to GND and a 10uA current source drive, connect this pin to VCC pin in normal use. charges this capacitor to set the soft-start time. BOOT OCSET This pin provides the bootstrap voltage to the upper This pin serves two functions: a shutdown control and gate driver for driving the N-channel MOSFET. the setting of over current limit threshold. Pulling this PHASE pin below 1.3V will shutdown the controller, forcing the UGATE and LGATE signals to be low. This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. This A resistor (Rocset) connected between this pin and pin is also used to monitor the voltage drop across the the drain of the high side MOSFET will determine the MOSFET for over-current protection. over current limit. An internal 200uA current source will flow through this resistor, creating a voltage drop, GND which will be compared with the voltage across the This pin is the signal ground pin. Connect the GND pin high side MOSFET. The threshold of the over current to a good ground plane. limit is therefore given by: PGND IPEAK = This pin is the power ground pin for the lower gate IOCSET (200uA ) × R OCSET R DS(ON) driver. It should be tied to GND pin on the board. EN COMP Pull this pin above 1.3V to enable the device and pull this pin below 1.2V to disable the device. In shutdown, This pin is the output of PWM error amplifier. It is used the SS is discharged and the UGATE and LGATE pins to set the compensation components. are held low. Note that don’t leave this pin open. FB RT This pin is the inverting input of the PWM error amplifier. This pin allows adjusting the switching frequency. It is used to set the output voltage and the compensation Connect a resistor from RT pin to the ground to increase components. This pin is also monitored for under- the switching frequency. Conversely, connect a resistor voltage protection; if the FB voltage is under 50% of from RT to the VCC to decrease the switching reference voltage, the device will be shut down. frequency. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 7 www.anpec.com.tw APW7073 Function Pin Descriptions (Cont.) SSDONE This pin is an open drain device; connect a pull up resistor to VCC for SSDONE function. REFIN This pin provides a external reference voltage instead of the internal 0.6V reference. The REFIN pin is pulled to 5V internally. If the REFIN voltage is less than 4V, the external voltage is used. Typical Characteristics Power Off Power On CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH2 CH1 CH2 CH3 CH3 CH1: VCC (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 CH1: VCC (5V/div) CH2: SS (2V/div) CH3: Vo (1V/div) Time: 2ms/div 8 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) EN (EN=Vcc) Shutdown (EN=GND) CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 CH2 CH2 CH3 CH3 CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div CH1: EN (5V/div) CH2: SS (5V/div) CH3: Vo (1V/div) Time: 10ms/div UGATE Falling UGATE Rising VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 CH2 CH2 CH3 CH3 CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div CH1: Ug (20V/div) CH2: Lg (5V/div) CH3: Phase (10V/div) Time: 50ns/div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 9 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) Load Transient Response Under Voltage Protection VCC=12V, Vin=12V Vo=1.5V, L=1uH VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 CH1 CH2 CH3 CH4 CH2 CH1: Vo (500mV/div) CH2: Io (5A/div) Time: 200us/div CH1: SS (5V/div) CH2: Io (5A/div) CH3: Vo (1V/div) CH4: Ug (10V/div) Time: 10ms/div Short Test Over Current Protection CH1 VCC=12V, Vin=12V Vo=1.5V, L=1uH CH1 VCC=12V, Vin=12V,Vo=1.5V, L=1uH Rocset=1KΩ , Rds(on)=8mΩ CH2 CH3 CH2 CH3 CH4 CH4 CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4: Ug (20V/div) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 CH1: SS (5V/div) CH2: IL (10A/div) CH3: Vo (1V/div) CH4: Ug (20V/div) Time: 10ms/div 10 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) Reference Voltage vs. Junction Temperature Switching Frequency vs. Junction Temperature 205 0.602 Reference Voltage(V) Switching Frequency(KHz) 0.601 200 195 190 185 0.6 0.599 0.598 0.597 0.596 0.595 180 -40 -20 0 20 40 60 80 100 0.594 -40 120 0 20 40 60 80 100 120 Junction Temperature ( °C) Junction Temperature ( °C) UGATE Source Current vs. UGATE Voltage UGATE Sink Current vs. UGATE Voltage 3.5 3 VBOOT=12V VBOOT=12V 3 2.5 UGAT Sink Current (A) UGATE Source Current (A) -20 2.5 2 1.5 1 0.5 2 1.5 1 0.5 0 0 0 2 4 6 8 10 0 12 UGATE Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 2 4 6 8 10 12 UGATE Voltage (V) 11 www.anpec.com.tw APW7073 Typical Characteristics (Cont.) LGATE Sink Current vs. LGATE Voltage LGATE Source Current vs. LGATE Voltage 3.5 3 PVCC=12V 5 LGATE Sink Current (A) LGATE Source Current (A) 6 4 3 2 1 0 PVCC=12V 2.5 2 1.5 1 0.5 0 0 2 4 6 8 10 12 0 LGATE Voltage (V) 2 4 6 8 10 12 LGATE Voltage (V) Function Descriptions Power On Reset (POR) Soft-Start/EN The Power-On Reset (POR) function of APW7074 The SS/EN pins control the soft-start and enable or continually monitors the input supply voltage (VCC), disable the controller. Connect a soft-start capacitor the enable (EN) pin and OCSET pin. The supply from SS pin to GND to set the soft-start interval. Figure1. voltage (VCC) must exceed its rising POR threshold shows the soft-start interval. When VCC reaches its voltage. The voltage at OCSET pin is equal to VIN less Power-On-Reset threshold (9.5V), internal 30uA current a fixed voltage drop (Vocset = VIN- VROCSET). EN pin can source starts to charge the capacitor. When the SS be pulled high with connecting a resistor to VCC. The reaches the enabled threshold about 1.8V, the internal POR function initiates soft-start operation after VCC, 0.6V reference starts to rise and follows the SS; the EN and OCSET voltages exceed their POR thresholds. error amplifier output (COMP) suddenly raises to 1.35V, For operation with a single +12V power source, VIN which is the valley of the triangle wave of the oscillator, and VCC are equivalent and the +12V power source leads the VOUT to start up. Until the SS reaches about must exceed the rising VCC threshold. The POR 4.2V, the internal reference completes the soft-start function inhibits operation at disabled status (EN pin interval and reaches to 0.6V; then V OUT is in regulation. low). With both input supplies above their POR The SS still rises to 5.5V and then stops. thresholds, the device initiates a soft-start interval. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 12 www.anpec.com.tw APW7073 Function Descriptions (Cont.) Soft-Start/EN (Cont.) TSoft − Start = t 2 − t 1 = ILIMIT = C SS ⋅ 2 .4 V ISS I OCSET × R OCSET R DS (ON ) For the over-current is never occurred in the normal operating load range; the variation of all parameters in Where: the above equation should be determined. CSS = external Soft-Start capacitor ISS = Soft-Start current=30uA - The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user should determine Voltage the maximum RDS(ON) in manufacturer’s datasheet. - The minimum IOCSET (170uA) and minimum ROCSET should be used in the above equation. VSS - Note that the ILIMIT is the current flow through the 4.2V upper MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. An over current condition will shut down the device VOUT and discharge the CSS with a 30uA sink current and 1.8V then initiate the soft-start sequence. If the over current condition is not removed during the soft-start interval, t0 t1 t2 the device will be shut down while the over current is Time detected and the SS still rises to 4V to complete its Figure 1. Soft-Start Internal cycle. The soft start function will be cycled until the over current condition is removed. Both over-current Over-Current Protection (monitor upper MOSFET) protections have the same behavior while an over The APW7073 provides two manners to protect the current condition is detected. converter from abnormal output load; one monitors Over-Current Protection (monitor lower MOSFET) the voltage across the upper MOSFET and use the MOSFET pin to set the over-current trip point, the other The other over-current protection monitors the output monitors the voltage across the lower MOSFET by current by using the voltage drop across the lower comparing with an internal reference voltage (0.27V). MOSFET’s RDS(ON) and this voltage drop will be compared with the internal 0.27V reference voltage. If the A resistor (ROCSET) connected between OCSET pin and voltage drop across the lower MOSFET’s RDS(ON) is the drain of the upper MOSFET will determine the over larger than 0.27V, an over-current condition is detected. current limit. An internal 200uA current source will flow The threshold of the over current limit is given by: through this resistor, creating a voltage drop, which ILIMIT = will be compared with the voltage across the upper MOSFET. When the voltage across the upper 0.27V R DS(ON) For the over-current is never occurred in the normal MOSFET exceeds the voltage drop across the R OCSET, an over-current will be detected. The threshold of the operating load range; the parameters RDS(ON) and ILIMIT over current limit is therefore given by: in the above equation also have the same notices as the previous section. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 13 www.anpec.com.tw APW7073 Function Descriptions (Cont.) 1000 Under Voltage Protection 900 The FB pin is monitored during converter operation by 800 RT Resistance (KΩ) their own Under Voltage (UV) comparator. If the FB voltage drops below 50% of the reference voltage (50% of 0.6V = 0.3V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter’s output is latched to be floating. Switching Frequency 700 600 500 400 300 200 100 0 The APW7073 provides the oscillator switching frequency 200 adjustment. The device includes a 200kHz free-running 300 400 500 600 700 800 900 1000 Frequency (KHz) triangle wave oscillator. If operating in higher frequency than 200KHz, connect a resistor from RT pin to the Figure3. Oscillator Frequency vs. RT Resistance ground to increase the switching frequency. (High Frequency) Conversely, if operating in lower frequency than 200KHz, connect a resistor from RT to the VCC to decrease the switching frequency. 1000 900 desired frequency. Figure 3. shows more detail for 800 RT Resistance (KΩ) Figure 2. shows how to select the resistor for the the higher frequencies and Figure 4. shows the lower frequency detail. 1000 900 RT Resistance (KΩ) 800 700 600 500 400 300 700 200 600 50 500 70 90 110 130 150 170 Frequency (KHz) 400 300 Figure4. Oscillator Frequency vs. RT Resistance 200 (Low Frequency) 100 0 10 1000 Frequency (KHz) Figure2. Oscillator Frequency vs. RT Resistance Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 14 www.anpec.com.tw APW7073 Application Information Output Voltage Selection types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it The output voltage can be programmed with a resistive saturates. This will result in a larger output ripple divider. Use 1% or better resistors for the resistive voltage. divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage Output Capacitor Selection is 0.6V. The output voltage is determined by: R V OUT = 0.6 × 1 + OUT R GND Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is Where ROUT is the resistor connected from VOUT to FB intended for switching regulator applications. In some and RGND is the resistor connected from FB to GND. applications, multiple capacitors have to be parallel to Output Inductor Selection achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also The inductor value determines the inductor ripple recommended, and the voltage rating of the output current and affects the load transient response. Higher capacitors also must be considered. If tantalum inductor value reduces the inductor’s ripple current and capacitors are used, make sure they are surge tested induces lower output ripple voltage. The ripple current by the manufactures. If in doubt, consult the capacitors and ripple voltage can be approximated by: V − VOUT V IRIPPLE = IN × OUT FS × L VIN manufacturer. Input Capacitor Selection ∆VOUT = IRIPPLE × ESR The input capacitor is chosen based on the voltage where Fs is the switching frequency of the regulator. rating and the RMS current rating. For reliable Although increase of the inductor value and frequency operation, select the capacitor voltage rating to be at reduces the ripple current and voltage, a tradeoff will least 1.3 times higher than the maximum input voltage. exist between the inductor’s ripple current and the The maximum RMS current rating requirement is regulator load transient response time. approximately IOUT/2, where IOUT is the load current. During power up, the input capacitors have to handle A smaller inductor will give the regulator a faster load large amount of surge current. If tantalum capacitors transient response at the expense of higher ripple are used, make sure they are surge tested by the current. Increasing the switching frequency (FS) also manufactures. If in doubt, consult the capacitors reduces the ripple current and voltage, but it will manufacturer. For high frequency decoupling, a ceramic increase the switching loss of the MOSFET and the capacitor 1uF can be connected between the drain of power dissipation of the converter. The maximum ripple upper MOSFET and the source of lower MOSFET. current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be MOSFET Selection approximately 30% of the maximum output current. The selection of the N-channel power MOSFETs are Once the inductance value has been chosen, select determined by the RDS(ON), reverse transfer capacitance an inductor that is capable of carrying the required (CRSS) and maximum output current requirement. There peak current without going into saturation. In some are two components of loss in the MOSFETs: Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 15 www.anpec.com.tw APW7073 Application Information (Cont.) PHASE MOSFET Selection (Cont.) L OUTPUT conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately C OUT given by the following: ESR PUPPER = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) Figure 5. The Output LC Filter Where IOUT is the load current F LC TC is the temperature dependency of RDS(ON) -40dB/dec FS is the switching frequency GAIN (dB) tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition F ESR -20dB/dec loss. The switching internal, tSW , is a function of the reverse transfer capacitance C RSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. Frequency(Hz) Figure 6. The LC Filter GAIN and Frequency PWM Compensation The PWM modulator is shown in Figure 7. The input The output LC filter of a step down converter introduces is the output of the error amplifier and the output is the a double pole, which contributes with -40dB/decade PHASE node. The transfer function of the PWM gain slope and 180 degrees phase shift in the control modulator is given by: VIN GAIN PWM = ∆ V OSC loop. A compensation network among COMP, FB and VOUT should be added. The compensation network is V IN shown in Fig. 8. The output LC filter consists of the output inductor and output capacitors. The transfer OSC function of the LC filter is given by: GAIN LC ΔV OSC 1 + s × ESR × C OUT = 2 s × L × C OUT + s × ESR × C OUT + 1 Driver 1 2×π× FESR = PHASE Output of Error Amplifier The poles and zero of this transfer functions are: FLC = Driver PWM Comparator L × C OUT Figure 7. The PWM Modulator 1 2 × π × ESR × C OUT The compensation network is shown in Figure 8. It provides a close loop transfer function with the highest The FLC is the double poles of the LC filter, and FESR is zero crossover frequency and sufficient phase margin. the zero introduced by the ESR of the output capacitor. The transfer function of error amplifier is given by: Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 16 www.anpec.com.tw APW7073 Application Information (Cont.) PWM Compensation (Cont.) 3.Place the first zero FZ1 before the output LC filter 1 1 // R2 + sC1 sC2 GAIN AMP = 1 R1// R3 + sC3 1 1 s + × s + ( ) R2 C2 R1 R3 C3 × + × R1 + R3 = × C1 + C2 1 R1 × R3 × C1 s s + × s + R2 × C1 × C2 R3 × C3 double pole frequency FLC. V = COMP V OUT FZ1 = 0.75 X FLC Calculate the C2 by the equation: C2 = 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: The poles and zeros of the transfer function are: F Z1 F Z2 FP1 FP2 C1 = 1 = 2 × π × R2 × C2 1 = 2 × π × (R1 + R3 ) × C3 1 = C1 × C2 2 × π × R2 × C1 + C2 frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. FP2 = 0.5 X FS C1 C3 C2 2 × π × R2 × C2 × FESR − 1 5.Set the second pole FP2 at the half of the switching 1 = 2 × π × R3 × C3 R3 1 2 × π × R2 × FLC × 0.75 R2 FZ2 = FLC C2 Combine the two equations will get the following V OUT component calculations: R1 FB V COMP R1 FS −1 2 × FLC 1 C3 = π × R3 × FS R3 = V REF Figure 8. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP F Z1 F Z2 Figure 9. shows the asymptotic plot of the closed loop F P1 F P2 GAIN (dB) converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade Compensation Gain 20log (R2/R1) 20log ( V IN/Δ V OSC ) slope and a phase margin greater than 45 degree. 1.Choose a value for R1, usually between 1K and 5K. F LC F ESR 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: R2 = Frequency(Hz) ∆ V OSC F × O × R1 V IN FLC Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 Converter Gain PWM & Filter Gain Figure 9. Converter Gain and Frequency 17 www.anpec.com.tw APW7073 Application Information (Cont.) the resistor dividers, boot capacitors, and SS Layout Considerations capacitors should be close their pins. (For In any high switching frequency converter, a correct example, place the decoupling ceramic capacitor layout is important to ensure proper operation of the near the drain of the high-side MOSFET as close regulator. With power devices switching at 300KHz, as possible. The bulk capacitors are also placed the resulting current transient will cause voltage spike near the drain). across the interconnecting impedance and parasitic - The input capacitor should be near the drain of circuit elements. As an example, consider the turn-off the upper MOSFET; the output capacitor should transition of the PWM MOSFET. Before turn-off, the be near the loads. The input capacitor GND should MOSFET is carrying the full load current. During be close to the output capacitor GND and the lower turn-off, current stops flowing in the MOSFET and is MOSFET GND. free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates - The drain of the MOSFETs (VIN and PHASE a large voltage spike during the switching interval. In nodes) should be a large plane for heat sinking. general, using short, wide printed circuit traces should minimize interconnecting impedances and APW7073 the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. VCC PVCC Figure 10. illustrates the layout, with bold lines BOOT VIN indicating high current paths; these traces must be short and wide. Components along the bold lines UGATE should be placed lose together. Below is a checklist PHASE for your layout: LGATE L O A D VOUT - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes Figure 10. Layout Guidelines since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 18 www.anpec.com.tw APW7073 Package Information 0.015 x 45 E H SOP – 14 (150mil) C D A Dim A A1 B C D E e H L θ° B 0.010 e GAUGE PLANE SEATING PLANE A1 Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 Inches Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150 1.274 5.808 0.382 0° Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 L Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 6.215 1.274 8° 19 0.228 0.015 0° 0.244 0.050 8° www.anpec.com.tw APW7073 Packaging Information QFN-16 e b E E2 L D D2 A2 A A A1 A2 A3 D E b D2 E2 e L A1 A3 Dim Millimeters Min. 0.76 0.00 0.57 Inches Max. 0.84 0.04 0.63 Min. 0.030 0.00 0.022 0.20 REF. 3.90 3.90 0.25 2.05 2.05 0.008 REF. 4.10 4.10 0.35 2.15 2.15 0.154 0.154 0.010 0.081 0.081 0.60 0.002 0.650 BSC 0.50 Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 Max. 0.033 0.0015 0.025 0.161 0.161 0.014 0.085 0.085 0.0257BSC 20 0.024 www.anpec.com.tw APW7073 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Tim e Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 21 www.anpec.com.tw APW7073 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volum e m m Volume mm <350 ≥350 <2.5 m m 240 +0/-5°C 225 +0/-5°C ≥2.5 m m 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 m m 260 +0°C* 260 +0°C* 260 +0°C* 1.6 m m – 2.5 m m 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 m m 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA Carrier Tape & Reel Dimensions t D P Po E P1 Bo F W Ko Ao Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 D1 22 www.anpec.com.tw APW7073 Carrier Tape & Reel Dimensions(Cont.) T2 J C A B T1 Application SOP-14 (150mil) A B C 330REF 100REF F D 13.0 + 0.5 - 0.2 D1 7.5 φ0.50 + 0.1 φ1.50 (MIN) J T1 T2 W P E 2 ± 0.5 16.5REF 2.5 ± 025 16.0 ± 0.3 8 1.75 Po P1 Ao Ko t 4.0 2.0 6.5 2.10 0.3±0.05 (mm) 5x5 Shipping Tray Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 23 www.anpec.com.tw APW7073 5x5 Shipping Tray (Cont.) Cover Tape Dimensions Application SOP- 14 Carrier Width 24 Cover Tape Width 21.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.1 - Apr., 2006 24 www.anpec.com.tw