APW7073A Synchronous Buck PWM Controller Features General Description • Single 12V Power Supply Required The APW7073A is a voltage mode and synchronous • 0.6V Reference with 1% Accuracy • Shutdown and Soft-Start Function PWM controller which drives dual N-channel MOSFETs. The device integrates all of the controlling, monitoring, • Programmable Frequency Range from 50 kHz to and protecting functions into a single package, and provides one controlled power output with over-current 1000kHz protection. • Voltage Mode PWM Control Design • Up to 100% Duty Cycle • Over-Current Protection (OCP) • SOP-14 Package • Lead Free and Green Devices Available The APW7073A provides excellent regulation for output load variation. The internal 0.6V temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. The device includes a 200kHz free-running triangle-wave oscillator that is adjustable from 50kHz to 1000kHz. (RoHS Compliant) The APW7073A has been equipped with excellent protection functions: Power-On-Reset (POR) and Over-Current Protection (OCP). The POR circuit can monitor the VCC, EN, and OCSET voltages to make sure the supply Typical Application Circuit 12V voltages exceed their threshold voltage while the controller is running. The OCP monitors the output current V IN ROCSET by using the voltage drop across the upper MOSFET’s RDS . When the output current reaches the trip point, the IC shuts off the converter and initiates a new soft-start RFS (ON) APW7073A L V OUT process. After two over-current events are counted, the device turns off both high-side and low-side MOSFETs and the converter output is latched to be floating. It requires a POR of VCC to restart. CSS Applications Pin Configuration • RT 1 OCSET 2 SS 3 COMP 4 FB 5 EN 6 GND 7 DC-DC Power Supply 14 VCC 13 PVCC SOP-14 12 LGATE 11 PGND 10 BOOT 9 UGATE 8 PHASE ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 1 www.anpec.com.tw APW7073A Ordering and Marking Information Package Code K : SOP - 14 Operating Ambient Temperature Range E : -20 to 70° C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7073A Assembly Material Handling Code Temperature Range Package Code APW7073A K : APW7073A XXXXX - Date Code XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCC, VPVCC VBOOT VUGATE VLGATE VPHASE VRT, VOCSET, VEN VFB, VCOMP, VSS VPGND (Note 1) Parameter VCC, PVCC to GND BOOT to PHASE UGATE to PHASE <400ns pulse width PHASE to GND Unit V -0.3 to +16 V -5 to VBOOT +5 >400ns pulse width LGATE to PGND Rating -0.3 to +16 V -0.3 to VBOOT +0.3 <400ns pulse width -5 to VPVCC +5 >400ns pulse width -0.3 to VPVCC +0.3 <400ns pulse width -10 to +30 >400ns pulse width -0.3 to 16 RT, OCSET, EN to GND FB, COMP, SS to GND V V -0.3 to VCC+0.3 V -0.3 to 7 V PGND to GND -0.3 to +0.3 V Junction Temperature Range -20 to 150 °C TSTG Storage Temperature -65 to 150 °C TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C TJ Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note 2) Symbol θJA Parameter Typical Value Junction-to-Ambient Thermal Resistance in Free Air Unit o SOP-14 160 C/W Note2: θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 2 www.anpec.com.tw APW7073A Recommended Operating Conditions Symbol Parameter VCC, VPVCC IC Supply Voltage VIN Converter Input Voltage VOUT Converter Output Voltage IOUT Converter Output Current Rating Unit 10.8 to 13.2 V 2.2 to 13.2 V 0.6 to 5 V 0 to 30 A TA Ambient Temperature Range -20 to 70 °C TJ Junction Temperature Range -20 to 125 °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7073A Max. Unit Min. Typ. VCC Supply Current (Shutdown Mode) UGATE, LGATE and EN = GND - 0.5 1 mA VCC Supply Current - 5 10 mA Rising VCC Threshold 9 9.5 10.0 V Falling VCC Threshold 7.5 8 8.5 V Rising VOCSET Threshold - 1.3 - V VOCSET Hysteresis Voltage - 0.1 - V Rising EN threshold Voltage - 1.3 - V EN Hysteresis Voltage - 0.1 - V -15 - +15 % INPUT SUPPLY CURRENT ICC UGATE and LGATE Open POWER-ON-RESET OSCILLATOR Accuracy FOSC Free Running Frequency RT = open - 200 - kHz Adjustment Range RT pin: resistor to GND; resistor to VCC 50 - 1000 kHz VOSC Ramp Amplitude (nominal 1.35V to 2.95V) - 1.6 - V Duty Duty Cycle Range 0 - 100 % Reference Voltage - 0.60 - V Reference Voltage Tolerance -1 - +1 % REFERENCE VREF PWM ERROR AMPLIFIER Gain GBWP SR Open Loop Gain RL = 10k, CL = 10pF (Note3) - 88 - dB Open Loop Bandwidth RL = 10k, CL = 10pF (Note3) - 15 - MHz Slew Rate RL = 10k, CL = 10pF (Note3) - 6 - V/µs FB Input Current VFB = 0.6V - 0.1 1 µA VCOMP COMP High Voltage - 5.5 - V VCOMP COMP Low Voltage - 0 - V ICOMP COMP Source Current VCOMP = 2V - 5 - mA ICOMP COMP Sink Current VCOMP = 2V - 5 - mA Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 3 www.anpec.com.tw APW7073A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC=12V, and TA =-20~70°C. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7073A Min. Typ. Max. Unit GATE DRIVERS IUGATE Upper Gate Source Current VBOOT = 12V, VUGATE -VPHASE = 2V - 2.6 - A RUGATE Upper Gate Sink Impedance VBOOT = 12V, IUGATE = 0.1A - 1.6 2.4 Ω ILGATE Lower Gate Source Current VPVCC = 12V, VLGATE = 2V - 3.0 - A RLGATE Lower Gate Sink Impedance VPVCC = 12V, ILGATE = 0.1A - 1.25 1.88 Ω - 50 - ns 170 200 250 µA 24 30 36 µA TD Dead Time PROTECTION IOCSET OCSET Source Current VOCSET = 11.5V ENABLE/SOFT-START ISS Soft-Start Charge Current Note 3 : Guaranteed by design Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 4 www.anpec.com.tw APW7073A Typical Operating Characteristics Switching Frequency vs. Junction Temperature Reference Voltage vs. Junction Temperature 205 0.602 Reference Voltage(V) Switching Frequency(kHz) 0.601 200 195 190 185 0.6 0.599 0.598 0.597 0.596 0.595 180 0.594 -40 -20 0 20 40 60 80 100 120 -40 Junction Temperature (°C) -20 0 20 40 60 80 100 120 Junction Temperature (°C) Operating Waveforms Power On Power Off Vcc =12V, Vin=12V VOUT =1.5V, L=1uH Vcc =12V, Vin=12V VOUT =1.5V, L=1uH 1 1 2 2 3 3 CH1: VCC (5V/div) CH2: VSS (2V/div) CH3: VOUT (1V/div) Time: 10ms/div Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 CH1: VCC (5V/div) CH2: VSS (2V/div) CH3: VOUT (1V/div) Time: 2ms/div 5 www.anpec.com.tw APW7073A Operating Waveforms (Cont.) EN (VEN=VCC) Shutdown (VEN=VGND) Vcc =12V, Vin=12V VOUT =1.5V, L=1uH Vcc =12V, Vin=12V VOUT =1.5V, L=1uH 1 1 2 2 3 3 CH1: VEN (5V/div) CH2: VSS (5V/div) CH3: VOUT (1V/div) CH1: VEN (5V/div) CH2: VSS (5V/div) CH3: VOUT (1V/div) Time: 10ms/div Time: 10ms/div UGATE Rising UGATE Falling Vcc =12V, Vin=12V VOUT =1.5V, L=1uH 1 1 2 2 3 3 CH1: VUGATE (20V/div) CH2: VLGATE (5V/div) CH3: VPHASE (10V/div) Time: 50ns/div CH1: VUGATE (20V/div) CH2: VLGATE (5V/div) CH3: VPHASE (10V/div) Time: 50ns/div Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 Vcc =12V, Vin=12V VOUT =1.5V, L=1uH 6 www.anpec.com.tw APW7073A Operating Waveforms (Cont.) Load Transient Response Short Test before Power On VCC =12V, VIN =12V, VOUT =1.5V, L=1 µH, ROCSET = 1kΩ , RDS(ON) = 8.5mΩ Vcc =12V, Vin=12V VOUT =1.5V, L=1uH 1 1 2 3 2 4 CH1: VOUT (500mV/div) CH4: IOUT (5A/div) Time: 200µs/div CH1: VSS (5V/div) CH2: IL (10A/div) CH3: VOUT (1V/div) CH4: VUGATE (20V/div) Time: 20ms/div Short Test after Power On 1 VCC =12V, VIN =12V, VOUT =1.5V, L=1 µH, ROCSET = 1kΩ , RDS(ON) = 8.5mΩ 2 3 4 CH1: VSS (5V/div) CH2: IL (10A/div) CH3: VOUT (1V/div) CH4: VUGATE (20V/div) Time: 20ms/div Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 7 www.anpec.com.tw APW7073A Function Pin Description VCC SS Power supply input pin. Connect a nominal 12V power supply to this pin. The power-on-reset function monitors Connect a capacitor to the GND and a 30µA current source the input voltage by this pin. It is recommended that a decoupling capacitor (1 to 10µF) be connected to the OCSET GND for noise decoupling. This pin serves two functions: a shutdown control and the setting of over current limit threshold. Pulling this pin charges this capacitor to set the soft-start time. PVCC below 1.3V will shutdown the controller, forcing the UGATE and LGATE signals to be low. This pin provides a supply voltage for the lower gate drive. Connect this pin to VCC pin in normal use. A resistor (Rocset) connected between this pin and the BOOT drain of the high side MOSFET will determine the over current limit. An internal 200µA current source will flow This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. through this resistor, creating a voltage drop, which will be compared with the voltage across the high side PHASE MOSFET. The threshold of the over current limit is therefore given by: This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. This pin is also used to monitor the voltage drop across the IPEAK = MOSFET for over-current protection. GND IOCSET ( 200uA ) × ROCSET RDS(ON) EN This pin is the signal ground pin. Connect the GND to a good ground plane. Pull this pin above 1.3V to enable the device and pull PGND this pin below 1.2V to disable the device. In shutdown, the SS is discharged and the UGATE and LGATE pins This pin is the power ground pin for the lower gate driver. are held low. Note that don’t leave this pin open. It should be tied to the GND on the board. RT COMP This pin allows adjusting the switching frequency. This pin is the output of PWM error amplifier. It is used to Connect a resistor from RT pin to the ground to increase the switching frequency. Conversely, connect a resistor set the compensation components. from RT to the VCC to decrease the switching frequency. FB This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. UGATE This pin is the gate driver for the upper MOSFET of PWM output. LGATE This pin is the gate driver for the lower MOSFET of PWM output. Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 8 www.anpec.com.tw APW7073A Block Diagram VCC GND OCSET Power-OnReset EN IOCSET 200µA BOOT UGATE ISS 30µA Soft-Start 15K O.C.P Comparator SS PHASE PVCC PWM Comparator VREF Gate Control LGATE 15K Error Amp PGND Oscillator FB Sawtooth Wave RT COMP Typical Application Circuit 12V 1µF 5.1 1N4148 Zener 15V PVCC VCC NC 1nF OCSET 2.2 BOOT NC VIN RT 3K 1µF 10µF 10µF 1500µFx2 0.1µF ON UGATE EN 2.2 APM2510 APM2510 VOUT 7.2µH PHASE OFF 1nF SS 2.2 0.1µF 1µF LGATE APM2556 APM2556 2200µFx2 2.2 COMP 10nF PGND FB 1nF GND 3.3k 8.2k 1.8k 3.3k 10nF Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 9 www.anpec.com.tw APW7073A Function Description Power-On-Reset (POR) Voltage The Power-On-Reset (POR) function of APW7073A continually monitors the input supply voltage (VCC), the enable (EN) pin, and the OCSET pin. The supply voltage (VCC) V SS must exceed its rising POR threshold voltage. The voltage at OCSET pin is equal to V IN less a fixed voltage 4.2V drop (V OCSET = VIN- V ROCSET). The EN pin can be pulled high with connecting a resistor to the VCC. The POR function initiates soft-start operation after VCC, EN, and OCSET voltages exceed their POR thresholds. For op- V OUT 1.8V eration with a single +12V power source, VIN and Vcc are equivalent and the +12V power source must exceed the Time rising VCC threshold. The POR function inhibits operation at disabled status (EN pin low). With both input sup- t0 t2 Figure 1. Soft-Start Internal plies above their POR thresholds, the device initiates a soft-start interval. Over-Current Protection (monitor upper MOSFET) Soft-Start/EN The APW7073A monitors the voltage across the upper MOSFET and uses the OCSET pin to set the over-current The SS/EN pins control the soft-start and enable or trip point. disable the controller. Connect a soft-start capacitor from SS pin to GND to set the soft-start interval. Figure1. A resistor (ROCSET) connected between OCSET pin and the drain of the upper MOSFET will determine the over shows the soft-start interval. When VCC reaches its PowerOn-Reset threshold (9.5V), internal 30µA current source current limit. An internal 200µA current source will flow through this resistor, creating a voltage drop, which will starts to charge the capacitor. When the VSS reaches the enabled threshold about 1.8V, the internal 0.6V reference be compared with the voltage across the upper MOSFET. When the voltage across the upper MOSFET exceeds the starts to rise and follows the VSS ; the error amplifier output (VCOMP) suddenly raises to 1.35V, which is the voltage drop across the ROCSET, an over-current will be detected. The threshold of the over current limit is valley of the triangle wave of the oscillator, leads the VOUT to start-up. Until the VSS reaches about 4.2V, the internal therefore given by: reference completes the soft-start interval and reaches to 0.6V, and then VOUT is in regulation. The SS still rises ILIMIT = to 5.5V and then stops. TSoft − Start = t 2 − t1 = t1 IOCSET × R OCSET RDS (ON ) For the over-current, it is never occurred in the normal CSS ⋅ 2 .4 V ISS operating load range; the variation of all parameters in the above equation should be determined. Where: - The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user should determine CSS = external Soft-Start capacitor ISS = Soft-Start current=30µA the maximum RDS(ON) in manufacturer’s datasheet. - The minimum IOCSET (170µA) and minimum ROCSET should be used in the above equation. - Note that the ILIMIT is the current flow through the upper MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 10 www.anpec.com.tw APW7073A Function Description (Cont.) 1000 Over-Current Protection (Cont.) 900 An over current condition will shut down the device and discharge the CSS with a 30µA sink current and then RT Resistance (kΩ) 800 initiate the soft-start sequence. After two over-current events are counted, the device turns off both high-side and low-side MOSFETs and the converter output is latched to be floating. It requires a POR of VCC to restart. Switching Frequency The APW7073A provides the oscillator switching frequency adjustment. The device includes a 200kHz free- 700 600 500 400 300 200 100 0 running triangle wave oscillator. If operating in higher frequency than 200kHz, connect a resistor from RT pin 10 1000 Frequency (kHz) Figure 2. Oscillator Frequency vs. RT Resistance to the ground to increase the switching frequency. Conversely, if operating in lower frequency than 200kHz, 1000 connect a resistor from RT to the VCC to decrease the switching frequency. Figure 2. shows how to select the resistor for the desired frequency. Figure 3 shows more detail for the higher 900 RT Resistance (kΩ) 800 frequencies and Figure 4 shows the lower frequency detail. 700 600 500 400 300 200 100 0 200 300 400 500 600 700 800 900 1000 Frequency (kHz) Figure 3. Oscillator Frequency vs. RT Resistance (High Frequency) 1000 RT Resistance (kΩ) 900 800 700 600 500 400 300 200 50 70 90 110 130 150 170 Frequency (kHz) Figure 4. Oscillator Frequency vs. RT Resistance (Low Frequency) Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 11 www.anpec.com.tw APW7073A Application Information Output Voltage Selection Output Capacitor Selection The output voltage can be programmed with a resistive Higher capacitor value and lower ESR reduce the output divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switch- error amplifier, and the reference voltage is 0.6V. The output voltage is determined by: ing regulator applications. In some applications, multiple capacitors have to be parallelled to achieve the R VOUT = 0.6 × 1 + OUT R GND desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make Where ROUT is the resistor connected from VOUT to FB, and sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. RGND is the resistor connected from FB to GND. Output Inductor Selection Input Capacitor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor The input capacitor is chosen based on the voltage rating value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current and ripple and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher voltage can be approximated by: than the maximum input voltage. The maximum RMS current rating requirement is approximately I OUT/2, IRIPPLE = VIN − VOUT VOUT × FS × L VIN where IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. ∆VOUT = IRIPPLE × ESR If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the where Fs is the switching frequency of the regulator. capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1µF can be connected between the Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor’s ripple current and the drain of upper MOSFET and the source of lower MOSFET. regulator load transient response time. MOSFET Selection A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction switching loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the fol- the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of lowing equations: 2 PUPPER = IOUT ( 1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS the maximum output current. Once the inductance value has been chosen, select an inductor that is capable of 2 PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) Where IOUT is the load current carrying the required peak current without going into saturation. In some types of inductors, especially core TC is the temperature dependency of RDS(ON) FS is the switching frequency that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger tSW is the switching interval D is the duty cycle output ripple voltage. Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 12 www.anpec.com.tw APW7073A Application Information (Cont.) MOSFET Selection (Cont.) Note that both MOSFETs have conduction loss while the upper MOSFET includes an additional transition loss. The PWM modulator is shown in Figure 7. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by: VIN GAINPWM = ∆VOSC V IN The switching internal, tSW , is the function of the reverse transfer capacitance C RSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. OSC PWM Compensation ΔV OSC The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain Figure 7. The PWM Modulator The compensation network is shown in Figure 8. It provides a close loop transfer function with the highest tor and output capacitors. The transfer function of the LC filter is given by: 1 FESR = 2 × π × ESR × COUT zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: 1 1 // R2 + VCOMP sC1 sC2 GAINAMP = = 1 VOUT R1// R3 + sC3 The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. V OUT 1 1 s + ×s + R2 × C2 R1 + R3) × C3 ( R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 × C1× C2 R3 × C3 C OUT ESR The poles and zeros of the transfer function are: 1 FZ1 = 2 × π × R2 × C2 1 FZ2 = 2 × π × (R1 + R3) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 Figure 5. The Output LC Filter FLC -40dB/dec GAIN (dB) PHASE Driver should be added. The compensation network is shown in Figure 8. The output LC filter consists of the output induc- L PWM Comparator Output of Error Amplifier slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB, and V OUT V PHASE Driver FP2 = FESR 1 2 × π × R3 × C3 C1 -20dB/dec R3 C3 R2 C2 V OUT R1 Frequency(Hz) V COMP V REF Figure 6. The LC Filter GAIN and Frequency Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 FB Figure 8. Compensation Network 13 www.anpec.com.tw APW7073A Application Information (Cont.) PWM Compensation (Cont.) The poles and zero of this transfer functions are: The closed loop gain of the converter can be written as: FLC = GAINLC X GAINPWM X GAINAMP Figure 9. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the 1 2 × π × L × COUT R3 = R1 FS −1 2 × FLC C3 = 1 π × R3 × FS curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. 1. Choose a value for R1, usually between 1K and 5K. FZ1 FZ2 2. Select the desired zero crossover frequency FP1 FP2 GAIN (dB) FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: ∆VOSC FO R2 = × × R1 VIN FLC 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. Compensation Gain 20log (R2/R1) 20log (VIN/ΔVOSC) FLC FZ1 = 0.75 X FLC FESR Calculate the C2 by the equation: 1 C2 = 2 × π × R2 × FLC × 0.75 PWM & Filter Gain Converter Gain Frequency(Hz) 4. Set the pole at the ESR zero frequency FESR: Figure 9. Converter Gain and Frequency FP1 = FESR Calculate the C1 by the equation: C2 C1 = 2 × π × R2 × C2 × FESR − 1 5. Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. FP2 = 0.5 X FS FZ2 = FLC Combine the two equations will get the following component calculations: 1 + s × ESR × COUT GAINLC = 2 s × L × COUT + s × ESR × COUT + 1 Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 14 www.anpec.com.tw APW7073A Layout Consideration Layout Consideration the loads. The input capacitor GND should be close In any high switching frequency converter, a correct layout to the output capacitor GND and the lower MOSFET GND. is important to ensure proper operation of the regulator. With power devices switching at 300kHz, the resulting - The drain of the MOSFETs (VIN and PHASE nodes) current transient will cause voltage spike across the interconnecting impedance and parasitic circuit should be a large plane for heat sinking. elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is APW7073A VIN VCC carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by PVCC the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike BOOT during the switching interval. In general, using short, wide, and printed circuit traces should minimize interconnect- UGATE L O A D PHASE ing impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separating VOUT LGATE till combined using ground plane construction or single point grounding. Figure 10 illustrates the layout, with Figure 10. Layout Guidelines bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UGATE, LGATE) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and SS capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 15 www.anpec.com.tw APW7073A Package Information SOP–14 D E E1 SEE VIEW A h X 45 ° e c 0.25 A GAUGE PLANE SEATING PLANE A1 A2 b L VIEW A S Y M B O L SOP-14 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.010 0.004 0.25 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 8.55 8.75 0.337 0.344 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° e 0.049 1.27 BSC 0.050 BSC 8° Note: 1. Follow JEDEC MS-012 AB. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 16 www.anpec.com.tw APW7073A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-14 A 330.0± 2.00 H T1 C d D W E1 F 16.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 50 MIN. P0 P1 P2 4.0±0.10 8.0±0.10 2.0±0.10 D0 1.5+0.10 -0.00 D1 1.5 MIN. T A0 B0 K0 0.6+0.00 -0.40 6.40±0.20 9.00±0.20 2.10±0.20 (mm) Devices Per Unit Package Type SOP- 14 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 Quantity 2500 17 www.anpec.com.tw APW7073A Taping Direction Information SOP–14 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 18 www.anpec.com.tw APW7073A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 19 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7073A Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.5 - Nov., 2012 20 www.anpec.com.tw