datasheet EN71SN10F_130 balls_b

EN71SN10F
EN71SN10F
1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package
Features
• Multi-Chip Package
- NAND Flash Density: 1-Gbits
- Mobile DDR SDRAM Density: 512-Mbit
• Device Packaging
- 130 balls FBGA
Area: 8x9 mm; Height: 1.0 mm
• Operating Voltage
- NAND : 1.7V to 1.95V
- Mobile DDR SDRAM : 1.7V to 1.95V
• Operating Temperature :-25 °C to +85 °C
NAND FLASH
Mobile DDR SDRAM
• Voltage Supply: 1.8V (1.7V ~ 1.95V )
• Organization
- Memory Cell Array :
(64M + 2M) x 16bit for 1Gb
- Multiplexed address/ data
- Data Register : (1K + 32) x 16bit
• Automatic Program and Erase
- Page Program : (1K + 32) words
- Block Erase : (64K + 2K) words
• Page Read Operation
- Page Size : (1K + 32) words
- Random Read : 25µs (Max.)
- Serial Access : 45ns (Min.)
• Memory Cell: 1bit/Memory Cell
• Fast Write Cycle Time
- Page Program Time : 250µs (Typ.)
- Block Erase Time : 2ms (Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power
Transitions
• Reliable CMOS Floating-Gate Technology
• Endurance:
- 100K Program/Erase Cycles (with 1 bit/264
words ECC)
- Data Retention: 10 Years
• Command Register Operation
• Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
• NOP: 4 cycles
• Cache Program/Read Operation
• Copy-Back Operation
• EDO mode
• OTP Operation
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This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
Density: 512M bits
Organization: 8M words x16 bits x 4 banks
Power supply: VDD/VDDQ= 1.70~1.95V
Speed: 400Mbps (max.) for data rate
2KB page size
- Row address: A0 to A12
- Column address: A0 to A9
Four internal banks for concurrent operation
Interface: LVCMOS
Burst Length : 2, 4, 8, or 16
Burst Type : Sequential and Interleave
CAS# Latency (CL) : 3
Precharge: auto precharge option for each
burst access
Drive Strength: normal, 1/2, 1/4, 1/8
Refresh: auto Refresh and self-refresh
Refresh cycles: 8192 cycles/64ms
Optional Partial Array Self Refresh (PASR)
Auto Temperature Compensated Self Refresh
(ATCSR) by built-in temperature sensor
Deep Power Down Mode
Burst termination by burst stop command and
precharge command
DLL in not implemented
Double-data-rate architecture, two data access
per clock cycle
The high-speed data transfer is realized by the
2 bits prefetch pipelined architecture
Bidirectional data strobe (DQS) is transmitted
/received with data for capturing data at the
receiver
DQS edge-aligned with data for READs;
center-aligned with data for WRITEs
Differential clock inputs (CLK and CLK# )
Commands entered on each positive CLK edge;
data and data mask referenced to both edges
of DQS
Data mask (DM) for write data
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Ordering Information
NAND Flash
Mobile DDR SDRAM
Product ID
EN71SN10F-45EBWP
Package
Configuration
Speed
1Gb
(64M X 16 bits)
45ns
Configuration
Speed
512Mb (4 Banks
200MHz 130 ball FBGA
X 8M X 16 bits)
Operation
Temperature
Range
Wireless
MCP Block Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Ball Configuration
(TOP VIEW)
(FBGA 130, 8mmx9mmx1.0mm Body, 0.65mm Ball Pitch)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Table 1. Ball Description
Pin Name
NAND
VCC
VSS
I/O0-I/O15
ALE
CLE
CE#
RE#
WE#
WP#
R / B#
Type
Function
Supply
Supply
Input/output
Input
Input
Input
Input
Input
Input
Output
Mobile DDR SDRAM
VDD
Supply
VSSD
Supply
VDDQ
Supply
VSSQ
Supply
Supply Voltage
Ground
Data input/outputs, address inputs, or command inputs
Address Latch Enable
Command Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready/Busy (open-drain output)
Power Supply
Ground
DQ’s Power Supply: Isolated on the die for improved noise immunity.
Ground
CLK and CLK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CLK and negative edge of CLK# .
Input and output data is referenced to the crossing of CLK and CLK# (both
directions of crossing). Internal clock signals are derived from CLK, CLK#
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWERDOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN
(row ACTIVE in any bank). CKE is synchronous for all functions except for SELF
REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CLK,
CLK# and CKE, are disabled during power-down and self refresh mode which are
contrived for low standby power consumption.
CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is considered part of
the command code.
CLK, CLK#
Input
CKE
Input
CS#
Input
RAS#
,
CAS# , WE#
Input
CAS#, RAS# , and WE# (along with CS# ) define the command being entered.
A0-A12
Input
Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ / WRITE commands, to select one location out of
the memory array in the respective bank. The address inputs also provide the
opcode during a MODE REGISTER SET command.
BA0, BA1
Input
BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
DQ0- DQ15
Input /
Output
Data Input/Output pins operate in the same manner as on conventional DRAMs.
LDQS, UDQS
Input
Output
LDM, UDM
Input
/
Output with read data, input with write data. Edge-aligned with read data, centered
with write data. Used to capture write data. LDQS corresponds to the data on DQ0DQ7, UDQS corresponds to the data on DQ8-DQ15.
DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading matches the DQ
and DQS loading. LDM corresponds to the data on DQ0-DQ7, UDM corresponds to
the data on DQ8-DQ15.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
PACKAGE DIMENSION
130-BALL FBGA ( 8x9 mm )
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
NAND Flash Memory Operations
General Description
The NAND Flash is a 64Mx16bit with spare 2Mx16bit capacity. The NAND Flash is offered in 1.8V VCC
Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage
market. The memory is divided into blocks that can be erased independently so it is possible to preserve
valid data while old data is erased.
The NAND Flash contains 1024 blocks, composed by 64 pages consisting in two NAND structures of
32 series connected Flash cells. A program operation allows to write the 1056-Word page in typical
250us and an erase operation can be performed in typical 2ms on a 64-word for device block.
Data in the page mode can be read out at 45ns cycle time per Byte. The I/O pins serve as the ports for
address and command inputs as well as data input/output. The copy back function allows the
optimization of defective blocks management: when a page program operation fails the data can be
directly programmed in another page inside the same array section without the time consuming serial
data insertion phase. The cache program feature allows the data insertion in the cache register while
the data register is copied into the Flash array. This pipelined program operation improves the program
throughput when long files are written inside the memory. A cache read feature is also implemented.
This feature allows to dramatically improving the read throughput when consecutive pages have to be
streamed out. This NAND Flash includes extra feature: Automatic Read at Power Up.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
6
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Table 2. Pin Description
Symbol
I/O0 – I/O15
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
Pin Name
Function
The I/O pins are used to input command, address and data, and
Data Inputs/Outputs to output data during read operations. The I/O pins float to Hi-Z
when the chip is deselected or when the outputs are disabled.
The CLE input controls the activating path for commands sent to
Command Latch
the command register. When active high, commands are latched
Enable
into the command register through the I/O ports on the rising edge
of the WE# signal.
The ALE input controls the activating path for address to the
Address Latch
internal address registers. Addresses are latched on the rising
Enable
edge of WE# with ALE high.
The CE# input is the device selection control. When the device is
in the Busy state, CE# high is ignored, and the device does not
Chip Enable
return to standby mode in program or erase operation. Regarding
CE# control during read operation, refer to ’Page read’ section of
Device operation.
The RE# input is the serial data-out control, and when active
drives the data onto the I/O bus. Data is valid tREA after the falling
Read Enable
edge of RE# which also increments the internal column address
counter by one.
The WE# input controls writes to the I/O port. Commands,
Write Enable
address and data are latched on the rising edge of the WE# pulse.
The WP# pin provides inadvertent program/erase protection
Write Protect
during power transitions. The internal high voltage generator is
reset when the WP# pin is active low.
The R/B# output indicates the status of the device operation.
When low, it indicates that a program, erase or random read
Ready/Busy Output
operation is in process and returns to high state upon completion.
It is an open drain output and does not float to Hi-Z condition
when the chip is deselected or when outputs are disabled.
VCC
Power Supply
VSS
Ground
NC
No Connection
VCC is the power supply for device.
Lead is not internally connected.
Note: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC
or VSS disconnected.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
7
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Block Diagram
Vcc
Vss
X-Buffers
Latches
& Decoders
A11 – A26
1,024M + 32M Bit for 1Gb
NAND Flash Array
Y-Buffers
Latches
& Decoders
A0 – A10
Data Register & S/A
Y - Gating
Command
Command
Register
Vcc
I/O Buffers & Latches
Vss
Control Logic
& High Voltage
Generator
CE#
RE#
WE#
Global Buffers
Output
Driver
I/O0
I/O15
CLE ALE
WP#
Array Organization
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
8
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Address Cycle Map
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8 ~ I/O15
Address
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
L*
Column Address
2nd Cycle
A8
A9
A10
L*
L*
L*
L*
L*
L*
Column Address
3rd Cycle
A11
A12
A13
A14
A15
A16
A17
A18
L*
Row Address
4th Cycle
Note:
A19
A20
A21
A22
A23
A24
A25
A26
L*
Row Address
1. Column Address : Starting Address of the Register.
2. * L must be set to “Low”.
3. * The device ignores any additional input of address cycles than required.
Product Introduction
The NAND Flash is a 1,056Mbit memory organized as 64K rows (pages) by 1,056x16 columns. Spare
32x16 columns are located from column address of 1,024~1,055. A 1,056-word data register is
connected to memory cell arrays accommodating data transfer between the I/O buffers and memory
during page read and page program operations. The program and read operations are executed on a
page basis, while the erase operation is executed on a block basis. The memory array consists of 1,024
separately erasable 64K-work blocks. It indicates that the bit-by-bit erase operation is prohibited on the
NAND Flash.
The NAND Flash has addresses multiplexed into 16 I/Os. This scheme dramatically reduces pin counts
and allows system upgrades to future densities by maintaining consistency in system board design.
Command, address and data are all written through I/O's by bringing WE# to low while CE# is low.
Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable
(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands
require one bus cycle. For example, Reset Command, Status Read Command, etc require just one
cycle bus. Some other commands, like page read and block erase and page program, require two
cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the NAND Flash incorporates copy-back program
feature from one page to another page without need for transporting the data to and from the external
buffer memory.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
9
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Command Set
Function
1st Cycle
2nd Cycle
Read
00h
30h
Read for Copy Back
00h
35h
Read ID
90h
-
Reset
FFh
-
Page Program
80h
10h
Copy-Back Program
85h
10h
Block Erase
60h
D0h
85h
-
Random Data Input
(1)
(1)
05h
E0h
Read Status
Cache Program
Cache Read
70h
80h
31h
15h
-
Read Start for Last Page
Cache Read
3Fh
-
Random Data Output
Acceptable Command during Busy
O
O
Note:
1. Random Data Input / Output can be executed in a page.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Temperature Under Bias
Storage Temperature
Short Circuit Current
Symbol
VCC
VIN
VI/O
TBIAS
TSTG
IOS
Rating
-0.6 to +2.45
-0.6 to +2.45
-0.6 to VCC + 0.3 (< 2.45)
-40 to +125
Unit
V
℃
℃
mA
-65 to +150
5
Note:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA = – 25°C to 85°C)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
VSS
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Min.
1.7
0
10
Typ.
1.8
0
Max.
1.95
0
Unit
V
V
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
DC AND OPERATION CHARACTERISTICS
(Recommended operating conditions otherwise noted)
Parameter
Page Read with
Serial Access
Operating
Program
Current
Erase
Stand-by Current (TTL)
Stand-by Current (CMOS)
Input Leakage Current
Output Leakage Current
Symbol
Test Conditions
Min.
Typ.
Max.
ICC1
tRC=45ns, CE# =VIL, IOUT=0mA
-
15
30
ICC2
ICC3
ISB1
ISB2
ILI
ILO
CE# =VIH, WP# =0V/VCC
CE# = VCC -0.2, WP# =0V/ VCC
VIN=0 to VCC (max)
VOUT=0 to VCC (max)
-
15
15
10
-
30
30
1
50
±10
±10
(1)
-
0.8 x VCC
-
VCC +0.3
V
(1)
IOH=-100uA
IOL=+100uA
VOL=0.1V
-0.3
VCC -0.1
3
4
0.2 x VCC
0.1
-
V
V
V
mA
Input High Voltage
VIH
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
Output Low Current (R/B#)
VIL
VOH
VOL
IOL (R /B#)
Note:
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less.
2. Typical value are measured at VCC =1.8V, TA = 25℃. And not 100% tested.
VALID BLOCK
Symbol
NVB
Min.
1,004
Typ.
-
Max.
1,024
Unit
Blocks
Note:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may
develop while being used. The number of valid blocks is presented as first shipped. Invalid blocks
are defined as blocks that contain one or more bad bits which cause status failure during program
and erase operation. Do not erase or program factory-marked bad blocks. Refer to the attached
technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of
shipment and is guaranteed to be a valid block up to 1K program/erase cycles with 1 bit/264 words
ECC.
AC TEST CONDITION
(TA = – 25°C to 85°C, VCC=1.7V~1.95V)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Condition
0V to VCC
5 ns
VCC /2
1 TTL Gate and CL=30pF
Note:
* Refer to Ready / Busy# section, R/B# output’s Busy to Ready time is decided by the pull-up resistor (RP) tied to
R/B# pin.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
Unit
mA
mA
uA
uA
uA
EN71SN10F
CAPACITANCE
(TA = 25°C, VCC=1.8V, f =1.0MHz)
Item
Symbol
Test Condition
Input / Output Capacitance
CI/O
VIL = 0V
Input Capacitance
CIN
VIN = 0V
Note: Capacitance is periodically sampled and not 100% tested.
Min.
-
Max.
10
10
Unit
pF
pF
MODE SELECTION
CLE
ALE
CE#
H
L
L
WE#
RE#
WP#
L
H
X
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
X
Data Output
H
X
X
X
X
H
X
X
X
X
X
X
H
X
X
X
X
X
H
X
X (1)
X
X
X
L
X
X
H
X
X
0V/VCC(2)
Note:
1. X can be VIL or VIH.
2. WP# should be biased to CMOS high or CMOS low for stand-by.
Mode
Read Mode
Write Mode
Command Input
Address Input (4 clock)
Command Input
Address Input (4 clock)
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
Stand-by
Program / Erase Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Unit
Program Time
tPROG
250
700
us
Dummy Busy Time for Cache
3
700
us
tCBSY
Program
Number of Partial Program Cycles
4
Cycle
NOP
in the Same Page
Block Erase Time
tBERS
2
10
ms
Note:
1. Typical program time is defined as the time within which more than 50% of the whole pages are
programmed at 1.8V VCC and 25°C temperature.
2. tPROG is the average program time of all pages. Users should be noted that the program time
variation from page to page is possible.
3. Max. time of tCBSY depends on timing between internal program completion and data in.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min.
Max.
Unit
tCLS(1)
CLE Setup Time
25
ns
CLE Hold Time
tCLH
10
ns
CE# Setup Time
tCS(1)
35
ns
CE# Hold Time
tCH
10
ns
WE# Pulse Width
tWP
25
ns
ALE Setup Time
tALS(1)
25
ns
ALE Hold Time
tALH
10
ns
Data Setup Time
tDS(1)
20
ns
Data Hold Time
tDH
10
ns
Write Cycle Time
tWC
45
ns
WE# High Hold Time
tWH
15
ns
ALE to Data Loading Time
tADL(2)
100
ns
Note:
1. The transition of the corresponding control pins must occur only once while WE# is held low.
2. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data
cycle.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
13
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
AC Characteristics for Operation
Parameter
Data Transfer from Cell to Register
ALE to RE# Delay
CLE to RE# Delay
Ready to RE# Low
RE# Pulse Width
WE# High to Busy
WP# Low to WE# Low (disable mode)
WP# High to WE# Low (enable mode)
Read Cycle Time
RE# Access Time
CE# Access Time
RE# High to Output Hi-Z
CE# High to Output Hi-Z
CE# High to ALE or CLE Don’t Care
RE# High to Output Hold
RE# Low to Output Hold
CE# High to Output Hold
RE# High Hold Time
Output Hi-Z to RE# Low
RE# High to WE# Low
WE# High to RE# Low
Read
Device Resetting
Program
Time during ...
Erase
Ready
Cache Busy in Read Cache
(following 31h and 3Fh)
Symbol
Min.
Max.
Unit
tR
tAR
tCLR
tRR
tRP
tWB
10
10
20
25
-
25
100
us
ns
ns
ns
ns
ns
tWW
100
-
ns
tRC
tREA
tCEA
tRHZ
tCHZ
tCSD
tRHOH
tRLOH
tCOH
tREH
tIR
tRHW
tWHR
45
0
15
5
15
15
0
100
60
-
30
45
100
30
5
10
500
5(1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
us
-
30
us
tRST
tDCBSYR
Note:
1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
14
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
NAND Flash Technical Notes
Mask Out Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is
not guaranteed by Eon. The information regarding the initial invalid block(s) is called as the initial invalid
block information. Devices with initial invalid block(s) have the same quality level as devices with all
valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the
performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address
mapping.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K
program/erase cycles with 1 bit/ 264 words ECC.
Identifying Initial Invalid Block(s) and Block Replacement Management
Unpredictable behavior may result from programming or erasing the defective blocks. The under figure
illustrates an algorithm for searching factory-mapped defects, and the algorithm needs to be executed
prior to any erase or program operations.
A host controller has to scan blocks from block 0 to the last block using page read command and check
the data at the column address of 0 or 1,023. If the read data is not FFh, the block is interpreted as an
invalid block. The initial invalid block information is erasable, and which is impossible to be recovered
once it has been erased. Therefore, the host controller must be able to recognize the initial invalid block
information and to create a corresponding table to manage block replacement upon erase or program
error when additional invalid blocks develop with Flash memory usage.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
15
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Algorithm for Bad Block Scanning
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
16
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Error in Write or Read Operation
Within its lifetime, the additional invalid blocks may develop with NAND Flash memory. Refer to the
qualification report for the actual data. The following possible failure modes should be considered to
implement a highly reliable system. In the case of status read failure after erase or program, block
replacement should be done. Because program status fail during a page program does not affect the
data of the other pages in the same block, block replacement can be executed with a page-sized buffer
by finding an erased empty block and reprogramming the current target data and copying the rest of the
replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it
is recommended that the read or verification failure due to single bit error be reclaimed by ECC without
any block replacement. The additional block failure rate does not include those reclaimed blocks.
Failure
Write
Read
Erase Failure
Program Failure
Single Bits Failure
Detection and Countermeasure sequence
Read Status after Erase → Block Replacement
Read Status after Program → Block Replacement
Verify ECC → ECC Correction
Note:
1. Error Correcting Code --> Hamming Code etc.
2. Example: 1bit correction / 264 words
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
17
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Program Flow Chart
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
18
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Erase Flow Chart
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
19
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Read Flow Chart
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
20
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Block Replacement
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page
of the block to MSB (Most Significant Bit) pages of the block. Random page address programming is
prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB page doesn’t need to be page 0.
Page 63
(64)
(64)
Page 63
:
Page 31
:
(32)
(1)
Page 31
:
:
Page 2
(3)
Page 2
(3)
Page 1
(2)
Page 1
(32)
Page 0
(1)
Page 0
(2)
Data register
Data register
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
DATA IN: Data (1)
Data (64)
This Data Sheet may be revised by subsequent versions
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21
Data (64)
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
System Interface Using CE# don’t-care
For an easier system interface, CE# may be inactive during the data-loading or serial access as shown
below. The internal 1,056 words page registers are utilized as separate buffers for this operation and the
system design gets more flexible. In addition, for voice or audio applications that use slow cycle time on
the order of u-seconds, de-activating CE# during the data-loading and serial access would provide
significant savings in power consumption.
Program / Read Operation with “CE# not-care”
Address Information
DATA
Data In / Out
1,056 words
I/O
I/Ox
I/O0~ I/O15
Col. Add1
A0 ~ A7
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
ADDRESS
Col. Add2
Row Add1
A8 ~ A10
A11 ~ A18
22
Row Add2
A19 ~ A26
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Command Latch Cycle
Address Latch Cycle
Input Data Latch Cycle
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
23
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Serial access Cycle after Read (CLE = L, WE# = H, ALE = L)
Note:
1. Dout transition is measured at ±200mV from steady state voltage at I/O with load.
2. tRHOH starts to be valid when frequency is lower than 20MHz.
Serial access Cycle after Read (EDO Type CLE = L, WE# = H, ALE = L)
Note:
1. Transition is measured at ±200mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3. tRLOH is valid when frequency is higher than 20MHz.
4. tRHOH starts to be valid when frequency is lower than 20MHz.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
24
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Status Read Cycle
Read Operation
Read Operation (Intercepted by CE#)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
25
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Random Data Output In a Page
Page Program Operation
Note: tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data
cycle.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
26
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Page Program Operation with Random Data Input
Note: tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data
cycle.
Copy-Back Program Operation with Random Data Input
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
27
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Cache Program Operation
Cache Read Operation
CE#
CLE
ALE
WE
RE#
I/Ox
[7..0]
R/B#
CE#
CLE
ALE
WE
RE#
I/Ox
[7..0]
R/B#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
28
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Block Erase Operation
Read ID Operation
ID Definition Table
ID Access command = 90h
1st Cycle
(Maker Code)
C8h
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
2nd Cycle
(Device Code)
B1h
3rd Cycle
4th Cycle
5th Cycle
80h
55h
40h
Description
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages,
etc.
Page Size, Block Size, Redundant Area Size, Organization, Serial Access Minimum.
Plane Number, Plane Size
This Data Sheet may be revised by subsequent versions
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29
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
3rd ID Data
Internal Chip Number
Cell Type
Number of
Simultaneously
Programmed Page
Interleave Program
Between
multiple
chips
Cache Program
Description
1
2
4
8
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
1
2
4
8
Not Support
I/O7
I/O5
I/O4
0
0
1
1
0
1
0
1
I/O5
I/O4
I/O3
I/O2
0
0
1
1
0
1
0
1
I/O3
I/O2
I/O1
0
0
1
1
I/O0
0
1
0
1
I/O1
I/O0
0
0
1
1
0
1
0
1
0
Support
Not Support
Support
I/O6
1
0
1
4th ID Data
Page Size
(w/o redundant area)
Redundant Area Size
(byte/512byte)
Block Size
(w/o redundant area)
Organization
Serial Access
Minimum
Descriptio
n
1KB
2KB
4KB
8KB
8
16
64KB
128KB
256KB
512KB
x8
x16
45ns
Reserved
Reserved
Reserved
I/O7
I/O6
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
This Data Sheet may be revised by subsequent versions
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30
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
5th ID Data
ECC Level
Plane Number
Plane Size
(w/o redundant area)
Reserved
Description
1 bit ECC/512Byte
2 bit ECC/512Byte
4 bit ECC/512Byte
Reserved
1
2
4
8
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
Reserved
I/O7
I/O6
0
0
0
0
1
1
1
1
I/O5
0
0
1
1
0
0
1
1
I/O4
I/O3
I/O2
0
0
1
1
0
1
0
1
I/O1
0
0
1
1
I/O0
0
1
0
1
0
1
0
1
0
1
0
1
0
DEVICE OPERATION
Page Read
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by
writing 00h command, four-cycle address, and 30h command. After initial power up, the 00h command
can be skipped because it has been latched in the command register. The 1,056 words of data on a
page are transferred to cache registers via data registers within 25us (tR). Host controller can detect the
completion of this data transfer by checking the R/B# output. Once data in the selected page have been
loaded into cache registers, each Byte can be read out in 45ns cycle time by continuously pulsing RE#.
The repetitive high-to-low transitions of RE# clock signal make the device output data starting from the
designated column address to the last column address.
The device can output data at a random column address instead of sequential column address by using
the Random Data Output command. Random Data Output command can be executed multiple times in
a page.
After power up, device is in read mode so 00h command cycle is not necessary to start a read operation.
A page read sequence is illustrated in under figure, where column address, page address are placed in
between commands 00h and 30h. After tR read time, the R/B# de-asserts to ready state. Read Status
command (70h) can be issued right after 30h. Host controller can toggle RE# to access data starting
with the designated column address and their successive bytes.
This Data Sheet may be revised by subsequent versions
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31
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Read Operation
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
32
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Random Data Output In a Page
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
33
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Page Program
The device is programmed based on the unit of a page, and consecutive partial page programming on
one page without intervening erase operation is strictly prohibited. Addressing of page program
operations within a block should be in sequential order. A complete page program cycle consists of a
serial data input cycle in which up to 1,056 words of data can be loaded into data register via cache
register, followed by a programming period during which the loaded data are programmed into the
designated memory cells.
The serial data input cycle begins with the Serial Data Input command (80h), followed by a four-cycle
address input and then serial data loading. The bytes not to be programmed on the page do not need to
be loaded. The column address for the next data can be changed to the address follows Random Data
Input command (85h). Random Data Input command may be repeated multiple times in a page. The
Page Program Confirm command (10h) starts the programming process. Writing 10h alone without
entering data will not initiate the programming process. The internal write engine automatically executes
the corresponding algorithm and controls timing for programming and verification, thereby freeing the
host controller for other tasks. Once the program process starts, the host controller can detect the
completion of a program cycle by monitoring the R/B# output or reading the Status bit (I/O6) using the
Read Status command. Only Read Status and Reset commands are valid during programming. When
the Page Program operation is completed, the host controller can check the Status bit (I/O0) to see if
the Page Program operation is successfully done. The command register remains the Read Status
mode unless another valid command is written to it.
A page program sequence is illustrated in under figure, where column address, page address, and data
input are placed in between 80h and 10h. After tPROG program time, the R/B# de-asserts to ready state.
Read Status command (70h) can be issued right after 10h.
Program & Read Status Operation
Random Data Input In a page
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
34
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Cache Program
Cache Program is an extension of Page Program, which is executed with 1,056-word data registers,
and is available only within a block. Since the device has 1 page of cache memory, serial data input
may be executed while data stored in data register are programmed into memory cell.
After writing the first set of data up to 1,056 words into the selected cache registers, Cache Program
command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to
start internal program operation. To transfer data from cache registers to data registers, the device
remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next
data-input while the internal programming gets started with the data loaded into data registers. Read
Status command (70h) may be issued to find out when cache registers become ready by polling the
Cache-Busy status bit (I/O6). Pass/fail status of only the previous page is available upon the return to
Ready state. When the next set of data is inputted with the Cache Program command, tCBSY is affected
by the progress of pending internal programming. The programming of the cache registers is initiated
only when the pending program cycle is finished and the data registers are available for the transfer of
data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identity the
completion of internal programming. If the system monitors the progress of programming only with R/B#,
the last page of the target programming sequence must be programmed with actual Page Program
command (10h).
Cache Program (available only within a block)
Note:
1. Since programming the last page does not employ caching, the program time has to be that of Page
Program. However, if the previous program cycle with the cache data has not finished, the actual
program cycle of the last page is initiated only after completion of the previous cycle, which can be
expressed as the following formula.
2. tPROG = Program time for the last page + Program time for the (last-1)th page – (Program command
cycle time + Last page data loading time)
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
35
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Copy-Back Program
Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming
data reloading when there is no bit error detected in the stored data. The benefit is particularly obvious
when a portion of a block is updated and the rest of the block needs to be copied to a newly assigned
empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of Copy-Back
Program with Destination address. A Read for Copy-Back operation with “35h” command and the
Source address moves the whole 1,056-word data into the internal buffer. The host controller can detect
bit errors by sequentially reading the data output. Copy-Back Program is initiated by issuing Page-Copy
Data-Input command (85h) with Destination address. If data modification is necessary to correct bit
errors and to avoid error propagation, data can be reloaded after the Destination address. Data
modification can be repeated multiple times as shown in under figure. Actual programming operation
begins when Program Confirm command (10h) is issued. Once the program process starts, the Read
Status command (70h) may be entered to read the status register. The host controller can detect the
completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status
Register. When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The
command register remains Read Status mode until another valid command is written to it.
Page Copy-Back Program Operation
Page Copy-Back Program Operation with Random Data Input
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
36
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Block Erase
The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a two-cycle
row address, in which only Plane address and Block address are valid while Page address is ignored.
The Erase Confirm command (D0h) following the row address starts the internal erasing process. The
two-step command sequence is designed to prevent memory content from being inadvertently changed
by external noise. At the rising edge of WE# after the Erase Confirm command input, the internal
control logic handles erase and erase-verify. When the erase operation is completed, the host controller
can check Status bit (I/O0) to see if the erase operation is successfully done. The under figure illustrates
a block erase sequence, and the address input (the first page address of the selected block) is placed in
between commands 60h and D0h. After tBERASE erase time, the R/B# de-asserts to ready state. Read
Status command (70h) can be issued right after D0h to check the execution status of erase operation.
Block Erase Operation
Read Status
A status register on the device is used to check whether program or erase operation is completed and
whether the operation is completed successfully. After writing 70h command to the command register, a
read cycle outputs the content of the status register to I/O pins on the falling edge of CE# or RE#,
whichever occurs last. These two commands allow the system to poll the progress of each device in
multiple memory connections even when R/B# pins are common-wired. RE# or CE# does not need to
toggle for status change.
The command register remains in Read Status mode unless other commands are issued to it. Therefore,
if the status register is read during a random read cycle, a read command (00h) is needed to start read
cycles.
Status Register Definition for 70h Command
I/O
Page
Program
Block Erase
Read
Cache Read
I/O0
Pass / Fail
Pass / Fail
NA
NA
I/O1
I/O2
I/O3
I/O4
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
I/O5
NA
NA
NA
True Ready / Busy
I/O6
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
I/O7
Write Protect
Write Protect
Write Protect
Write Protect
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
37
Definition
Pass: 0
Fail: 1
Don’t cared
Don’t cared
Don’t cared
Don’t cared
Busy: 0
Ready: 1
Busy: 0
Ready: 1
Protected: 0
Not Protected: 1
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register,
followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (C8h),
and the device code and 3rd, 4th and 5th cycle ID respectively. The command register remains in Read
ID mode until further commands are issued to it.
Read ID Operation
ID Definition Table
Maker Code
Device Code
3rd Cycle
4th Cycle
5th Cycle
C8h
B1h
80h
55h
40h
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is
in Busy State during random read, program or erase mode, the reset operation will abort these
operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status
Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset
command will be accepted by the command register. The R/B# pin changes to low for tRST after the
Reset command is written. Refer to Figure below.
Reset Operation
Device Status Table
Operation mode
After Power-up
00h Command is latched
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
38
After Reset
Waiting for next command
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Cache Read
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read
command (00h-30h) is always issued before invoking Cache Read. After issuing the Cache Read
command (31h), read data of the designated page (page N) are transferred from data registers to cache
registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is transferred to
data registers while the data in the cache registers are being read out. Host controller can retrieve
continuous data and achieve fast read performance by iterating Cache Read operation. The Read Start
for Last Page Cache Read command (3Fh) is used to complete data transfer from memory cells to data
registers.
Read Operation with Cache Read
CLE
CE#
WE
ALE
RE#
I/Ox
R/B#
CLE
CE#
WE
ALE
RE#
I/Ox
R/B#
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
39
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
READY/BUSY#
The device has an R/B# output that provides a hardware method of indicating the completion of a page
program, erase and random read completion. The R/B# pin is normally high but transitions to low after
program or erase command is written to the command register or random read is started after address
loading. It returns to high when the internal controller has finished the operation. The pin is an opendrain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is
related to tr (R/B#) and current drain during busy (ibusy), an appropriate value can be obtained with the
following reference chart. Its value can be determined by the following guidance.
Ready/ Busy# Pin Electrical Specifications
R/B#
RP value guidance
1.85V
Rp (min)
3 mA
where IL is the sum of the input currents of all devices tied to the R/ B# pin.
RP (max) is determined by maximum permissible limit of tr
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
40
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Data Protection & Power-up sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power
on sequence. During the initialization the device R/B# signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are 70h.
The WP# signal is useful for protecting against data corruption at power on/off.
AC Waveforms for Power Transition
Write Protect Operation
Enabling WP# during erase and program busy is prohibited. The erase and program operations are
enabled and disabled as follows:
Enable Programming:
NOTE: WP# keeps “High” until programming finish.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
41
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Disable Programming:
Enable Erasing:
NOTE: WP keeps “High” until erasing finish.
Disable Erasing:
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
42
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
One-Time Programmable (OTP) Operations
This flash device offers one-time programmable memory area. Thirty full pages of OTP data are
available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only
through the OTP commands.
The OTP area leaves the factory in an unwritten state. The OTP area cannot be erased, whether it is
protected or not. Protecting the OTP area prevents further programming of that area.
The OTP area is only accessible while in OTP operation mode. To set the device to OTP operation
mode, issue the Set Feature (EFh-90h-01h) command. When the device is in OTP operation mode,
subsequent Read and/or Page Program are applied to the OTP area. When you want to come back to
normal operation, you need to use EFh-90h-00h for OTP mode release. Otherwise, device will stay in
OTP mode.
To program an OTP page, issue the Serial Data Input (80h) command followed by 4 address cycles.
The first two address cycles are column address. For the third cycle, select a page in the range of 00h
through 1Dh. The fourth cycle is fixed at 00h. Next, up to 1,056 words of data can be loaded into data
register. The bytes other than those to be programmed do not need to be loaded. This device supports
Random Data Input (85h) command, which can be operated multiple times in a page. The column
address for the next data to be entered may be changed to the address follows the Random Data Input
command. The Page Program confirm (10h) command initiates the programming process. The internal
control logic automatically executes the programming algorithm, timing and verification. Please note that
no partial-page program is allowed in the OTP area. In addition, the OTP pages must be programmed in
the ascending order. A programmed OTP page will be automatically protected.
Similarly, to read data from an OTP page, set the device to OTP operation mode and then issue the
Read (00h-30h) command. The device may output random data (not in sequential order) in a page by
writing Random Data Output (05h-E0h) command, which can be operated multiple times in a page. The
column address for the next data to be output may be changed to the address follows the Random Data
Output command.
All pages in the OTP area will be protected simultaneously by issuing the Set Feature (EFh-90h-03h)
command to set the device to OTP protection mode. After the OTP area is protected, no page in the
area is programmable and the whole area cannot be unprotected.
The Read Status (70h) command is the only valid command for reading status in OTP operation mode.
OTP Modes and Commands
OTP Operation mode
OTP Protection mode
OTP Release mode
Set feature
Read
EFh-90h-01h
Page Program
EFh-90h-01h
Program Protect
EFh-90h-03h
Leave OTP mode
EFh-90h-00h
Command
00h-30h
80h-10h
80h-10h
OTP Area Details
Description
Number of OTP pages
OTP page address
Number of partial page programs for each page in the OTP area
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
43
Value
30
01h – 1Eh
1
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Mobile DDR SDRAM Memory Operations
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
44
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
ELECTRICAL SPECIFICATIONS
● All voltages are referenced to VSS (GND).
● After power-up, wait more than 200 μs and then, execute power on sequence and CBR (Auto) refresh
before proper device operation is achieved.
Absolute Maximum Rating
Parameter
Symbol
Value
Unit
VIN, VOUT
-0.5 ~ 2.3
V
Voltage on VDD supply relative to VSS
VDD
-0.5 ~ 2.3
V
Voltage on VDDQ supply relative to VSS
VDDQ
-0.5 ~ 2.3
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
-25 ~ +85
°C
TSTG
-55 ~ +125
°C
Voltage on any pin relative to VSS
Storage temperature (plastic)
Caution:
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
Recommended DC Operating Conditions
Recommended operating conditions unless otherwise noted, VDD / VDDQ = 1.7~1.95V
Parameter
Pins
Supply voltage
Input high voltage
Input low voltage
All other
input pins
DC input voltage
DC input differential voltage
AC input differential voltage
AC input differential cross
point voltage
DC input high voltage
DC input low voltage
AC input high voltage
AC input low voltage
CLK,
CLK#
DQ, DM,
DQS
Symbol
Min
Typ.
Max
Unit
Note
VDD / VDDQ
1.7
1.8
1.95
V
1
VSS / VSSQ
0
0
0
V
VIH
0.8 x VDDQ
-
VDDQ + 0.3
V
VIL
-0.3
-
0.2 x VDDQ
V
VIN
-0.3
-
VDDQ + 0.3
V
VID (DC)
0.4 x VDDQ
VDDQ + 0.6
V
5
VID (AC)
0.6 x VDDQ
VDDQ + 0.6
V
5
VIX (AC)
0.4 x VDDQ
0.6 x VDDQ
V
6
VIHD (DC)
0.7 x VDDQ
VDDQ + 0.3
V
VILD (DC)
-0.3
0.3 x VDDQ
V
VIHD (AC)
0.8 x VDDQ
VDDQ + 0.3
V
VILD (AC)
-0.3
0.2 x VDDQ
V
0.5 x VDDQ
Note:
1. VDDQ must be equal to VDD.
2. VIH (max.) = 2.3V (pulse width ≤ 5ns).
3. VIL (min.) = -0.5V (pulse width ≤ 5ns).
4. All voltage referred to VSS and VSSQ must be same potential.
5. VID (DC) and VID (AC) are the magnitude of the difference between the input level on CLK and the input level on
CLK#.
6. The value of VIX is expected to be 0.5 x VDDQ and must track variations in the DC level of the same.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
45
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
DC Characteristics 1
Recommended operating conditions unless otherwise noted, VDD / VDDQ = 1.7~1.95
Parameter
Symbol
Max.
Unit
Test Condition
One bank active-prechange, tRC= tRC (min); tCK = tCK
(min); CKE = HIGH; CS# = HIGH between valid
commands; address inputs are SWITCHING; data
input signals are STABLE
All banks idle, CKE = LOW; CS# = HIGH, tCK = tCK
(min); address & control inputs are SWITCHING;
data input signals are STABLE
Operating Current
(ACT-PRE)
IDD0
85
mA
Standby Current in
power-down mode
IDD2P
0.8
mA
Standby Current in
power-down mode
IDD2PS
0.6
mA
IDD2N
7
mA
IDD2NS
2
mA
IDD3P
3
mA
IDD3PS
2
mA
IDD3N
10
mA
One bank active, CKE = HIGH, CS# = HIGH, tCK =
tCK (min); address & control inputs are SWITCHING;
data input signals are STABLE
IDD3NS
7
mA
One bank active, CKE = HIGH; CS# = HIGH, CLK=
LOW, CLK# = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
Operating Current
(Burst Mode)
IDD4
135
mA
One bank active; BL=4; CL=3; tCK = tCK (min);
continuous read bursts; IOUT = 0 mA; address inputs
are SWITCHING; 50% data changing each burst
Auto Refresh
Current
IDD5
80
mA
CKE = HIGH; tCK = tCK (min); tRFC = tRFC (min);
address and control inputs are SWITCHING; data
input signals are STABLE
Deep Power-down
Current
IDD8
10
uA
Address and control pins are disable;
data input signals are STABLE
Standby Current in
non power-down
mode
Active Standby
Current in powerdown mode
Active Standby
Current in powerdown mode with
clock stop
Active Standby
Current in non
power-down mode
Active Standby
Current in non
power-down mode
with clock stop
Note
All banks idle, CKE = LOW; CS# = HIGH, CLK =
LOW, CLK# = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
All banks idle, CKE = HIGH; CS# = HIGH, tCK = tCK
(min); address & control inputs are SWITCHING;
data input signals are STABLE
All banks idle, CKE = HIGH; CS# = HIGH, CLK =
LOW, CLK# = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
One bank active, CKE = LOW; CS# = HIGH, tCK =
tCK (min); address & control inputs are SWITCHING;
data input signals are STABLE
One bank active, CKE = LOW; CS# = HIGH, CLK =
LOW, CLK# = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
46
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Advanced Data Retention current ( VDD/VDDQ=1.70~1.95V )
Parameter
(Self Refresh Current)
Symbol
Max.
Unit
250
uA
220
uA
PASR=”010” (1BK)
200
uA
PASR=”000” (full)
480
uA
350
uA
PASR=”000” (full)
IDD6
PASR=”001” (2BK)
IDD6
PASR=”001” (2BK)
PASR=”010” (1BK)
280
uA
PASR=”000” (full)
600
uA
400
uA
IDD6
PASR=”001” (2BK)
Condition
Note
-25 C ° ~ +40 C°
CKE=L
+40 C ° ~+70 C°
CKE=L
+70 C ° ~ +85 C°
CKE=L
300
uA
Note: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by Test Conditions.
3. Definitions for IDD:
LOW is defined as V IN ≤ 0.1 * V DDQ;
HIGH is defined as V IN ≥ 0.9 * V DDQ;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
Address and command: inputs changing between HIGH and LOW once per two clock cycles;
Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are
STABLE.
PASR=”010” (1BK)
DC Characteristics 2
Recommended operating conditions unless otherwise noted, VDD / VDDQ = 1.7~1.95
Parameter
Symbol
Min
Max.
Unit
Pins
Input leakage current
ILI
-2
2
uA
0 ≤ VIN ≤ VDDQ
Output leakage current
ILO
-1.5
1.5
uA
0 ≤ VOUT ≤ VDDQ
DQ = disable
Output high voltage
VOH
0.9 x VDDQ
V
IOH = -0.1mA
Output low voltage
VOL
-
V
IOL = 0.1mA
0.1 x VDDQ
Note
Pin Capacitance
Parameter
Pins
Symbol
MIN
MAX
Unit
Notes
CLK, CLK#
CI1
1.5
3.5
pF
1
All other input-only pins
CI2
1.5
3.0
pF
1
CLK, CLK#
CDI1
-
0.25
pF
1
All other input-only pins
CDI2
-
0.5
pF
1
Data Input/output capacitance
DQs, DQS, DM
CIO
2.0
4.5
pF
1, 2
Delta Input/output capacitance:
DQs, DQS, DM
CDIO
-
0.5
pF
1
Input capacitance:
Delta Input capacitance
Note:
1. These parameters are measured on conditions: f = 100MHz, VOUT = VDDQ/2, ΔVOUT = 0.2V, TA = +25°C.
2. DOUT circuits are disabled.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
47
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
AC Characteristics (Reference)
o
o
Recommended operating condition unless otherwise noted, VDD/VDDQ = 1.7~1.95V, TA = -25 C to 85 C
Parameter
200MHz
Symbol
min
max
Unit
Note
Clock cycle time
tCK
5.0
CLK high-level width
tCH
0.45
0.55
tCK
CLK low-level width
tCL
0.45
0.55
tCK
CLK half period
tHP
Min (tCH, tCL)
-
tCK
DQ output access time from CLK, CLK#
tAC
2.0
5.0
ns
DQS-in cycle time
DQS output access time from CLK,
CLK#
DQ-out high-impedance from CLK, CLK#
tDSC
0.9
1.1
tCK
tDQSCK
2.0
5.0
ns
2, 8
tHZ
-
5.0
ns
5, 8
DQ-out low-impedance from CLK, CLK#
tLZ
1.0
-
ns
6, 8
tDQSQ
-
0.4
ns
3
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
-
ns
4
Data hold skew factor
tQHS
-
0.5
ns
DQ and DM input setup time
tDS
0.5
-
ns
3
DQ and DM input hold time
tDH
0.5
-
ns
3
DQ and DM input pulse width
tDIPW
1.6
-
ns
Read Preamble
tRPRE
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
tCK
Write preamble setup time
tWPRES
0
-
ns
Write preamble
tWPRE
0.25
-
tCK
Write postamble
Write command to first DQS latching
transition
DQS falling edge to CLK setup time
tWPST
0.4
0.6
tCK
tDQSS
0.75
1.25
tCK
tDSS
0.2
-
tCK
DQS falling edge hold time from CLK
tDSH
0.2
-
tCK
DQS input high pulse width
tDQSH
0.4
-
tCK
DQS input low pulse width
tDQSL
0.4
-
tCK
Address and control input setup time
tIS
0.9
-
ns
3
Address and control input hold time
tIH
0.9
-
ns
3
Address and control input pulse width
tIPW
2.3
-
ns
3
Mode register set command cycle time
tMRD
2
-
tCK
Active to precharge command period
tRAS
40
120000
ns
Active to Active/Auto-refresh command period
tRC
55
-
ns
Auto-refresh to Active/ Auto-refresh command
period
tRFC
96
-
ns
Active to Read/Write delay
tRCD
15
-
ns
DQS to DQ skew
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
48
ns
2, 8
7
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Parameter
Symbol
Precharge to Active command period
Column address to column address
delay
Active to Active command period
200MHz
Unit
min
max
tRP
15
-
ns
tCCD
1
-
tCK
tRRD
10
-
ns
tWR
15
tDAL
-
-
tSREX
120
-
ns
Power-down entry
tPDEN
2
-
tCK
Power-down exit to command input
tPDEX
1
-
tCK
Internal Write to READ command delay
tWTR
2
-
tCK
Refresh period
tREF
-
64
ms
Average periodic refresh interval
tREFI
7.8
us
CKE minimum pulse width
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay (to input all
data)
Burst stop command to write command
delay (CL=3)
Burst stop command to DQ high-Z
(CL=3)
Read command to write command delay
(to output all data) (CL=3)
Precharge command to high-Z (CL=3)
tCKE
2
-
tCK
tWPD
4+BL/2
-
tCK
tRPD
BL/2
-
tCK
tWRD
3+BL/2
-
tCK
tBSTW
3
-
tCK
tBSTZ
3
-
tCK
tWRD
3+BL/2
-
tCK
tHZP
3
-
tCK
tMRD
2
-
tCK
WRITE recovery time
Auto precharge write
precharge time
Self-Refresh exit period
recovery
Mode register set command cycle time
and
Note
ns
9
Note:
1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver strength is
assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
2. This parameter defines the signal transition delay from the cross point of CK and CK#. The signal transition is
defined to occur when the signal level crossing VDDQ/2.
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals. The signal
transition is defined to occur when the signal level crossing VDDQ/2.
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The timing reference
is cross point of CK and CK#. This parameter is not referred to a specific DOUT voltage level, but specify when the
device output stops driving.
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This parameter is
not referred to a specific DOUT voltage level, but specify when the device output begins driving.
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific reference
voltage to judge this transition is not given.
8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading condition.
9. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and minimum 1 clock
for tRP. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher
integer.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
49
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Test Conditions
Parameter
Symbol
Value
Unit
Note
Input high voltage
VIH (AC)
0.8 x VDDQ
V
1
Input low voltage
VIL (AC)
0.2 x VDDQ
V
1
VID (AC)
1.4
V
1
VIX (AC)
VDDQ/2 with VDD=VDDQ
V
SLEW
1
V/ ns
CL
15
pF
Input differential voltage, CLK and CLK#
inputs
Input differential cross point voltage,
CLK and CLK# inputs
Input signal skew rate
Output load
1
Note:
1. VDD=VDDQ.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
50
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Block Diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
51
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
PIN FUNCTION
CLK, CLK# (input pins)
The CLK and the CLK# are the master clock inputs. All inputs except DMs, DQSs and DQs are referred
to the cross point of the CLK rising edge and the CK# falling edge. When a read operation, DQSs and
DQs are referred to the cross point of the CLK and the CLK#. When a write operation, DMs and DQs
are referred to the cross point of the DQS and the VDDQ/2 level. DQSs for write operation are referred
to the cross point of the CLK and the CLK#. The other input signals are referred at CLK rising edge.
CS# (input pins)
When CS# is low, commands and data can be input. When CS# is high, all inputs are ignored. However,
internal operations (bank active, burst operations, etc.) are held.
RAS#, CAS#, and WE# (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their
voltage levels. See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising
edge and the CK# falling edge in a bank active command cycle. Column address is loaded at the cross
point of the CK rising edge and the CK# falling edge in a read or a write command cycle (See “Address
Pins Table”). This column address becomes the starting address of a burst operation
Address Pins Table
Page size
Organization
Row address
Column address
2KB
x 16 bits
AX0 to AX12
AY0 to AY9
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is
issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low
when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10
= high when read or write command, auto precharge function is enabled.
BA0 and BA1 (input pins)
BA0 and BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2
and bank 3. (See Bank Select Signal Table)
Bank Select Signal Table
BA0
BA1
Bank 0
Bank 1
L
H
L
L
Bank 2
Bank 3
L
H
H
H
Remark: H: VIH and L:VIL
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
52
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
CKE (input pin)
CKE controls power-down mode, self-refresh function and deep power-down function with other
command inputs. The CKE level must be kept for 2 clocks at least, that is, if CKE changes at the cross
point of the CLK rising edge and the CLK# falling edge with proper setup time tIS, by the next CLK rising
edge CKE level must be kept with proper hold time tIH.
DQ0 to DQ15 (input/Output pins)
Data are input to and output from these pins.
UDQS and LDQS (input and output pins)
DQS provides the read data strobes (as output) and the write data strobes (as input). Each DQS pin
corresponds to eight DQ pins, respectively (See DQS and DM Correspondence Table).
UDM and LDM (input pins)
DM is the reference signals of the data input mask function. DM is sampled at the cross point of DQS
and VDDQ/2. When DM = high, the data input at the same timing are masked while the internal burst
counter will be counting up. Each DM pin corresponds to eight DQ pins, respectively (See DQS and DM
Correspondence Table).
DQS and DM Correspondence Table
Organization
X16 bits
DQS
Data mask
DQs
LDQS
LDM
DQ0 to DQ7
UDQS
UDM
DQ8 to DQ15
VDD, VSS, VDDQ and VSSQ (power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the
output buffers. VDD must be equal to VDDQ.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
53
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
COMMAND OPERATIONS
Command Truth Table
CKE
Name (Function)
Symbol
n-1
n
CS#
RAS#
CAS#
WE#
BA1
BA0
AP
ADDR
Ignore command
DESL
H
H
H
X
X
X
X
X
X
X
No operation
NOP
H
H
L
H
H
H
X
X
X
X
Burst stop command
BST
H
H
L
H
H
L
X
X
X
X
Column address and read
command
READ
H
H
L
H
L
H
V
V
L
V
Read with auto precharge
READA
H
H
L
H
L
H
V
V
H
V
Column address and write
command
WRIT
H
H
L
H
L
L
V
V
L
V
Write with auto precharge
WRITA
H
H
L
H
L
L
V
V
H
V
Row address strobe and bank
active
ACT
H
H
L
L
H
H
V
V
V
V
Precharge selected bank
PRE
H
H
L
L
H
L
V
V
L
X
Precharge all banks
PALL
H
H
L
L
H
L
X
X
H
X
REF
H
H
L
L
L
H
X
X
X
X
SELF
H
L
L
L
L
H
X
X
X
X
MRS
H
H
L
L
L
L
L
L
L
V
EMRS
H
H
L
L
L
L
H
L
L
V
Refresh
Mode register set
Remark: H: VIH, L: VIL, X: Don’t care, and V: Valid address input
Notes:
1. The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When CS# is high at the cross point of the CLK rising edge and the CLK# falling edge, all input signals
are neglected and internal state is held.
No operation [NOP]
As long as this command is input at the cross point of the CLK rising edge and the CLK# falling edge,
address and data input are neglected and internal state is held.
Burst stop command [BST]
This command stops a current burst operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column
address (See “Address Pins Table” in Pin Function) and the bank select address. After the completion
of the read operation, all output buffers become high-Z.
Read with auto precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is
automatically executed.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
54
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column
address (See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is
automatically executed.
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0 and BA1 (See Bank Select Signal Table) and
determines the row address (Address Pins Table in “Pin Function”).
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0 and BA1. (See Bank Select
Signal Table)
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh,
and another is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR Mobile RAM has the two mode registers, the mode register and the extended mode register,
to define how it works. The both mode registers are set through the address pins in the mode register
set cycle. For details, refer to "Mode register and extended mode register set"
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
55
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Function Truth Table
The following tables show the operations that are performed when each command is issued in each
state of the DDR Mobile RAM.
Current state
Precharging
Idle
*1
*2
Refresh (auto*3
refresh)
Activating
Active *5
Read
*6
*4
CS#
RAS#
CAS#
WE#
Address
Command
Operation
H
L
L
L
L
L
L
X
H
H
H
H
L
L
X
H
H
L
L
H
H
X
H
L
H
L
H
L
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
NOP
NOP
ILLEGAL *11
ILLEGAL *11
ILLEGAL *11
ILLEGAL *11
NOP
L
H
L
L
L
L
L
L
L
L
H
L
H
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
L
X
H
H
L
L
H
H
L
L
X
H
H
L
X
X
H
L
H
L
H
L
H
L
X
H
L
X
X
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
MODE
X
X
X
X
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
REF, SELF
MRS
DESL
NOP
BST
ILLEGAL
NOP
NOP
NOP
ILLEGAL *11
ILLEGAL *11
Activating
NOP
Refresh/Self-refresh *12
Mode register set *12
NOP
NOP
ILLEGAL
ILLEGAL
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
X
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
L
H
L
L
L
X
H
H
L
X
H
H
X
X
H
L
X
X
X
X
DESL
NOP
BST
L
H
L
H
BA, CA, A10
READ/READA
L
L
H
L
L
H
L
H
BA, CA, A10
BA, RA
WRIT/WRITA
ACT
L
L
H
L
BA, A10
PRE, PALL
L
L
L
X
X
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
56
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
ILLEGAL
NOP
NOP
ILLEGAL *11
ILLEGAL *11
ILLEGAL *11
ILLEGAL *11
ILLEGAL *11
ILLEGAL
NOP
NOP
NOP
Start read operation
Start write operation
ILLEGAL *11
PRECHARGE
ILLEGAL
NOP
NOP
Burst stop
Interrupting burst read
operation to start new
read
ILLEGAL *13
ILLEGAL *11
Interrupting burst read
operation to precharge
ILLEGAL
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22
EN71SN10F
Current state
CS#
RAS#
CAS#
WE#
Address
Command
Operation
Read with auto*7
precharge
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
L
X
H
L
H
L
H
L
X
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL *11
ILLEGAL *11
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DESL
NOP
BST
L
H
L
H
BA, CA, A10
READ/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE, PALL
NOP
NOP
Burst stop
Interrupting burst write
operation to start read
operation
Interrupting burst write
operation to start new
write operation
ILLEGAL *11
Interrupting write
operation to precharge
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
X
H
L
H
X
X
X
X
BA, CA, A10
DESL
NOP
BST
READ/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
L
L
H
H
H
L
BA, RA
BA, A10
ACT
PRE, PALL
ILLEGAL
NOP
NOP
ILLEGAL
Starting read operation
Starting new write
operation
ILLEGAL *11
ILLEGAL *11
L
H
L
L
L
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
L
L
H
H
X
X
H
L
H
L
H
L
X
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
DESL
NOP
BST
READ/READA
WRIT/WRITA
ACT
PRE, PALL
ILLEGAL
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL *11
ILLEGAL *11
L
L
L
X
X
Write
*8
Write recovering
*9
Write with auto*10
precharge
ILLEGAL
Remark: H: VIH, L: VIL, and X: Don’t care
Notes:
1.
The DDR Mobile RAM is in "Precharging" state for tRP after precharge command is issued.
2.
The DDR Mobile RAM reaches "IDLE" state tRP after precharge command is issued.
3.
The DDR Mobile RAM is in "Refresh" state for tRFC after auto-refresh command is issued.
4.
The DDR Mobile RAM is in "Activating" state for tRCD after ACT command is issued.
5.
The DDR Mobile RAM is in "Active" state after "Activating" is completed.
6.
The DDR Mobile RAM is in "READ" state until burst data have been output and DQ output circuits are turned
off.
7.
The DDR Mobile RAM is in "READ with auto precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8.
The DDR Mobile RAM is in "WRITE" state from WRIT command to the last burst data are input.
9.
The DDR Mobile RAM is in "Write recovering" for tWR after the last data are input.
10. The DDR Mobile RAM is in "Write with auto precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. Not bank-specific; requires that all banks are idle and no bursts are in progress.
13. Before executing a write command to stop the preceding burst read operation, BST command must be issued.
All states and sequences not shown are reserved and/or illegal.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2013/10/22
EN71SN10F
CKE Truth Table
CKE
Current state
Command
n-1
n
CS#
RAS#
CAS#
WE#
Address
Notes
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
X
2
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
X
2
Active/Idle
Power-down entry (PDEN)
H
H
L
L
L
H
H
X
H
X
H
X
X
X
2
Idle Self-refresh
Deep power-down entry
(DPDEN)
Self-refresh exit (SELFX)
H
L
L
L
H
H
L
L
H
H
H
X
H
H
X
L
H
X
X
X
X
Power-down
Power-down exit (PDEX)
L
L
H
H
L
H
H
X
H
X
H
X
X
X
Deep power-down
Power-down exit (DPDEX)
L
H
X
X
X
X
X
Notes:
1. H: VIH. L: VIL. X: Don’t care.
2. All the banks must be in IDLE and no bursts in progress before executing this command.
3. The CKE level must be kept for 1 clock cycle at least.
Auto-refresh command [REF]
This command executes auto-refresh. The bank and the ROW addresses to be refreshed are internally
determined by the internal refresh controller. The output buffer becomes high-Z after auto-refresh start.
Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be
issued tRFC after the last auto-refresh command. The average refresh interval is 7.8us. To allow for
improved efficiency in scheduling, some flexibility in the absolute refresh interval is provided. A
maximum of eight auto-refresh commands can be posted to the DDR Mobile RAM or the maximum
absolute interval between any auto-refresh command and the next auto-refresh command is 8 x tREFI.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held low.
During the self-refresh operation, all ROW addresses are repeated refreshing by the internal refresh
controller. A self-refresh is terminated by a self-refresh exit command.
Power-down mode entry [PDEN]
tPDEN (= 2 clocks) after the cycle when [PDEN] is issued, the DDR Mobile RAM enters into power-down
mode. In power-down mode, power consumption is suppressed by deactivating the input initial circuit.
Power-down mode continues while CKE is held low. No internal refresh operation occurs during the
power-down mode.
Deep power-down mode entry [DPDEN]
After the command execution, deep power-down mode continues while CKE remains low. Before
executing deep power-down, all banks must be precharged or in idle state.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. tSREX after [SELFX], the device will be into idle
state.
Power-down mode exit [PDEX]
The DDR Mobile RAM can exit from power-down mode tPDEX (1 cycle min.) after the cycle when [PDEX]
is issued.
Deep power-down mode exit [DPDEX]
As CKE goes high in the deep power-down mode, the DDR Mobile RAM exits from the deep powerdown mode through deep power-down exiting sequence.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2013/10/22
EN71SN10F
Simplified state diagram
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN71SN10F
Operation of the DDR Mobile RAM
Initialization
The DDR Mobile RAM is initialized in the power-on sequence according to the following.
1.
Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up
simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and
VDDQ are from the same power source. Also assert and hold Clock Enable (CKE) to a LV-CMOS
logic high level.
2.
Once the system has established consistent device power and CKE is driven high, it is safe to
apply stable clock.
3.
There must be at least 200μs of valid clocks before any command may be given to the DRAM.
During this time NOP or deselect (DESL) commands must be issued on the command bus.
4.
Issue a precharge all command.
5.
Provide NOPs or DESL commands for at least tRP time.
6.
Issue an auto-refresh command followed by NOPs or DESL command for at least tRFC time. Issue
the second auto-refresh command followed by NOPs or DESL command for at least tRFC time.
Note as part of the initialization sequence there must be two auto-refresh commands issued. The
typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.
7.
Using the MRS command, load the base mode register. Set the desired operating modes.
8.
Provide NOPs or DESL commands for at least tMRD time.
9.
Using the MRS command, program the extended mode register for the desired operating modes.
10. Provide NOP or DESL commands for at least tMRD time.
11. The DRAM has been properly initialized and is ready for any valid command.
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the
operating mode. Parameters are set to both through the A0 to the A12 and BA0 and BA1 pins by the
mode register set command [MRS] or the extended mode register set command [EMRS]. The mode
register and the extended mode register are set by inputting signal via the A0 to the A12 and BA0 and
BA1 pins during mode register set cycles. BA0 and BA1 determine which one of the mode register or
the extended mode register are set. Prior to a read or a write operation, the mode register must be set.
Mode register
The mode register has four fields;
Reserved
CAS# latency
Wrap type
Burst length
: A12 through A7
: A6 through A4
: A3
: A2 through A0
Following mode register programming, no command can be issued before at least 2 clocks have
elapsed.
CAS# Latency
CAS# latency must be set to 3
Burst length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read
burst is completed, the output bus will become high-Z. The burst length is programmable as 2, 4, 8 and
16.
Wrap type (Burst sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable
as either ”Sequential” or “Interleave”. “Burst Operation” shows the addressing sequence for each burst
length for each wrap type.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN71SN10F
Extended mode register
The extended mode register has three fields;
Reserved
: A12 through A7, A4, A3
Driver Strength
: A6 through A5
Partial Array Self-Refresh : A2 through A0
Following extended mode register programming, no command can be issued before at least 2 clocks
have elapsed.
Driver strength
By setting specific parameter on A6 and A5, driving capability of data output drivers is selected.
Auto Temperature Compensated Self-Refresh (ATCSR)
The DDR Mobile RAM automatically changes the self-refresh cycle by on die temperature sensor. No
extended mode register program is required. Manual TCSR (Temperature Compensated Self-Refresh)
is not implemented.
Partial Array Self-Refresh
Memory array size to be refreshed during self-refresh operation is programmable in order to reduce
power. Data outside the defined area will not be retained during self-refresh.
Deep Power-Down Exit Sequence
In order to exit from the deep power-down mode and enter into the idle mode, the following sequence is
needed, which is similar to the power-on sequence.
(1) A 200μs or longer pause must precede any command other than ignore command (DESL).
(2) After the pause, all banks must be precharged using the precharge command (the precharge all
banks command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto-refresh must be
performed.
(4) Both the mode register and the extended mode register must be programmed. After the mode
register set cycle or the extended mode register set cycle, tMRD (2 clocks minimum) pause must be
satisfied.
Remarks:
1.
The sequence of Auto-refresh, mode register programming and extended mode register
programming above may be transposed.
2.
CKE must be held high.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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Rev. B, Issue Date: 2013/10/22
EN71SN10F
Power-Down Mode and CKE Control
DDR Mobile RAM will be into power-down mode at the second CK rising edge after CKE to be low level
with NOP or DESL command at first CK rising edge after CKE signal to be low.
Notes:
1. Valid*1 can be either Activate command or Precharge command, When Valid*1 is Activate command,
power-down mode will be active power-down mode, while it will be precharge power down mode, if
Valid*1 will be Precharge command.
2. Valid*2 can be any command as long as all of specified AC parameters are satisfied.
Power-Down Entry and Exit
However, if the CKE has one clock cycle high and on clock cycle low just as below, even DDR Mobile
RAM will not enter power-down.
Note: Assume PRE and ACT command is closing and activating same bank.
CKE Control
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN71SN10F
Mode Register Definition
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
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EN71SN10F
Burst Operation
The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst Length
2
4
8
16
Starting Column Address
(A3, A2,A1,A0)
Burst type = Sequential A3 = 0
Burst type = Interleaved A3 = 1
0000
0,1
0,1
0001
1,0
1,0
0000
0,1,2,3
0,1,2,3
0001
1,2,3,0
1,0,3,2
0010
2,3,0,1
2,3,0,1
0011
3,0,1,2
3,2,1,0
0000
0,1,2,3,4,5,6,7
0,1,2,3,4,5,6,7
0001
1,2,3,4,5,6,7,0
1,0,3,2,5,4,7,6
0010
2,3,4,5,6,7,0,1
2,3,0,1,6,7,4,5
0011
3,4,5,6,7,0,1,2
3,2,1,0,7,6,5,4
0100
4,5,6,7,0,1,2,3
4,5,6,7,0,1,2,3
0101
5,6,7,0,1,2,3,4
5,4,7,6,1,0,3,2
0110
6,7,0,1,2,3,4,5
6,7,4,5,2,3,0,1
0111
7,0,1,2,3,4,5,6
7,6,5,4,3,2,1,0
0000
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
0001
1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,0
1,0,3,2,5,4,7,6,9,8,B,A,D,C,F,E
0010
2,3,4,5,6,7,8,9,A,B,C,D,E,F,0,1
2,3,0,1,6,7,4,5,A,B,8,9,E,F,C,D
0011
3,4,5,6,7,8,9,A,B,C,D,E,F,0,1,2
3,2,1,0,7,6,5,4,B,A,9,8,F,E,D,C
0100
4,5,6,7,8,9,A,B,C,D,E,F,0,1,2,3
4,5,6,7,0,1,2,3,C,D,E,F,8,9,A,B
0101
5,6,7,8,9,A,B,C,D,E,F,0,1,2,3,4
5,4,7,6,1,0,3,2,D,C,F,E,9,8,B,A
0110
6,7,8,9,A,B,C,D,E,F,0,1,2,3,4,5
6,7,4,5,2,3,0,1,E,F,C,D,A,B,8,9
0111
7,8,9,A,B,C,D,E,F,0,1,2,3,4,5,6
7,6,5,4,3,2,1,0,F,E,D,C,B,A,9,8
1000
8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7
8,9,A,B,C,D,E,F,0,1,2,3,4,5,6,7
1001
9,A,B,C,D,E,F,0,1,2,3,4,5,6,7,8
9,8,B,A,D,C,F,E,1,0,3,2,5,4,7,6
1010
A,B,C,D,E,F,0,1,2,3,4,5,6,7,8,9
A,B,8,9,E,F,C,D,2,3,0,1,6,7,4,5
1011
B,C,D,E,F,0,1,2,3,4,5,6,7,8,9,A
B,A,9,8,F,E,D,C,3,2,1,0,7,6,5,4
1100
C,D,E,F,0,1,2,3,4,5,6,7,8,9,A,B
C,D,E,F,8,9,A,B,4,5,6,7,0,1,2,3
1101
D,E,F,0,1,2,3,4,5,6,7,8,9,A,B,C
D,C,F,E,,9,8,B,A,5,4,7,6,1,0,3,2
1110
E,F,0,1,2,3,4,5,6,7,8,9,A,B,C,D
E,F,C,D,A,B,8,9,6,7,4,5,2,3,0,1
1111
F,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E
F,E,D,C,B,A,9,8,7,6,5,4,3,2,1,0
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EN71SN10F
Read/Write Operations
Bank Active
A read or a write operation begins with the bank active command [ACT]. The bank active command
determines a bank address and a row address. For the bank and the row, a read or a write command
can be issued tRCD after the ACT is issued.
Read operation
The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred
when a read command is issued. The burst length (BL) determines the length of a sequential output
data by the read command that can be set to 2, 4, 8 or 16. The starting address of the burst read is
defined by the column address, the bank select address (See “Pin Function”) in the cycle when the read
command is issued. The data output timing is characterized by CL and tAC. The read burst start (CL-1) ×
tCK + tAC (ns) after the clock rising edge where the read command is latched. The DDR Mobile RAM
outputs the data strobe through DQS pins simultaneously with data. tRPRE prior to the first rising edge of
the data strobe, the DQS pins are driven low from high-Z state. This low period of DQS is referred as
read preamble. The burst data are output coincidentally at both the rising and falling edge of the data
strobe. The DQ pins become high-Z in the next cycle after the burst read operation completed. tRPST
from the last falling edge of the data strobe, the DQS pins become high-Z. This low period of DQS is
referred as read postamble.
Read Operation (Burst Length)
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or modifications due to changes in technical specifications.
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EN71SN10F
Read Operation (CAS# Latency)
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EN71SN10F
Write Operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command
is issued. The burst length (BL) determines the length of a sequential data input by the write command
that can be set to 2, 4, 8 or 16. The latency from write command to data input is fixed to 1. The starting
address of the burst write is defined by the column address, the bank select address (See “Pin
Function”) in the cycle when the write command is issued. DQS should be input as the strobe for the
input-data and DM as well during burst operation. tWPRE prior to the first rising edge of DQS, DQS must
be set to low. tWPST after the last falling edge of DQS, the DQS pins can be changed to high-Z. The
leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write
postamble.
Write Operation
This Data Sheet may be revised by subsequent versions
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EN71SN10F
Burst Stop
Burst stop command during burst operation
The burst stop (BST) command stops the burst read and sets all output buffers to high-Z. tBSTZ (= CL)
cycles after a BST command issued, all DQ and DQS pins become high-Z. The BST command is also
supported for the burst write operation. No data will be written in subsequent cycles. Note that bank
address is not referred when this command is executed.
Burst Stop during a Read Operation
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EN71SN10F
Auto Precharge
Read with auto precharge
The precharge is automatically performed after completing a read operation. The precharge starts BL/2
(= tRPD) clocks after READA command input. tRAS lock out mechanism for READA allows a read
command with auto precharge to be issued to a bank that has been activated (opened) but has not yet
satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next
cycle after the last data output. Read with auto precharge command does not limit row commands
execution for other bank.
Read with auto precharge
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Write with auto precharge
The precharge is automatically performed after completing a burst write operation. The precharge
operation is started Write latency (WL) + BL/2 + tWR (= tWPD) clocks after WRITA command issued.
A column command to the other banks can be issued the next cycle after the internal precharge.
Burst Write (BL=4)
The Concurrent Auto Precharge
The DDR Mobile RAM supports the concurrent auto precharge feature, a read with auto precharge or a
write with auto precharge, can be followed by any command to the other banks, as long as that
command does not interrupt the read or write data transfer, and all other related limitations apply (e.g.
contention between READ data and WRITE data must be avoided.) The minimum delay from a read or
write command with auto precharge, to a command to a different bank, is summarized below.
From
command
Read w/ AP
Write w/ AP
To command (different bank, noninterrupting command)
Minimum delay
(Concurrent AP supported)
Units
Read or Read w/ AP
BL/2
tCK
Write or Write w/ AP
CL (round up) + (BL/2)
tCK
Precharge or Activate
1
tCK
Read or Read w/ AP
1 + (BL/2) + tWTR
tCK
Write or Write w/ AP
BL/2
tCK
Precharge or Activate
1
tCK
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Command Intervals
A Read command to the consecutive Read command interval
Destination row of the consecutive read command
1
2
3
Bank address
Row Address
Status
Operation
Same
Same
ACTIVE
The consecutive read can be performed after an interval of no less than
1 cycle to interrupt the preceding read operation.
-
Precharge the bank to interrupt the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT
command, the consecutive read command can be issued. See ‘A read
command to the consecutive precharge interval’ section.
ACTIVE
The consecutive read can be performed after an interval of no less than
1 cycle to interrupt the preceding read operation.
IDLE
Precharge the bank without interrupting the preceding read operation.
tRP after the precharge command, issue the ACT command. tRCD after
the ACT command, the consecutive read command can be issued.
Same
Different
Different
Any
Read to Read command interval (same ROW address in the same bank)
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Read to Read command interval (different bank)
A Write command to the consecutive Write command interval
Destination row of the consecutive write command
1
2
3
Bank address
Row Address
Status
Operation
Same
Same
ACTIVE
The consecutive write can be performed after an interval of no less than
1 cycle to interrupt the preceding write operation.
-
Precharge the bank to interrupt the preceding write operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT
command, the consecutive write command can be issued. See ‘A write
command to the consecutive precharge interval’ section.
ACTIVE
The consecutive write can be performed after an interval of no less than
1 cycle to interrupt the preceding write operation.
IDLE
Precharge the bank without interrupting the preceding write operation.
tRP after the precharge command, issue the ACT command. tRCD after
the ACT command, the consecutive write command can be issued.
Same
Different
Different
Any
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Write to Write command interval (same ROW address in the same bank)
Write to Write command interval (different bank)
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A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive writ command
1
2
3
Bank address
Row Address
Status
Operation
Same
Same
ACTIVE
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
-
Precharge the bank to interrupt the preceding read operation. tRP after
the precharge command, issue the ACT command. tRCD after the ACT
command, the consecutive write command can be issued. See ‘A read
command to the consecutive precharge interval’ section.
ACTIVE
Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the
consecutive write command can be issued.
IDLE
Precharge the bank independently of the preceding read operation. tRP
after the precharge command, issue the ACT command. tRCD after the
ACT command, the consecutive write command can be issued.
Same
Different
Different
Any
Read to Write command interval
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A Write command to the consecutive Read command interval: to complete the burst operation
Destination row of the consecutive read command
1
2
3
Bank address
Row Address
Status
Operation
Same
Same
ACTIVE
To complete the burst operation, the consecutive read command
should be performed tWRD after the write command.
-
Precharge the bank tWPD after the preceding write command. tRP after
the precharge command, issue the ACT command. tRCD after the ACT
command, the consecutive read command can be issued. See ‘A read
command to the consecutive precharge interval’ section.
ACTIVE
To complete a burst operation, the consecutive read command should
be performed tWRD after the write command.
IDLE
Precharge the bank independently of the preceding write operation. tRP
after the precharge command, issue the ACT command. tRCD after the
ACT command, the consecutive read command can be issued.
Same
Different
Different
Any
Write to Read command interval
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A Write command to the consecutive Read command interval: to interrupt the write operation
Destination row of the consecutive read command
Bank address
Row Address
Status
Operation
DM must be input 1 cycle prior to the read command input to prevent
from being written invalid data. In case, the read command is input in
the next cycle of the write command, DM is not necessary.
1
Same
Same
ACTIVE
2
Same
Different
-
-*1
ACTIVE
3
Different
Any
IDLE
DM must be input 1 cycle prior to the read command input to prevent
from being written invalid data. In case, the read command is input in
the next cycle of the write command, DM is not necessary.
*1
Note:
1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in
this case.
Write to Read Command Interval (same bank, same ROW address)
[Write to Read delay = 1 clock cycle]
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[Write to Read delay = 2 clock cycle]
Note: tWTR is referenced from the first positive CLK edge after the last desired data in pair tWTR.
[Write to Read delay = 4 clock cycle]
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A Write command to the Bust stop command interval: To interrupt the write operation
WRITE to BST Command Interval (Same bank, same ROW address)
[Write to BST delay = 1 clock cycle]
[Write to BST delay = 2 clock cycle]
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[Write to BST delay = 3 clock cycle]
A Read command to the consecutive Precharge command interval
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
Operation
1
Same
The PRE and PALL command can interrupt a read operation. To complete a burst read
operation, tRPD is required between the read and the precharge command. Please refer to the
following timing chart.
2
Different
The PRE command does not interrupt a read command. No interval timing is required
between the read and the precharge command.
READ to PRECHARGE Command Interval (same bank): To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command
must be issued tRPD (= BL/ 2 cycles) after the read command is issued.
READ to PRECHARGE Command Interval (same bank): To output all data (CL=3, BL=4)
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READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become
high-Z tHZP (= CL) after the precharge command.
READ to PRECHARGE Command Interval (same bank): To stop output data (CL=3, BL=4, 8)
A Write command to the consecutive Precharge command interval (same bank)
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
1
Same
2
Different
Operation
The PRE and PALL command can interrupt a write operation. To complete a burst write
operation, tWPD is required between the write and the precharge command. Please refer to the
following timing chart.
The PRE command does not interrupt a write command. No interval timing is required
between the write and the precharge command.
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Write to Precharge command interval (same bank)
The minimum interval tWPD is necessary between the write command and the precharge command.
Write to Precharge command interval (same bank) (BL=4)
Write to Precharge command interval (same bank) (BL=4, DM to mask data)
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Bank active command interval
Destination row of the consecutive ACT command
1
2
Bank address
Row Address
Status
Operation
Same
Any
ACTIVE
Two successive ACT commands can be issued at tRC interval. In
between two successive ACT operations, precharge command should
be executed.
ACTIVE
Precharge the bank. tRP after the precharge command, the consecutive
ACT command can be issued.
Different
Any
IDLE
tRRD after an ACT command, the next ACT command can be issued.
Bank Active to Bank Active
Mode register set to Bank-active command interval
The interval between setting the mode register and executing a bank-active command must be no less
than tMRD.
Mode Register Set to Bank Active
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DM Control
DM can mask input data. By setting DM to low, data can be written. UDM and LDM can mask the upper
and lower byte of input data, respectively. When DM is set to high, the corresponding data is not written,
and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
DM Control
Timing Waveforms
Command and Addresses Input Timing Definition
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Read Timing Definition (1)
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Read Timing Definition (2)
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Write Timing Definition
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Initialization Sequence
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Read Cycle
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Write Cycle
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Mode Register Set Cycle
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Read/Write Cycle
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Auto-Refresh Cycle
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Self-Refresh Cycle
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Power-Down Entry and Exit
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Deep Power-Down Entry
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Deep Power-Down Exit
Note:
The sequence of auto-refresh, mode register programming and extended mode register programming
above may be transposed.
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Revisions List
Revision No
Description
Date
Preliminary 0.0 Initial Release
A
Update datasheet version from Preliminary 0.0 to A.
B
Correct the Ball Configuration’s typo (M2 => I/O1) on page 3.
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97
2012/09/21
2012/12/07
2013/10/22
©2013 Eon Silicon Solution, Inc., www.eonssi.com
Rev. B, Issue Date: 2013/10/22