EN71SN2BGD11 EN71SN2BGD11 1.8V NAND Flash + 1.8V Mobile DDR SDRAM Multi-Chip Package Features • Multi-Chip Package - NAND Flash Density: 2-Gbits - Mobile DDR SDRAM Density: 1-Gbits • Device Packaging - 137 balls BGA Area: 10.5x13 mm; Height: 1.2 mm - 130 balls BGA Area: 8x9 mm; Height: 1.0 mm • Operating Voltage - NAND : 1.7V to 1.95V - Mobile DDR SDRAM : 1.7V to 1.95V • Operating Temperature :-25 °C to +85 °C NAND FLASH Mobile DDR SDRAM • Voltage Supply: 1.7V ~ 1.95V • Organization - Memory Cell Array : (256M + 8M) x 8bit for 2Gb - Multiplexed address/ data - Data Register : (2K + 64) x 8bit • Automatic Program and Erase - Page Program : (2K + 64) bytes - Block Erase : (128K + 4K) bytes • Page Read Operation - Page Size : (2K + 64) bytes - Random Read : 25µs (Max.) - Serial Access : 45ns (Min.) • • • • • • • • Density: 1G bits Organization: 8M words x 32 bits x 4 banks Power supply: VDD/VDDQ= 1.70~1.95V Four internal banks for concurrent operation 1.8V LVCMOS-compatible inputs Programmable Burst Lengths : 2, 4, 8 or 16 Burst Type : Sequential and Interleave Auto Refresh and Self Refresh Modes • Configurable Drive Strength (DS) • Optional Partial Array Self Refresh (PASR) • On-chip temperature sensor to control self refresh rate Temperature Compensated Self Refresh (TCSR) • Deep Power Down Mode (DPD) • Double-data rate architecture; two data transfer per clock cycle • Bidirectional, data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS edge-aligned with data for READ; centeraligned with data for WRITE • Differential clock inputs (CLK and CLK# ) • Memory Cell: 1bit/Memory Cell • Fast Write Cycle Time - Page Program Time : 250µs (Typ.) - Block Erase Time : 2ms (Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - ECC Requirement: 4 bit/512 bytes - Endurance: 100K Program/Erase Cycles - Data Retention: 10 Years • Command Register Operation • Automatic Page 0 Read at Power-Up Option - Boot from NAND support - Automatic Memory Download • NOP: 4 cycles • Cache Program/Read Operation • Copy-Back Operation • • • • • • • Commands entered on each positive CLK edge Data mask (DM) for write data – one mask per byte Bidirectional data strobe per byte of data (DQS) Clock Stop capability Concurrent Auto Precharge option is supported Status Read Register (SRR) 64ms refresh • Two-plane Operation • EDO mode • Bad-Block-Protect This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 1 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Ordering Information NAND Flash Mobile DDR SDRAM Product ID Configuration EN71SN2BGD1145CGWP EN71SN2BGD1145EBWP 2Gb (256M X 8 bits) 2Gb (256M X 8 bits) Speed 45ns 45ns Configuration Package Operation Temperature Range 137 ball BGA Wireless 130 ball BGA Wireless Speed 1Gb (4 Banks X 200MHz 8M X 32 bits) 1Gb (4 Banks X 200MHz 8M X 32 bits) MCP Block Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 2 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Ball Configuration (TOP VIEW) (BGA 137 Balls, 10.5mmx13mmx1.2mm Body, 0.8mm Ball Pitch) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 3 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 (TOP VIEW) (BGA 130 Balls, 8mmx9mmx1.0mm Body, 0.65mm Ball Pitch) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 4 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Table 1. Ball Description Pin Name Type NAND Flash VCC Supply VSS Supply Function Supply Voltage Ground I/O0-I/O7 Input/output The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. ALE Input The ALE input controls the activating path for addresses sent to the internal address registers. Addresses are latched into the address register through the I/O ports on the rising edge of WE# with ALE high. CLE Input The CLE input controls the activating path for commands sent to the internal command registers. Commands are latched into the command register through the I/O ports on the rising edge of the WE# signal with CLE high. CE# Input The CE# input is the device selection control. When the device is in the Busy state, CE# high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE# control during read operation, refer to ’Page read’ section of Device operation. RE# Input The RE# input is the serial data-out control, and when it is active low, it drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE# which also increments the internal column address counter by one. WE# Input The WE# input controls writes to the I/O ports. Commands, address and data are latched on the rising edge of the WE# pulse. WP# Input The WP# pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP# pin is active low. Output The R/B# output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in progress and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. R / B# Mobile DDR SDRAM VDD Supply VSSD Supply VDDQ Supply VSSQ Supply CLK, CLK# Input CKE Input CS# Input RAS# Input CAS# Input WE# Input A0-A12 Input BA0, BA1 Input Input / DQ0- DQ31 Output Input / DQS0-DQS3 Output DM0-DM3 Input NC / DNU - Power Supply Ground DQ’s Power Supply: Isolated on the die for improved noise immunity. Ground CLK and CLK# are differential system clock inputs. Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Input Bank Address Input Data Input/Output pins Data Strobe Input Data Mask No Connection / Do Not Use This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 PACKAGE DIMENSION 137-BALL BGA ( 10.5x13 mm ) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 6 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 130-BALL BGA ( 8x9 mm ) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 7 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 NAND Flash Memory Operations This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 8 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Block Diagram Vcc Vss X-Buffers Latches & Decoders A12 – A28 2,048M + 64M Bit for 1Gb NAND Flash Array Y-Buffers Latches & Decoders A0 – A11 Data Register & S/A Y - Gating Command Command Register Vcc I/O Buffers & Latches Vss Control Logic & High Voltage Generator CE# RE# WE# Global Buffers Output Driver I/O0 I/O7 CLE ALE WP# Array Organization This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 9 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Array Address I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Address 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 Column Address 2nd Cycle A8 A9 A10 A11 L* L* L* L* Column Address 3rd Cycle A12 A13 A14 A15 A16 A17 A18 A19 Row Address 4th Cycle A20 A21 A22 A23 A24 A25 A26 A27 Row Address 5th Cycle Note: A28 L* L* L* L* L* L* L* Row Address 1. Column Address : Starting Address of the Register. 2. * L must be set to “Low”. 3. * The device ignores any additional input of address cycles than required. 4. A18 is for Plane Addressing setting. Product Introduction The NAND Flash is a 2,112Mbit memory organized as 64K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2,048 separately erasable 128K-byte blocks. It indicates that the bit-by-bit erase operation is prohibited on the NAND Flash. The NAND Flash has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE# to low while CE# is low. Those are latched on the rising edge of WE#. Command Latch Enable (CLE) and Address Latch Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. In addition to the enhanced architecture and interface, the NAND Flash incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 10 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Command Set Function 1st Cycle 2nd Cycle Acceptable Command during Busy Read 00h 30h Read for Copy Back 00h 35h Read ID 90h Reset FFh O Page Program 80h 10h Copy-Back Program 85h 10h Block Erase 60h D0h Random Data Input (1) 85h Random Data Output (1) 05h E0h Read Status 70h O Read Status 2 F1h O Two-Plane Read (3) 60h-60h 30h Two-Plane Read for Copy-Back 60h-60h 35h Two-Plane Random Data Output (1) (3) 00h-05h E0h Two-Plane Page Program (2) 80h-11h 81h-10h (2) Two-Plane Copy-Back Program 85h-11h 81h-10h Two-Plane Block Erase 60h-60h D0h Cache Program 80h 15h Cache Read 31h Read Start for Last Page Cache Read 3Fh Two-Plane Cache Read (3) 60h-60h 33h Two-Plane Cache Program (2) 80h-11h 81h-15h Note: 1. Random Data Input / Output can be executed in a page. 2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh. 3. Two-Plane Random Data Output must be used after Two-Plane Read operation or Two-Plane Cache Read operation. Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Temperature Under Bias Storage Temperature Short Circuit Current Symbol VCC VIN VI/O TBIAS TSTG IOS Rating -0.6 to +2.45 -0.6 to +2.45 -0.6 to VCC + 0.3 (< 2.45) -40 to +125 -65 to +150 5 Unit V ℃ ℃ mA Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, TA = – 25°C to 85°C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min. 1.7 0 Typ. 1.8 0 Max. 1.95 0 Unit V V DC AND OPERATION CHARACTERISTICS (Recommended operating conditions otherwise noted) Parameter Page Read with Serial Access Operating Program Current Erase Stand-by Current (TTL) Stand-by Current (CMOS) Symbol Test Conditions Min. Typ. Max. ICC1 tRC=45ns, CE# =VIL, IOUT=0mA - 15 20 ICC2 ICC3 ISB1 ISB2 CE# =VIH, WP# =0V/VCC CE# = VCC -0.2, WP# =0V/ VCC - 15 15 10 Input Leakage Current ILI VIN=0 to VCC (max) - - 20 20 1 50 ±10 Output Leakage Current ILO VOUT=0 to VCC (max) - - ±10 Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current (R/B#) VIH mA uA uA uA - 0.8 x VCC - VCC +0.3 V (1) IOH=-100uA IOL=+100uA VOL=0.2V -0.3 VCC -0.1 3 4 0.2 x VCC 0.1 - V V V mA VIL VOH VOL IOL (R /B#) VALID BLOCK Min. 2,008 mA (1) Note: 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC+0.4V for durations of 20ns or less. 2. Typical value are measured at VCC =1.8V, TA = 25℃. And not 100% tested. Symbol NVB Unit Typ. - Max. 2,048 Unit Blocks Note: 1. The device may include initial invalid blocks when first shipped. The number of valid blocks is presented as first shipped. Invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do not erase or program factorymarked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment. 3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 12 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 AC TEST CONDITION (TA = – 25°C to 85°C, VCC=1.7V~1.95V, unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Condition 0V to VCC 5 ns VCC /2 1 TTL Gate and CL=30pF CAPACITANCE (TA = 25°C, VCC=1.8V, f =1.0MHz) Item Symbol Test Condition Input / Output Capacitance CI/O VIL = 0V Input Capacitance CIN VIN = 0V Note: Capacitance is periodically sampled and not 100% tested. Min. - Max. 10 10 Unit pF pF MODE SELECTION CLE ALE CE# H L L WE# RE# WP# L H X H L H X H L L H H L H L H H L L L H H Data Input L L L X Data Output H X X X X H X X X X X X H X X X X X H (1) X X X X X L X X H X X 0V/VCC(2) Note: 1. X can be VIL or VIH. 2. WP# should be biased to CMOS high or CMOS low for standby. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 13 Mode Read Mode Write Mode Command Input Address Input (5 clock) Command Input Address Input (5 clock) During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect Stand-by ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Program / Erase Characteristics Parameter Symbol Min. Typ. Max. Unit Average Program Time tPROG 250 700 us Dummy Busy Time for Cache tCBSY 3 700 us Program Number of Partial Program Cycles NOP 4 Cycle in the Same Page Block Erase Time tBERS 2 10 ms Dummy Busy Timer for Two-Plane 0.5 1 us tDBSY Page Program Note: 1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V VCC and 25°C temperature. 2. tPROG is the average program time of all pages. Users should be noted that the program time variation from page to page is possible. 3. Max. time of tCBSY depends on timing between internal program completion and data in. AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min. Max. Unit (1) CLE Setup Time tCLS 25 ns CLE Hold Time tCLH 10 ns CE# Setup Time tCS(1) 35 ns CE# Hold Time tCH 10 ns WE# Pulse Width tWP 25 ns ALE Setup Time tALS(1) 25 ns ALE Hold Time tALH 10 ns Data Setup Time tDS(1) 20 ns Data Hold Time tDH 10 ns Write Cycle Time tWC 45 ns WE# High Hold Time tWH 15 ns ALE to Data Loading Time tADL(2) 100 (2) ns Note: 1. The transition of the corresponding control pins must occur only once while WE# is held low. 2. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 14 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE# Delay CLE to RE# Delay Ready to RE# Low RE# Pulse Width WE# High to Busy WP# Low to WE# Low (disable mode) WP# High to WE# Low (enable mode) Read Cycle Time RE# Access Time CE# Access Time RE# High to Output Hi-Z CE# High to Output Hi-Z CE# High to ALE or CLE Don’t Care RE# High to Output Hold RE# Low to Output Hold CE# High to Output Hold RE# High Hold Time Output Hi-Z to RE# Low RE# High to WE# Low WE# High to RE# Low Read Device Resetting Program Time during ... Erase Ready Cache Busy in Read Cache (following 31h and 3Fh) Symbol Min. Max. Unit tR tAR tCLR tRR tRP tWB 10 10 20 25 - 25 100 us ns ns ns ns ns tWW 100 - ns tRC tREA tCEA tRHZ tCHZ tCSD tRHOH tRLOH tCOH tREH tIR tRHW tWHR 45 0 15 5 15 15 0 100 60 - 30 45 100 30 5 10 500 5(1) ns ns ns ns ns ns ns ns ns ns ns ns ns us us us us - 30 us tRST tDCBSYR Note: 1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 15 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 NAND Flash Technical Notes Mask Out Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Eon. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 4 bit/512 bytes ECC. Identifying Initial Invalid Block(s) and Block Replacement Management Unpredictable behavior may result from programming or erasing the defective blocks. The under figure illustrates an algorithm for searching factory-mapped defects, and the algorithm needs to be executed prior to any erase or program operations. A host controller has to scan blocks from block 0 to the last block using page read command and check the data at the column address of 2,048. If the read data is not FFh, the block is interpreted as an invalid block. Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop with Flash memory usage. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 16 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 17 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Error in Write or Read Operation Within its lifetime, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks. Failure Write Read Detection and Countermeasure sequence Read Status after Erase → Block Replacement Erase Failure Read Status after Program → Block Replacement Program Failure Up to eight Bits Failure Verify ECC → ECC Correction Note: 1. Error Correcting Code --> RS Code or BCH Code etc. 2. Example: 4bit correction / 512 Byte This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 18 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Program Flow Chart This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 19 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Erase Flow Chart Read Flow Chart This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 20 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Block Replacement This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 21 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page of the block to MSB (Most Significant Bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 22 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 System Interface Using CE# don’t-care For an easier system interface, CE# may be inactive during the data-loading or serial access as shown below. The internal 2,112 byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications that use slow cycle time on the order of u-seconds, de-activating CE# during the data-loading and serial access would provide significant savings in power consumption. Program / Read Operation with “CE# not-care” Address Information DATA Data In / Out 2,112 bytes I/O I/Ox I/O0~ I/O7 Col. Add1 A0 ~ A7 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Col. Add2 A8 ~ A11 23 ADDRESS Row Add1 A12 ~ A19 Row Add2 A20 ~ A27 Row Add3 A28 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Command Latch Cycle Address Latch Cycle This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 24 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Input Data Latch Cycle Serial Access Cycle after Read (CLE = L, WE# = H, ALE = L) Note: 1. Dout transition is measured at ±200mV from steady state voltage at I/O with load. 2. tRHOH starts to be valid when frequency is lower than 20MHz. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 25 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Serial Access Cycle after Read (EDO Type CLE = L, WE# = H, ALE = L) Note: 1. Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRLOH is valid when frequency is higher than 20MHz. tRHOH starts to be valid when frequency is lower than 20MHz. Status Read Cycle This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 26 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Read Operation Read Operation (Intercepted by CE#) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 27 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Random Data Output In a Page Page Program Operation Note: tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data cycle. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 28 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Page Program Operation with Random Data Input Note: tADL is the time from WE# rising edge of final address cycle to the WE# rising edge of first data cycle. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 29 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Copy-Back Program Operation with Random Data Input Cache Program Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 30 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Cache Read Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 31 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Block Erase Operation Read ID Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 32 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-plane Page Read Operation with Two-plane Random Data Out This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 33 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-plane Cache Read Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 34 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-plane Page Program Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 35 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-plane Cache Program Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 36 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-plane Block Erase Operation ID Definition Table ID Access command = 90h 1st Cycle (Maker Code) C8h 2nd Cycle (Device Code) AAh 3rd Cycle 4th Cycle 5th Cycle 90h 15h 44h Description st 1 Byte 2nd Byte 3rd Byte 4th Byte 5th Byte Maker Code Device Code Internal Chip Number, Cell Type, etc. Page Size, Block Size, etc. Plane Number, Plane Size, ECC Level 3rd ID Data Internal Chip Number Cell Type Number of Simultaneously Programmed Page Interleave Program Between multiple chips Cache Program Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support I/O7 I/O6 I/O4 0 0 1 1 I/O3 I/O2 0 0 1 1 0 1 0 1 I/O1 0 0 1 1 0 1 0 1 0 Support Not Support Support I/O5 1 0 1 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 37 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 I/O0 0 1 0 1 EN71SN2BGD11 4th ID Data Page Size (w/o redundant area) Redundant Area Size (byte/512byte) Block Size (w/o redundant area) Organization Serial Access Minimum Description 1KB 2KB 4KB 8KB 8 16 64KB 128KB 256KB 512KB x8 x16 45ns Reserved Reserved Reserved I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 0 0 1 1 I/O0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 5th ID Data Description Plane Number Plane Size (w/o redundant area) Reserved 1 2 4 8 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb Reserved I/O7 I/O6 I/O5 I/O4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 38 I/O3 0 0 1 1 I/O2 0 1 0 1 I/O1 I/O0 0 0 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 DEVICE OPERATION Page Read Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h command, five-cycle address, and 30h command. After initial power up, the 00h command can be skipped because it has been latched in the command register. The 2,112Byte of data on a page are transferred to cache registers via data registers within 25us (tR). Host controller can detect the completion of this data transfer by checking the R/B# output. Once data in the selected page have been loaded into cache registers, each Byte can be read out in 45ns cycle time by continuously pulsing RE#. The repetitive high-to-low transitions of RE# clock signal make the device output data starting from the designated column address to the last column address. The device can output data at a random column address instead of sequential column address by using the Random Data Output command. Random Data Output command can be executed multiple times in a page. After power up, device is in read mode so 00h command cycle is not necessary to start a read operation. A page read sequence is illustrated in under figure, where column address, page address are placed in between commands 00h and 30h. After tR read time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after 30h. Host controller can toggle RE# to access data starting with the designated column address and their successive bytes. Read Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 39 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Random Data Output In a Page This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 40 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Page Program The device is programmed based on the unit of a page, and consecutive partial page programming on one page without intervening erase operation is strictly prohibited. Addressing of page program operations within a block should be in sequential order. A complete page program cycle consists of a serial data input cycle in which up to 2,112 byte of data can be loaded into data register via cache register, followed by a programming period during which the loaded data are programmed into the designated memory cells. The serial data input cycle begins with the Serial Data Input command (80h), followed by a five-cycle address input and then serial data loading. The bytes not to be programmed on the page do not need to be loaded. The column address for the next data can be changed to the address follows Random Data Input command (85h). Random Data Input command may be repeated multiple times in a page. The Page Program Confirm command (10h) starts the programming process. Writing 10h alone without entering data will not initiate the programming process. The internal write engine automatically executes the corresponding algorithm and controls timing for programming and verification, thereby freeing the host controller for other tasks. Once the program process starts, the host controller can detect the completion of a program cycle by monitoring the R/B# output or reading the Status bit (I/O6) using the Read Status command. Only Read Status and Reset commands are valid during programming. When the Page Program operation is completed, the host controller can check the Status bit (I/O0) to see if the Page Program operation is successfully done. The command register remains the Read Status mode unless another valid command is written to it. A page program sequence is illustrated in under figure, where column address, page address, and data input are placed in between 80h and 10h. After tPROG program time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after 10h. Program & Read Status Operation Random Data Input In a page This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 41 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Cache Program Cache Program is an extension of Page Program, which is executed with 2,112 byte (x8) data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell. After writing the first set of data up to 2,112 bytes (x8) into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit (I/O5) for internal Ready/Busy may be polled to identity the completion of internal programming. If the system monitors the progress of programming only with R/B#, the last page of the target programming sequence must be programmed with actual Page Program command (10h). Cache Program (available only within a block) Note: 1. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula. 2. tPROG = Program time for the last page + Program time for the (last-1)th page – (Program command cycle time + Last page data loading time) This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 42 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Copy-Back Program Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is no bit error detected in the stored data. The benefit is particularly obvious when a portion of a block is updated and the rest of the block needs to be copied to a newly assigned empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of Copy-Back Program with Destination address. A Read for Copy-Back operation with “35h” command and the Source address moves the whole 2,112byte data into the internal buffer. The host controller can detect bit errors by sequentially reading the data output. Copy-Back Program is initiated by issuing Page-Copy Data-Input command (85h) with Destination address. If data modification is necessary to correct bit errors and to avoid error propagation, data can be reloaded after the Destination address. Data modification can be repeated multiple times as shown in under figure. Actual programming operation begins when Program Confirm command (10h) is issued. Once the program process starts, the Read Status command (70h) may be entered to read the status register. The host controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register. When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The command register remains Read Status mode until another valid command is written to it. Page Copy-Back Program Operation Page Copy-Back Program Operation with Random Data Input This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 43 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Block Erase The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a threecycle row address, in which only Plane address and Block address are valid while Page address is ignored. The Erase Confirm command (D0h) following the row address starts the internal erasing process. The two-step command sequence is designed to prevent memory content from being inadvertently changed by external noise. At the rising edge of WE# after the Erase Confirm command input, the internal control logic handles erase and erase-verify. When the erase operation is completed, the host controller can check Status bit (I/O0) to see if the erase operation is successfully done. The under figure illustrates a block erase sequence, and the address input (the first page address of the selected block) is placed in between commands 60h and D0h. After tBERASE erase time, the R/B# de-asserts to ready state. Read Status command (70h) can be issued right after D0h to check the execution status of erase operation. Block Erase Operation Read Status A status register on the device is used to check whether program or erase operation is completed and whether the operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the status register to I/O pins on the falling edge of CE# or RE#, whichever occurs last. These two commands allow the system to poll the progress of each device in multiple memory connections even when R/B# pins are common-wired. RE# or CE# does not need to toggle for status change. Read Status command 70h is used to retrieve operating status of commands like page read, page program and block erase. Similarly, Read Status Two-plane Command F1h is used to retrieve operating status of two-plane commands. The command register remains in Read Status mode unless other commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command (00h) is needed to start read cycles. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 44 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Status Register Definition for 70h Command I/O Page Program Block Erase Cache Program Read Cache Read I/O0 Pass / Fail Pass / Fail Pass / Fail (N) NA NA I/O1 NA NA Pass / Fail (N-1) NA NA I/O2 I/O3 I/O4 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA I/O5 NA NA True Ready / Busy NA True Ready / Busy I/O6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy I/O7 Write Protect Write Protect Write Protect Write Protect Write Protect Definition Pass: 0 Fail: 1 Pass: 0 Fail: 1 Don’t cared Don’t cared Don’t cared Busy: 0 Ready: 1 Busy: 0 Ready: 1 Protected: 0 Not Protected: 1 Status Register Definition for F1h Command I/O Page Program Block Erase Cache Program Read Cache Read I/O0 Chip Pass / Fail Chip Pass / Fail Chip Pass / Fail (N) NA NA I/O1 Plane 0 Pass / Fail Plane 0 Pass / Fail Plane 0 Pass / Fail (N) NA NA I/O2 Plane 1 Pass / Fail Plane 1 Pass / Fail Plane 1 Pass / Fail (N) NA NA I/O3 NA NA Plane 0 Pass / Fail (N-1) NA NA I/O4 NA NA Plane 1 Pass / Fail (N-1) NA NA I/O5 NA NA True Ready / Busy NA True Ready / Busy I/O6 Ready / Busy Ready / Busy Ready / Busy Ready / Busy Ready / Busy I/O7 Write Protect Write Protect Write Protect Write Protect Write Protect Definition Pass: 0 Fail: 1 Pass: 0 Fail: 1 Pass: 0 Fail: 1 Pass: 0 Fail: 1 Pass: 0 Fail: 1 Busy: 0 Ready: 1 Busy: 0 Ready: 1 Protected: 0 Not Protected: 1 Note: 1. I/Os defined NA are recommended to be masked out when Read Status is being executed. 2. n : current page, n-1 : previous page. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 45 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (C8h), and the device code and 3rd, 4th and 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Read ID Operation ID Definition Table 1st Cycle (Maker Code) C8h 2nd Cycle (Device Code) AAh 3rd Cycle 4th Cycle 5th Cycle 90h 15h 44h RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy State during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP# is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B# pin changes to low for tRST after the Reset command is written. Refer to Figure below. Reset Operation Device Status Table Operation mode After Power-up 00h Command is latched This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 46 After Reset Waiting for next command ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Cache Read Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are transferred from data registers to cache registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used to complete data transfer from memory cells to data registers. Read Operation with Cache Read This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 47 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-Plane Page Program Two-plane Page Program is an extension of Page Program, and which utilizes the two sets of 2,112byte data registers to enable simultaneous programming of same page of same block from each plane. After writing the first set of data (up to 2,112 bytes) into the selected data registers, Dummy Page Program command (11h) instead of Page Program command (10h) is input to finish data loading for the first memory plane. R/B# remains in Busy state for a short period of time (tDBSY). Read Status (70h) may be issued to find out when the device returns to Ready state by polling the Status bit I/O6. The second set of data for the other memory plane is loaded after the 81h command and address sequence. After that, the Page Program command (10h) must be issued to start the programming process. Refer to Page Program command for the operation of R/B and Read Status. The Status bit I/O0 is set to “1” when either page fails. The following figure shows the restriction in addressing with Two-plane Page Program. Read Command Sequence of Two-plane Page Program Note: Any command between 11h and 81h is prohibited except 70h/F1h and FFh. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 48 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-Plane Page Read The Two-plane Page Read sequence and its restrictions are shown in the following figure. Two-plane Page Read is initiated by repeating command 60h followed the three address cycles twice, and only same page of same block can be selected from each plane. Once the data is loaded into the cache registers, the data output of the first plane can be read out by issuing command 00h with five address cycles, command 05h with two-cycle column address and finally E0h. The data output of the second plane can be read out using the identical command sequence. Two-plane Read command can only must be used in a block which has been programmed with Two-plane Page Program operation. Two-Plane Block Erase Similar to Two-plane Page Program, two symmetric blocks from each plane can be simultaneously erased by using Two-plane Block Erase command. Following figure illustrates the Two-plane Block Erase sequence. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 49 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-Plane Cache Read The Two-plane Cache Read sequence is shown in below, only same page of same block can be selected from each plane. After Read Confirm command (33h), the data are transferred to data registers within tR. After issuing Cache Read command (31h), read data in the data registers are transferred to cache registers within a short period of time (tDCBSYR). Once the data are loaded into the cache registers, the data of both planes can be read out in the same way as the Two-Plane Page Read operation. The host controller shall use 3Fh instead of 31h to indicate the Two-plane Cache Read operation for the last target pages. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 50 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-Plane Copy-Back Program Note: 1. Copy Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 51 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-Plane Copy-Back Program with Random Data Input Note: 1. Copy Back Program operation is allowed only within the same memory plane. 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 52 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Two-Plane Cache Program Operation Note: Any command between 11h and 81h is prohibited except 70h/F1h and FFh. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 53 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 READY/BUSY# The device has an R/B# output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B# pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an opendrain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor value is related to tr (R/B#) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart. Its value can be determined by the following guidance. Ready/ Busy# Pin Electrical Specifications R/B# RP value guidance 1.85V Rp (min) 3 mA where IL is the sum of the input currents of all devices tied to the R/ B# pin. RP (max) is determined by maximum permissible limit of tr This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 54 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Data Protection & Power-up sequence The timing sequence shown in the figure below is necessary for the power-on/off sequence. The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the initialization the device R/B# signal indicates the Busy state as shown in the figure below. In this time period, the acceptable commands are 70h. The WP# signal is useful for protecting against data corruption at power on/off. AC Waveforms for Power Transition Write Protect Operation Enabling WP# during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows: Enable Programming: NOTE: WP# keeps “High” until programming finish. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 55 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Disable Programming: Enable Erasing: Note: WP keeps “High” until erasing finish. Disable Erasing: This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 56 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Mobile DDR SDRAM Memory Operation This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 57 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Functional Block Diagram This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 58 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Simplified State Diagram Abbreviation ACT Function Active Abbreviation LMR Function Load mode register Abbreviation PRE Precharge READ Read (w/o Autoprecharge) CKEH Exit power-down READ A Read (w/ Autoprecharge) CKEL Enter power-down AREF Auto Refresh WRITE Write (w/o Autoprecharge) DPD Enter Deep Power Down SREF Enter self refresh WRITE A Write (w/ Autoprecharge) DPDX EMR Load extended mode registe BST This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Exit Deep Power Down Burst Terminate 59 PREALL Function SREFX SRR Precharge all banks Exit self refresh Status Register Read ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Electrical Specifications Absolute Maximum DC Ratings Symbol Parameter Min Max Unit VDD/VDDQ VDD/VDDQ supply voltage relative to VSS -1.0 2.4 V Vin Voltage on any pin relative to VSS -0.5 2.4 or (VDDQ+0.3V), whichever is less V Tstg Storage Temperature (plastic) -55 +150 °C Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD. Input / Output Capacitance Note1 applies to all of the parameters in this table Symbol CCK CDCK CI Parameter Min Max Unit Input capacitance: CLK, CLK# 1.5 3.0 pF - 0.25 pF 1.5 3.0 pF - 0.5 pF 2.0 4.5 pF - 0.5 pF Delta Input capacitance: CLK, CLK# Input capacitance: command, address CDI Delta Input capacitance: command, address CIO Input capacitance: DQs, DQS, DM CDIO Delta Input capacitance: DQs, DQS, DM Note 2 2 3 Notes: 1. This parameter is sampled. VDD/VDDQ = 1.70-1.95V, f=100MHz, TA = 25℃, Vout(DC) = VDDQ/2, Vout(peak-to-peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 2. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 60 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 AC/DC Electrical Characteristics and Operating Conditions Note 1 apply to all of conditions/parameters in this table VDD / VDDQ = 1.70 ~ 1.95V Symbol VDD VDDQ Parameter Min Max Unit Supply voltage 1.7 1.95 V I/O Supply voltage 1.7 1.95 V Note Address and Command inputs VIH Input high voltage 0.8 x VDDQ VDDQ + 0.3 V VIL Input low voltage -0.3 0.2 x VDDQ V -0.3 VDDQ + 0.3 V Clock inputs (CLK, CLK#) VIN DC input voltage VID (DC) DC input differential voltage 0.4 x VDDQ VDDQ + 0.6 V 2 VID (AC) AC input differential voltage 0.6 x VDDQ VDDQ + 0.6 V 2 AC differential crosspoint voltage 0.4 x VDDQ 0.6 x VDDQ V 3 VIX Data inputs VIH (DC) DC input high voltage 0.7 x VDDQ VDDQ + 0.3 V VIL (DC) DC input low voltage -0.3 0.3 x VDDQ V VIH (AC) AC input high voltage 0.8 x VDDQ VDDQ + 0.3 V VIL (AC) AC input low voltage -0.3 0.2 x VDDQ V 0.9 x VDDQ - V - 0.1 x VDDQ V -1 1 uA -5 5 uA -25 +85 °C Data outputs VOH DC Output high voltage: Logic 1 (IOH = -0.1 mA) VOL DC Output low voltage: Logic 0 (IOL = 0.1mA) Leakage current II IOZ Input leakage current Any input 0 ≦ VIN ≦ VDD, All other pins not under test = 0V Output leakage current DQs are disabled; 0 ≦ VOUT≦ VDDQ Operation Temperature TA Ambient temperature Notes: 1. All voltage referenced to VSS and VSSQ must be same potential. 2. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CLK and the input level on CLK#. 3. The value of VIX is expected to be 0.5 x VDDQ and must track variations in the DC level of the same. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 61 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 IDD Specifications and Measurement Conditions Note 1-5 apply to all of conditions/parameters in this table; VDD / VDDQ = 1.70 ~ 1.95V Symbol Version Parameter / Condition Unit Note 100 mA 6 600 uA 7,8 600 uA 7 18 mA 9 14 mA 9 5 mA 8 5 mA 20 mA 6 16 mA 6 150 mA 6 150 mA 6 tRFC = 100ns 100 mA 10 tRFC = tREFI 15 mA 10,11 10 uA 7,13 -5 IDD0 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4R IDD4W IDD5 IDD5A IDD8 Operating one bank active-precharge current: CKE = H, CS# = H between valid commands, tCK = tCK (min.), tRC = tRC (min.), Address bus inputs are SWITCHING; Data bus inputs are STABLE Precharge power-down standby current: All banks idle, CKE = L, CS# = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE Precharge power-down standby current with clock stopped: All banks idle, CKE = L, CS# = H, CLK = L,CLK# = H, Address and control inputs are SWITCHING; Data bus inputs are STABLE Precharge non power-down standby current: All banks idle, CKE = H, CS# = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE Precharge non power-down standby current with clock stopped: All banks idle, CKE = H, CS# = H, CLK = L, CLK# = H, Address and control inputs are SWITCHING; Data bus inputs are STABLE Active power-down standby current: One bank active, CKE = L, CS# = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE Active power-down standby current with clock stopped: One bank active, CKE = L, CS# = H, CLK = L, CLK# = H; Address and control inputs are SWITCHING; Data bus inputs are STABLE Active non power-down standby current: One bank active, CKE = H, CS# = H, tCK = tCK (min.), Address and control inputs are SWITCHING; Data bus inputs are STABLE Active non power-down standby current with clock stopped: One bank active, CKE = H, CS# = H, CLK = L, CLK# = H, Address and control inputs are SWITCHING; Data bus inputs are STABLE Operating burst read current: One bank active, tCK = tCK (min.), CL = 3, BL = 4, IOUT = 0mA, Continuous burst reads; Address inputs are SWITCHING, 50% data change each burst transfer Operating burst write current: One bank active, tCK = tCK (min.), BL = 4, Continuous burst writes; Address inputs are SWITCHING, 50% data change each burst transfer Auto Refresh current: tRC = tRFC (min.), tCK = tCK (min.), Burst refresh; CKE = H; Address and control inputs are SWITCHING; Data bus inputs are STABLE Deep power-down current: Address and control inputs are STABLE; Data bus inputs are STABLE This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 62 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 IDD6 Self-refresh current Note 1-5, 7 and 12 apply to all of conditions/parameters in this table; VDD / VDDQ = 1.70 ~ 1.95V Symbol IDD6 Parameter / Condition Self refresh current: CKE = L; tCK = tCK (min.); Address and control inputs are STABLE; Data bus inputs are STABLE 85 ℃ 45 ℃ PASR Typ. Max. Full Array 1000 1200 1/2 Array 700 900 1/4 Array 560 760 Full Array 1000 1200 1/2 Array 700 900 1/4 Array 560 760 Unit Note uA Notes: 1. All voltages referenced to VSS. 2. Tests for IDD may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage and temperature range specified. 3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 (or, to the crossing point for CLK and CLK#). The output timing reference voltage level is VDDQ/2. 4. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open. 5. IDD specifications are tested after the device is properly initialized, and are averaged at the defined cycle rate. 6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 7. Measurement is taken 500ms after entering into this operating mode to provide settling time for the tester. 8. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 9. IDD2N specifies DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level. 10. CKE must be active (HIGH) during the entire time a REFRESH command is executed. From the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge until tRFC later. 11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (for example, during standby). 12. Values for IDD6 85°C are guaranteed for the entire temperature range. 13. Typical values at 25°C, not a maximum value. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 63 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Electrical Characteristics and Recommended AC Operating Conditions Note 1-9 apply to all of the parameters in this table VDD/VDDQ = 1.70~1.95V Symbol -5 Parameter min. max. Unit Note Clock parameters CL = 3 2.0 4.8 ns CL = 2 2.0 6.5 ns CL = 3 4.8 - ns CL = 2 12 - ns tAC Access window of DQs from CLK, CLK# tCK Clock cycle time tCH CK high-level width 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 tCK tHP Half-clock period tCH, tCL - ns 10 17 CKE input parameters tCKE CKE minimum pulse width (high and low) 1* tCK - ns CL = 3 2.0 5.0 ns CL = 2 2.0 6.5 ns - 0.4 ns - 0.5 ns tHP - tQHS - ns 12,16 ns 16 Read parameters tDQSCK Access window of DQS from CLK, CLK# tDQSQ DQS-DQ skew, DQS to last DQ valid, per group, per access tQHS tQH n/a Data hold skew factor DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data Valid output window (DVW) tLZ CL = 3 CL = 2 DQ-out low-z window from CLK, CLK# tRPRE DQS read preamble tHZ DQ-out high-z window from CLK, CLK# tRPST DQS read postamble tSRC Read of SRR to next valid command tSRR SRR-to READ Internal temperature sensor valid temperature output enable tTQ tQH - tDQSQ 1.0 5.0 6.5 - ns ns ns CL = 3 0.9 1.1 tCK CL = 2 0.5 1.1 tCK 0.4 0.6 tCK CL+1 - tCK 2 - 12,16 18,19 18 tCK 2 ms Write parameters tDQSH DQ and DM input hold time relative to DQS (fast slew rate) DQ and DM input hold time relative to DQS (slow slew rate) DQ and DM input setup time relative to DQS (fast slew rate) DQ and DM input setup time relative to DQS (slow slew rate) DQ and DM input pulse width (for each input) Write command to first DQS latching transition DQS input high pulse width tDQSL DQS input low pulse width 0.4 0.6 tCK tDSH DQS falling edge from CK rising - hold time 0.2 - tCK tDSS DQS falling edge to CK rising - setup time 0.2 - tCK tDHf tDHs tDSf tDSs tDIPW tDQSS This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 64 0.6 - ns 0.7 - ns 0.6 - ns 0.7 - ns 1.8 - ns 0.75 1.25 tCK 0.4 0.6 tCK 12,13,14 15 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Symbol -5 Parameter tWPRE DQS write preamble tWPRES DQS write preamble setup time tWPST DQS write postamble Unit Note min. max. 0.25 - tCK 0 - ns 23,24 0.4 0.6 tCK 25 0.9 - ns 1.1 - ns 0.9 - ns Command / Address Input parameters tIHf tIHs tISf Address and control input hold time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (fast slew rate) 14,20 tISs Address and control input setup time (slow slew rate) 1.1 - ns tIPW Address and control input pulse width 2.3 - ns 2 - tCK 40 70000 ns 15 Mode register parameters tMRD Load Mode register command cycle time SDRAM core parameters 55 - ns tRCD Active to Precharge command Active to Active/Auto-refresh command period Active to Read/Write delay 15 - ns tRP Precharge command period 15 - ns tRRD Active bank-a to active bank-b command Auto precharge write recovery and precharge time Write recovery time 10 - ns - - 15 - ns Internal Write to Read command delay Exit power-down mode to first valid command Exit SELF REFRESH to first valid command 2 - tCK tRAS tRC tDAL tWR tWTR tXP tXSR 6 112.5 21 11 26 ns - ns ms tREF Refresh period - 64 tREFI Average periodic refresh interval - 7.8 us tRFC Auto Refresh command period 72 - ns 27 22 Notes: 1. All voltages referenced to Vss. 2. All parameters assume proper device initialization. 3. Tests for AC timing, and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Specifications are correlated to production test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half-strength driver with a nominal 10pF load, parameters tAC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or other simulation tools for system design validation is suggested. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 65 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 5. The CLK, CLK# input reference voltage level (for timing referenced to CLK, CLK#) is the point at which CLK and CLK# cross; the input reference voltage level for signals other than CLK, CLK# is VDDQ/2. 6. A CLK and CLK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for all parameters. 7. All AC timings assume an input slew rate of 1 V/ns. 8. CAS latency definition: with CL = 2, the first data element is valid at (tCK + tAC) after the clock at which the READ command was registered; for CL = 3, the first data element is valid at (2 × tCK + tAC) after the first clock at which the READ command was registered. 9. Timing tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 or to the crossing point for CLK, CLK#. The output timing reference voltage level is VDDQ/2. 10. Clock frequency change is supported only during a clock stop, power-down, or self-refresh mode. 11. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round to the next higher integer. 12. Referenced to each output group: DQS0 with DQ0–DQ7; DQS1 with DQ8–DQ15; DQS2 with DQ16– DQ23; and DQS3 with DQ24–DQ31. 13. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/DM/DQS slew rate is less than 1.0 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. 14. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and addresses) are measured between VIL(DC) to VIH(AC) for rising input signals and VIH(DC) to VIL(AC) for falling input signals. 15. These parameters guarantee device timing but are not tested on each device. 16. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tHP tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is provided a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. 17. tHP (MIN) is the lesser of tCL (MIN) and tCH (MIN) actually applied to the device CLK and CLK# inputs, collectively. 18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). 19. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. 20. Fast command/address input slew rate ≥1 V/ns. Slow command/address input slew rate ≥0.5 V/ns. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from the 0.5 V/ns. tIH has 0ps added, therefore, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. 21. READs and WRITEs with auto precharge must not be issued until tRAS (MIN) can be satisfied prior to the internal PRECHARGE command being issued. 22. The refresh period equals 64ms. This equates to an average refresh rate of 7.8125μs. 23. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 25. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 26. At least one clock cycle is required during tWR time when in auto precharge mode. 27. Clock must be toggled a minimum of two times during the tXSR period. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 66 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Target Output Drive Characteristics (Full Strength) Characteristics are specified under best and worst process variation/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 Pull-Down Current (mA) Pull-Up Current (mA) Min Max Min Max 0.00 2.8 5.6 8.4 11.2 14 16.8 19.6 22.4 23.8 23.8 23.8 23.8 23.8 23.8 23.8 23.8 23.8 23.8 23.8 - 0.00 18.53 26.8 32.8 37.05 40 42.5 44.57 46.5 47.48 48.5 49.4 50.05 51.35 52.65 53.95 55.25 56.55 57.85 59.15 60.45 61.75 0.00 -2.80 -5.60 -8.40 -11.20 -14.00 -16.80 -19.60 -22.40 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 - 0.00 -18.53 -26.80 -32.80 -37.05 -40.00 -42.50 -44.57 -46.50 -47.48 -48.50 -49.40 -50.05 -51.35 -52.65 -53.95 -55.25 -56.55 -57.85 -59.15 -60.45 -61.75 Notes: 1. Table values based on nominal impedance of 25Ω (full-drive) at VDDQ/2. 2. The full variation in drive current, from minimum to maximum—due to process, voltage, and temperature—will lie within the outer bounding lines of the I-V curves. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 67 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Target Output Drive Characteristics (Three-Quarter Strength) Characteristics are specified under best and worst process variation/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 Pull-Down Current (mA) Pull-Up Current (mA) Min Max Min Max 0.00 1.96 3.92 5.88 7.84 9.8 11.76 13.72 15.68 16.66 16.66 16.66 16.66 16.66 16.66 16.66 16.66 16.66 16.66 16.66 - 0.00 12.97 18.76 22.96 25.94 28 29.75 31.2 32.55 33.24 33.95 34.58 35.04 35.95 36.86 37.77 38.68 39.59 40.5 41.41 42.32 43.23 0.00 -1.96 -3.92 -5.88 -7.84 -9.8 -11.76 -13.72 -15.68 -16.66 -16.66 -16.66 -16.66 -16.66 -16.66 -16.66 -16.66 -16.66 -16.66 -16.66 - 0.00 -12.97 -18.76 -22.96 -25.94 -28 -29.75 -31.2 -32.55 -33.24 -33.95 -34.58 -35.04 -35.95 -36.86 -37.77 -38.68 -39.59 -40.5 -41.41 -42.32 -43.23 Notes: 1. The IV current for the Three-Quarters Strength Driver is approximately 70% of the full drive strength current. Table values based on nominal impedance of 36Ω (three-quarter drive strength) at VDDQ/2. 2. The full variation in drive current, from minimum to maximum—due to process, voltage, and temperature—will lie within the outer bounding lines of the I-V curves. 3. Contact factory for availability of three-quarter drive strength. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 68 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Target Output Drive Characteristics (One-half Strength) Characteristics are specified under best and worst process variation/conditions Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 Pull-Down Current (mA) Pull-Up Current (mA) Min Max Min Max 0.00 1.27 2.55 3.82 5.09 6.36 7.64 8.91 10.16 10.8 10.8 10.8 10.8 10.8 10.8 10.8 10.8 10.8 10.8 10.8 - 0.00 8.42 12.3 14.95 16.84 18.2 19.3 20.3 21.2 21.6 22 22.45 22.73 23.21 23.67 24.14 24.61 25.08 25.54 26.01 26.48 26.95 0.00 -1.27 -2.55 -3.82 -5.09 -6.36 -7.64 -8.91 -10.16 -10.8 -10.8 -10.8 -10.8 -10.8 -10.8 -10.8 -10.8 -10.8 -10.8 -10.8 - 0.00 -8.42 -12.3 -14.95 -16.84 -18.2 -19.3 -20.3 -21.2 -21.6 -22 -22.45 -22.73 -23.21 -23.67 -24.14 -24.61 -25.08 -25.54 -26.01 -26.48 -26.95 Notes: 1. Table values based on nominal impedance of 55Ω (half-drive strength) at VDDQ/2. 2. The full variation in drive current, from minimum to maximum—due to process, voltage, and temperature—will lie within the outer bounding lines of the I-V curves. 3. The I-V curve for one-quarter drive strength is approximately 50 percent of one-half drive strength. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 69 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 I-V Curves for Full, Three-Quarters and Half Drive Strength Characteristics are specified under best and worst process variation/conditions This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 70 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Basic Functionality The Mobile DDR SDRAM is a high-speed CMOS, dynamic random access memory internally configured as a four-bank DRAM. The double data rate architecture is essentially a 2n prefetch with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Mobile DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write access to the Mobile DDR SDRAM are burst oriented; access start at a selected location and continue for a programmed number of locations in a programmed sequence. Operation begins with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be activated (BA0-BA1 select the bank; A0-A13 select the row). The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst operation. The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, 8, or 16. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of the Mobile DDR SDRAMs supports concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power saving power-down mode. Deep power-down mode is offered to achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained after device enters deep power-down mode. Two self refresh features, temperature-compensated self refresh (TCSR) and partial array self refresh (PASR), offer additional power saving. TCSR is controlled by the automatic on-chip temperature sensor. The PASR can be customized using the extended mode register settings. The two features may be combined to achieve even greater power saving. The DLL that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has been omitted to save power. Prior to normal operation, the Mobile DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 71 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Initialization Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Operations procedures other than those specified may result in undefined operation. And any interruption to the device power, the initialization routine should be followed to ensure proper functionality of the Mobile DDR SDRAM. The Following sequence is required for POWER UP and Initialization 1. Apply power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simultaneously to prevent device latch-up. It is recommended that VDD and VDDQ be from the same power source or VDDQ must never exceed VDD. Assert and hold CKE HIGH. 2. When power supply voltages are stable and the CKE has been driven HIGH, it’s safe to apply the clock. 3. There must be at least 200us of valid clocks before any command may be given to the DRAM. During this time, NOP or DESELECT commands must be issued on the command bus. 4. Issue a PRECHARGE ALL command. 5. Provide NOPs or DESELECT commands for at least tRP time. 6. Issue AUTO REFRESH command followed by NOPs or DESELECT commands for at least tRFC time. And Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Two AUTO REFRESH commands must be issued. Typically, both of these commands are issued at this stage as described above. 7. Issue MRS Command to load the base mode register as desired. 8. Issue NOPs or DESELECT commands for at least tMRD time. 9. Issue MRS Command to program the extended mode register for the desired operating modes. Note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. Issue NOP or DESELECT commands for at least tMRD time. After steps 1 through 10 are completed, the Mobile DDR SDRAM has been properly initialized and is ready for any valid command. Brief Description of Initialization Sequence Step Description for Initialization 1 2 3 VDD and VDDQ Ramp: CKE must be held high Apply stable clocks Wait at least 200 μs with NOP or DESELECT on command bus 4 PRECHARGE ALL 5 Assert NOP or DESELCT for tRP time 6 Issue two AUTOREFRESH commands each followed by NOP or DESELECT commands for tRFC time 7 Configure Mode Register 8 Assert NOP or DESELECT for tMRD time 9 10 11 Configure Extended Mode Register Assert NOP or DESELECT for tMRD time Mobile SDRAM is ready for any valid command This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 72 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Initialization Sequence Note: 1. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH command; ACT = ACTIVE command. 2. NOP or DESELECT commands are required for at least 200us. 3. Other valid commands are possible. 4. NOPs or DESELECTs are required during this time. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 73 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Register Definition Mode Registers and Extended Mode Registers The Mode Registers are used to define the specific mode of operation of the Mobile DDR SDRAM. This define includes the definition of a burst length, a burst type, a CAS latency. Additionally, driver strength, Temperature Compensated Self Refresh (TCSR), and Partial Array Self Refresh (PASR) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. The default value of the mode register is not defined, therefore the mode register must be written after power up for proper operation. The Mode Register must be loaded when all banks are idle and no bursts are progress, and the controller must wait the specific time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. The MRS contents won’t be changed until it is reprogrammed, the device goes into Deep Power-Down, or the device loses power. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0 and BA1, while controlling the state of address pins A0~A13. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on the functionality. Burst length is defined by A0~A2 with options of 2, 4, 8 and 16 bit burst length. Burst address sequence type is defined by A3 and CAS# latency is defined by A4~A6. A7~A13 must be set to low to ensure future compatibility. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 74 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Standard Mode Register definition Notes: 1. The integer n is equal to the most significant address bit. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 75 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Burst Length, Type, and Order Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. The burst length is defined by bits A0-A2. Burst length options include 2, 4, 8 or 16 for both the sequential and the interleaved burst types. When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap when a boundary is reached. The block is uniquely selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, by A3–Ai when BL = 8, and by A4–Ai when BL = 16, where Ai is the most significant column address bit for a given configuration. The remaining (least significant) address bits are used to specify the starting location within the block. The programmed BL applies to both READ and WRITE bursts. Accesses within a given burst may be programmed to be either sequential or interleaved via the standard mode register. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 76 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Burst Type and Burst Order Burst Length Starting Column Address Sequential Mode Interleave Mode 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F 0 0 0 1 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, B, A, D, C, F, E 0 0 1 0 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1 2, 3, 0, 1, 6, 7, 4, 5, A, B, 8, 9, E, F, C, D 0 0 1 1 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4, B, A, 9, 8, F, E, D, C 0 1 0 0 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3, C, D, E, F, 8, 9, A, B 0 1 0 1 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2, D, C, F, E, 9, 8, B, A 0 1 1 0 6, 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1, E, F, C, D, A, B, 8, 9 0 1 1 1 7, 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0, F, E, D, C, B, A, 9, 8 1 0 0 0 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7 8, 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7 1 0 0 1 9, A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8 9, 8, B, A, D, C, F, E, 1, 0, 3, 2, 5, 4, 7, 6 1 0 1 0 A, B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 A, B, 8, 9, E, F, C, D, 2, 3, 0, 1, 6, 7, 4, 5 1 0 1 1 B, C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A B, A, 9, 8, F, E, D, C, 3, 2, 1, 0, 7, 6, 5, 4 1 1 0 0 C, D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B C, D, E, F, 8, 9, A, B, 4, 5, 6, 7, 0, 1, 2, 3 1 1 0 1 D, E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C D, C, F, E, 9, 8, B, A, 5, 4, 7, 6, 1, 0, 3, 2 1 1 1 0 E, F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D E, F, C, D, A, B, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 1 F, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E F, E, D, C, B, A, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 A3 A2 A1 A0 2 4 8 16 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 77 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 CAS Latency (CL) The CAS Latency, or READ latency is the delay, in clock cycles, between the registration of a Read command and the availability of the first bit of output data. CAS Latency is defined by bit A6~A4 in the standard mode register. If a READ command is registered at a clock edge n, and the CAS latency is 3 clocks, the first data element will be valid at (n + 2tCK + tAC). If a READ command is registered at a clock edge n, and the CAS latency is 2 clocks, the first data element will be valid at (n + 1tCK + tAC). This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 78 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Extended Mode Register definition The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include output drive strength selection, Temperature Compensated Self Refresh (TCSR) and Partial Array Self Refresh (PASR). TCSR and PASR are effective in Self Refresh mode only. The extended mode register is programmed via the LOAD MODE REGISTER command with BA0=0 and BA1=1, and the information won’t be changed until it is reprogrammed, the device goes into deep power-down mode, or the device loses power. The EMRS must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. Address bits A0-A2 specify PASR, A3-A4 the TCSR, A5-A6 the Drive Strength. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility. Temperature Compensated Self Refresh (TCSR) On this version of the Mobile DDR SDRAM, the internal temperature sensor is implemented to adjust the self refresh oscillator automatically base on the case temperature. To maintain backward compatibility, the programming of TCSR bits no effect on the device. The address bits, A3 and A4 are ignore (don’t care) during EMRS programming. Partial-Array Self Refresh (PASR) For further power savings during self refresh, the PASR feature may allow the self refresh to be restricted to a variable portion of the total array. They are full array (default: banks 0, 1, 2, and 3), 1/2 array (banks 0 and 1), 1/4 array (bank 0). Data outside the defined area will be lost. Address bits A0 to A2 are used to set PASR. Output Drive Strength Mobile DDR SDRAM provides the option to control the drive strength of the output buffers for the smaller systems or point-to-point environments. The value was selected based on the expected loading of the memory bus. Total four values provided, and they are 25 ohm, 36ohm, 55ohm, and 80ohm internal impedance. They are full, three-quarter, one-half, and one-quarter drive strengths, respectively. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 79 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Extended Mode Register Notes: 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect. 2. The integer n is equal to the most significant address bit. Status Read Register (SRR) The status read register (SRR) is only for READ, and contains the specific die information such as density, device type, data bus width, refresh rate, revision ID and manufactures. The SRR is read via the LOAD MODE REGISTER command with BA0=1 and BA1=0. The sequence to perform an SRR command is as follows: ● ● ● ● ● ● The device had been properly initialized and in the idle or all banks precharge state. Issue a LMR command with BA [1:0] = “01”. Wait tSRR; only NOP or DESELECT commands are supported during this period. Issue a READ command with all address pins set to “0”. CAS latency cycles later, the device returns the registers data. The SRR read with fixed burst length 2, first bit of the burst output SRR data, and second bit of the burst is “Don’t Care”. The next command to the SDRAM must be issued tSRC after the SRR READ command is issued; only NOP or DESELECT commands are supported during this period. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 80 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. SRR can only be issued after power-up sequence is complete, and all banks are precharged and in the idle state. 2. NOP or DESELECT commands are required between LMR and READ command (tSRR) and between READ and next VALID command (tSRC) 3. CAS latency is predetermined by the programming of the mode register. Here CL=3 as an example only. 4. Burst length is fixed to 2 for SRR regardless of the value programmed by the mode register. 5. The second bit of the data-out burst is a “Don’t Care”. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 81 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Status Register Definition Notes: 1. Reserved bits should be set to zero for future compatibility. 2. Refresh multiplier is based on the memory device’s on-board temperature sensor. Required average periodic refresh interval = tREFI x multiplier. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 82 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Mobile DDR SDRAM Command Description and Operation Command Truth Table NAND (Function) Abbreviation CS# RAS# CAS# WE# BA A10/AP ADDR NOTES DESELECT H X X X X X X 2 NO OPERATION NOP L H H H X X X 2 ACTIVE (select bank and active row) ACT L L H H Valid Row Row READ L H L H Valid L Col DESELECT READ (select bank, column, and start read burst) READ with AP (read burst with Auto Precharge) READA L H L H Valid H Col WRITE (select bank, column, and start write burst) WRITE L H L L Valid L Col 3 WRITE with AP (write burst with Auto Precharge) WRITEA L H L L Valid H Col 3 BURST TERMINATE or enter Deep Power-Down BST L H H L X X X 4, 5 PRECHARGE (deactive row in selected bank) PRE L L H L Valid L X 6 PRECHARGE ALL (deactive rows in all banks) PREALL L L H L X H X 6 REFA / REFS L L L H X X X 7, 8, 9 LMR L L L L Valid AUTO REFRESH or enter SELF REFRESH LOAD MODE REGISTER Op-code 10 Notes: 1. All states and sequences not shown are illegal or reserved. 2. DESELECT and NOP are functionally interchangeable. 3. Auto-precharge is non-persistent. A10 High enables Auto Precharge, while A10 Low disables Autoprecharge. 4. Burst Terminate applies to only Read bursts with Auto0precharge disabled. This command is undefined and should not be used for Read with Auto-precharge enable, and for write bursts. 5. This command is BURST TERMINATE if CKE is High, and Deep Power-Down entry is CKE is Low. 6. If A10 is Low, bank address determines which bank is to be precharged. If A10 is High, all banks are precharged and BA0, BA1 are don’t care. 7. This command is AUTO REFRESH is CKE is High, and SELF REFRESH if CKE is Low. 8. All address inputs and I/O are ‘Don’t care’, except for CKE. Internal refresh counters control bank and row addressing. 9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command. 10. BA0 and BA1 value select between MRS, EMRS and SRR. 11. CKE is High for all commands shown, except SELF REFRESH and Deep Power-Down. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 83 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Basic Timing Parameters for Commands Notes: 1. Input = A0 – An, BA0, BA1, CKE, CS#, RAS#, CAS#, WE#; An = Address bus MSB. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 84 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Current State Bank n Truth Table (command to Bank n) Current State Any Idle Row Active Read (AP disable) Write (AP disable) Command CS # RAS # CAS# Action (n) -Result WE# Description H X X X DESELECT (NOP) Continue previous operation L H H H NOP Continue previous operation L L H H ACTIVE L L L H AUTO REFRESH Notes Select and Activate row Auto refresh MODE REGISTER SET Mode register set 10 L L L L L H L H READ Select column & start read burst 10 L H L L WRITE Select column & start write burst L L H L PRECHARGE Deactivate row in bank or banks L H L H READ Select column & start new read burst L H L L WRITE Select column & start write burst L L H L PRECHARGE L H H L BURST TERMINATE L H L H READ Select column & start read burst L H L L WRITE Select column & start new write burst 5, 6 L L H L PRECHARGE Truncate write burst, start precharge 12 4 5, 6 5, 6, 13 Truncate read burst, start precharge Burst terminate 11 5, 6, 12 Notes: 1. The Table applies when both CKEn-1 and CKE are HIGH, and after tXSR or tXP has been met if the previous state was self refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 5. A command other than NOP should not be issued to the same bank while a READ or WRITE burst with Auto Precharge is enabled. 6. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled. 7. Current State Definitions: Idle: The bank has been precharged, and the tRP has been met. Row Active: A row in the bank has been activated, and tRCD had been met. No data bursts/accesses, register accesses in progress Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 8. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or supported commands to the other bank, should be issued on any clock edge occurring during these states. Supported commands to any other bank are determined by that bank’s current state. Precharging: Starts with registration of a PRECHARGE command, ends when tRP is met. Then the bank will be in idle state. Row Activating: Starts with registration of an AVTIVE command, ends when tRCD is met Then the bank will be in row active state Read w/ AP enabled: Start with registration of a READ command with auto precharge enabled, ends when tRP has been met. Then the bank will be in the idle state. Write w/ AP enabled: Start with registration of a WRITE command with auto precharge enabled, ends when tRP has been met. Then the bank will be in the idle state. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 85 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command, ends when tRFC is met. Then all banks will be in idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command, ends when tMRD is met. Then all banks will be in idle state. Precharging All: Starts with registration of a PRECHARGE ALL command, ends when tRP is met. Then all banks will be in idle state 10. Not bank-specific; requires that all banks are idle and no bursts are in progress. 11. Not bank-specific; BURST TERMINATE affects the most recent read burst, regardless of bank. 12. Requires appropriate DM masking. 13. A WRITE command may be applied after the READ burst had been completed; otherwise, a BURST TERMINATE must be used to end the READ prior to asserting a WRITE command. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 86 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Current State Bank n Truth Table (command to Bank m) Current State Any Idle Row Activating, Active, or Precharging Read (AP disable) Write (AP disable) Read (AP enable) Write (AP disable) Command CS # RAS # CAS# Action (n) -Result WE# Description Notes H X X X DESELECT (NOP) Continue previous operation L H H H NOP Continue previous operation X X X X ANY Any command allowed to bank m L L H H ACTIVE L H L H READ Select column & start read burst 8 L H L L WRITE Select column & start write burst 8 L L H L PRECHARGE L L H H ACTIVE L H L H READ Select column & start read burst 8 L H L L WRITE Select column & start write burst 8, 10 L L H L PRECHARGE L L H H ACTIVE L H L H READ L H L L WRITE L L H L PRECHARGE L L H H ACTIVE L H L H READ Select and activate row Precharge Select and activate row Precharge Select and activate row Select column & start read burst 8, 9 Select column & start write burst 8 Precharge Sselect and activate row Select column & start read burst 5, 8 Select column & start write burst 5, 8, 10 L H L L WRITE L L H L PRECHARGE L L H H ACTIVE L H L H READ Select column & start read burst 5, 8 L H L L WRITE Select column & start write burst 5, 8 L L H L PRECHARGE Precharge Sselect and activate row Precharge Notes: 1. The Table applies when both CKEn-1 and CKE are HIGH, and after tXSR or tXP has been met if the previous state was self refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. Current State Definitions: Idle: The bank has been precharged, and the tRP has been met. Row Active: A row in the bank has been activated, and tRCD had been met. No data bursts/accesses, register accesses in progress Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 5. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. The devices support concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 87 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 is enabled, any command to other banks is supported, as long as that command does not interrupt the read or write data transfer already in progress. In either case, all other related limitations apply (for example, contention between read data and write data must be avoided). The minimum delay from a READ or WRITE command with auto precharge enabled to a command to a different bank is summarized below. 6. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all banks are idle. 7. A BURST TERMINATE command can not be issued to another bank; it applies to the bank represented by the current state only. 8. READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs and WRITEs with Auto Precharge disabled. 9. Requires appropriate DM masking. 10. A WRITE command may be only be applied after the completion of data output, otherwise a BURST TERMINATE command must be issued to end the READ prior to asserting a WRITE command. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 88 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 COMMAND NO OPERATION (NOP) The No operation (NOP) command is used to instruct the selected Mobile DDR SDRAM to perform a NOP. This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. DESELECT The Deselect function (CS#=HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via the address inputs and can only be issued when all banks are idle, no bursts are in progress. The subsequent executable command can not be issued until tMRD is met. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 89 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The values on the BA0 and BA1 inputs select the bank, and the addresses provided on inputs A0-A13 selects the row. Once a row is open, a READ or WRITE command could be issued to that row, subject to the tRCD specification. A subsequent ACTIVE command to another row in the same bank can only be issued after the previous row has been closed. The minimum time interval between two successive ACTIVE commands on the same bank is defined by tRC. The subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total rowaccess overhead. The minimum time interval between two successive ACTIVE commands on different banks is defined by tRRD. These rows remain active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 90 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 READ The READ command is used to initiate a burst read access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. During Read bursts, DQS is driven by the Mobile DDR SDRAM along with the output data. The initial Low state of the DQS is known as the read preamble; the Low state coincident with last data-out element is known as the read postamble. The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out elements are edge aligned to successive edges of DQS. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 91 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 WRITE The WRITE command is used to initiate a burst write access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE command and the first rising edge is called the write preamble; the Low state on DQS following the last data-in element is called write postamble. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 92 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. AUTO PRECHARGE Auto Precharge is a feature which performs the same individual bank precharge function, but without requiring an explicit command. This is accomplished by using A10 (A10=High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst. Auto precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. BURST TERMINATE The BURST TERMINATE command is used to truncate read bursts with auto precharge disabled. The most recently registered READ command prior to the BURST TERMINATE command will be truncated. The BURST TERMINATE command is not bank specific, and should not be used to terminate write bursts. REFRESH Mobile DDR SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode: AUTO REFRESH AUTO REFRESH command is used during normal operation of the Mobile DDR SDRAM, and it’s nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. The address bits become “Don’t Care” during AUTO REFRESH. The Mobile DDR SDRAM requires AUTO REFRESH commands at an average periodic interval of tREFI. To provide improved efficiency in scheduling and switching between tasks, some flexibility in the absolute interval is provided. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 93 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 SELF REFRESH SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without external clocking. The Mobile DDR SDRAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. Once the SELF REFRESH command is registered, the external clock can be halted after one clock later. CKE must be held low to keep the device in Self Refresh mode, and internal clock also disabled to save power. The minimum time that the device must remain in Self Refresh mode is tRFC. In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self Refresh and Partial Array Self Refresh. During this mode, the device is refreshed as identified in the extended mode register. An internal temperature sensor will adjust the refresh rate to optimize device power consumption while ensuring data integrity. During SELF REFRESH operation, refresh intervals are scheduled internally and may vary. These refresh intervals may be different then the specified tREFI time. For this reason, the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command. The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. When CKE is HIGH, the Mobile DDR SDRAM must have NOP commands issued for tXSR time. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 94 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Power-Down Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Power-down mode deactivates the input and output buffers, excluding CLK, CLK# and CKE. CKE keep Low to maintain device in the power-down mode, and all other inputs signals are “Don’t Care”. The minimum power-down duration is specified by tCKE. The device can not stay in this mode for longer than the refresh requirements of the device, without losing data. The power-down state is synchronously existed when CKE is registered High (along with a NOP or DESELECT command). A valid command can be issued after tXP after exist from power-down. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 95 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Deep-Power-Down The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the Mobile DDR SDRAM are stopped and all memory data, MRS and EMRS information is lost in this mode. The DPD command is the same as a BURST TERMINATE command with CKE LOW. All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this mode, CKE must be held in a constant Low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands must be maintained for at least 200us. After 200us a complete reinitialization is required. Clock Stop Stopping a clock during idle periods is an effective method of reducing power consumption. The Mobile DDR SDRAM supports clock stop mode under the following conditions: ● The last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any data-out during read bursts; the number of clock pluses per access command depends on the device’s AC timing parameters and the clock frequency; ● The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met; ● CKE is held High. When all conditions have been met, the device is either in “idle state” or “row active state”, and clock stop may be entered with CLK held Low and CLK# held High. Clock Stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 96 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Timing READs READ burst operations are initiated with a READ command. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out elements are edge aligned to successive edges of DQS. DQS is driven by Mobile DDR SDRAM along with output data. Upon completion of a read burst, assuming no other READ command has been initiated, the DQ will go to High-Z. Notes: 1. Dout n = data-out from column n. 2. Shown with nominal tAC, tDQSCK, and tDQSQ. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 97 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. DQ transitioning after DQS transitions define tDQSQ window. 2. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. 3. tAC is the DQ output window relative to CK and is the “long-term” component of DQ skew. 4. Commands other than NOP may be valid during this cycle. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 98 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. DQ transitioning after DQS transitions define tDQSQ window. 2. Byte 0 is DQ0-DQ7, Byte 1 is DQ8-DQ15, Byte 2 is DQ16-DQ23, and Byte 3 is DQ24-DQ31. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition . 4. tOH is derived from tHP, tOH = tHP - tOHS. 5. tOH is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived from each DQS transition and is tOH – tDQSQ. 7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for byte 2; DQ[31:24] and DQS3 for byte This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 99 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 READ to READ Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. The new READ command should be issued X cycles after the first READ command, where X equals the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture). Notes: 1. Dout n (or b) = data-out from column n (or column b). 2. BL = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first). 3. Shown with nominal tAC, tDQSCK, and tDQSQ. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 100 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Dout n (or b) = data-out from column n (or column b). 2. BL = 4, 8, or 16 (if 4, the bursts are concatenated; if 8 or 16, the second burst interrupts the first). 3. Shown with nominal tAC, tDQSCK, and tDQSQ. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 101 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Dout n (or x, b, g) = data-out from column n (or column x, column b, column g). 2. BL = 2, 4, 8, or 16 (if 4, 8 or 16, the following burst interrupts the previous). 3. Shown with nominal tAC, tDQSCK, and tDQSQ. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 102 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 READ BURST TERMINATE Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is equal to read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ command where X equals the desired data-out element pairs (pairs are required by the 2n-prefetech architecture). Notes: 1. Dout n = data-out from column n. 2. BL = 4, 8, or 16. 3. Shown with nominal tAC, tDQSCK, and tDQSQ. 4. BST = BURST TERMINATE command; page remains open. 5. CKE = HIGH. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 103 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 READ to WRITE Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used. Notes: 1. Dout n = data-out from column n. 2. BL = 4, 8, or 16. 3. Shown with nominal tAC, tDQSCK, and tDQSQ. 4. BST = BURST TERMINATE command; page remains open. 5. CKE = HIGH. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 104 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 READ to Precharge A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank. The PRECHARGE command should be issued X cycles after the READ command, where X equals the number of desired data element pairs. Following the PRECHARGE command, a subsequent command to the same bank can not be issued until tRP is met. Part of the row precharge time is hidden during the access of the last data element. In the case of a READ being executed to completion, a PRECHARGE command issued at optimum time provides the same operation as READ with AP. The disadvantage of PRECHARGE command is that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that can be used to truncate bursts. Notes: 1. Dout n = data-out from column n. 2. BL = 4, or an interrupted burst 8 or 16. 3. Shown with nominal tAC, tDQSCK, and tDQSQ. 4. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out. A READ command with auto precharge enabled, provided tRAS (min) is met, would cause a precharge to be performed at X number of clock cycles after the READ command, where x = BL/2. 5. PRE = PRECHARGE command; ACT = ACTIVE command. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 105 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 WRITEs WRITE burst operations are initiated with a WRITE command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. Input data appearing on the data bus is written to the memory array subject to the state of the data mask DM inputs coincident with the data. Notes: 1. Din n = data-in from column n. 2. BL = 4 in the case shown. 3. Disable auto precharge. 4. Bank x at T8 is “Don’t Care”, if A10 is HIGH at T8. 5. PRE = PRECHARGE command. 6. NOP commands are shown for ease of illustration; other commands may be valid at these time. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 106 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 WRITE Burst The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75% to 125% of one clock cycle). All of the WRITE diagrams show the nominal case, and where the two extreme cases (that is, tDQSS(min) and tDQSS(max)) might not be intuitive, they have also been included. Upon completion of the burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored. Notes: 1. Din b = data-in from column b. 2. An uninterrupted burst of 4 is shown. 3. A10 is LOW with the WRITE command (Auto Precharge is disabled). This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 107 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 WRITE to WRITE Data for any WRITE burst may be concatenated with or truncated by a subsequent WRITE command. In either case, a continuous flow input data can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command. The first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of the longer burst which is being truncated. The new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of desired data-in element pairs (pairs are required by the 2n-prefetch architecture). Notes: 1. Din b (n) = data-in from column b (n). 2. An uninterrupted burst of 4 is shown. 3. Each WRITE command may be to any bank. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 108 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Din b (n) = data-in from column b (n). 2. An uninterrupted burst of 4 is shown. 3. Each WRITE command may be to any bank. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 109 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Din b (or x, n, a, g) = data-in from column b (or x, n, a, g). 2. b’ (or x’, n’, a’, g’) = the next data-in following Din b (x, n, a, g) according to the programmed burst order. 3. Programmed BL = 2, 4, 8, or 16 in cases shown. 4. Each WRITE command may be to any bank. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 110 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 WRITE to READ Data for any Write burst may be followed by a subsequent READ command. To follow a Write without truncating the write burst, tWTR should be met as shown in Figure. Notes: 1. Din b = data-in from column b; Dout n = data-out for column n. 2. An uninterrupted burst of 4 is shown. 3. tWTR is referenced from the first positive CLK edge after the last data-in pair. 4. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices. In which case tWTR is not required and the READ command could be applied earlier. 5. A10 is LOW with the WRITE command (auto precharge is disabled). Data for any Write burst may be truncated by a subsequent READ command as shown in Figure. Note that the only data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 111 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Din b = data-in from column b; Dout n = data-out for column n. 2. An uninterrupted burst of 4 is shown; two data elements are written. 3. tWTR is referenced from the first positive CK edge after the last data-in pair. 4. A10 is LOW with the WRITE command (auto precharge is disabled). 5. DQS is required at T2 and T2n (nominal case) to register DM. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 112 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 WRITE to PRECHARGE Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in the Figure. Notes: 1. PRE = PRECHARGE. 2. Din b = data-in from column b. 3. An uninterrupted burst of 4 is shown. 4. A10 is LOW with the WRITE command (auto precharge is disabled). 5. tWTR is referenced from the first positive CK edge after the last data-in pair. 6. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands can be to different devices; in this case, tWR is not required and the PRECHARGE command can be applied earlier. Data for any Write burst may be truncated by a subsequent PRECHARGE command as shown in Figure. Note that the only data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in must be masked with DM. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 113 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 After the PRECHARGE command, a subsequent command to the same bank can not be issued until tRP is met. Notes: 1. PRE = PRECHARGE. 2. tWR is referenced from the first positive CLK edge after the last data-in pair. 3. Din b = data-in from column b. 4. An interrupted burst of 8 is shown; two data elements are written. 5. A10 is LOW with the WRITE command (auto precharge is disabled). 6. DQS is required at T4 and T4n to register DM. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 114 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be precharged (A10=LOW), inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. AUTO PRECHARGE Auto Precharge is a feature which performs the same individual bank precharge function described previously, but without requiring an explicit command. This is accomplished by using A10 (A10=High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank / row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst. Auto precharge is non-persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The “earliest valid stage” is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS(min). The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. For READ with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all the data in the burst. For WRITE with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. In addition, during a WRITE with auto precharge, at least one clockis required during tWR time. During the prechare period, the user must not issue another command to the same bank until tRP is satisfied. This device supports tRAS lock-out. In the case of a single READ with auto-precharge or a single WRITE with auto-precharge issued at tRCD(min), the internal precharge will be delayed until tRAS(min) has been satisfied. Concurrent AUTO PRECHARGE This device supports concurrent auto precharge such that when a READ with auto precharge is enabled or a WRITE with auto precharge is enabled, any command to another bank is supported, as long as that command does not interrupt the read or write data transfer already in process. This feature enables the precharge to complete in the bank in which the READ or WRITE with auto precharge was executed, without requiring an explicit PREACHRGE command, thus freeing the command bus for operations in other banks. During the access period of a READ or a WRITE with auto precharge, only ACTIVE and PRECHARGE commands may be applied to other banks. During the precharge period, ACTIVE, PRECHARGE, READ, and WRITE commands may be applied to other banks. In either situation, all other related limitations apply. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 115 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Din n = data-out from column n. 2. BL =4 in the case shown. 3. Enable auto precharge. 4. NOP commands are shown for ease of illustration; other commands may be valid at these times. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 116 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Din n = data-out from column n. 2. BL =4 in the case shown. 3. Disable auto precharge. 4. BANK x at T5 is “Don’t Care”, if A10 is HIGH at T5. 5. PRE = PRECHARGE. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. The PRECHARGE command can only be applied at T5, if tRAS(min) is met. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 117 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Din n = data-out from column n. 2. BL =4 in the case shown. 3. Enable auto precharge. 4. NOP commands are shown for ease of illustration; other commands may be valid at these times. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 118 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Notes: 1. Din n = data-out from column n. 2. BL =4 in the case shown. 3. Disable auto precharge. 4. Bank x at T8 is “Don’t Care”, if A10 is HIGH at T8. 5. PRE = PRECHARGE. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 119 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 AUTO REFRESH AUTO REFRESH command is used during normal operation of the Mobile DDR SDRAM, and is analogous to CAS#-BEFORE-RAS# (CBR) Refresh in the FPM/EDO DRAMs. The Auto Refresh is nonpersistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. The address bits become “Don’t Care” during AUTO REFRESH. The Mobile DDR SDRAM requires AUTO REFRESH commands at an average periodic interval of tREFI. To provide improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. Although it is not a JEDEC requirement, CKE must be active (HIGH) during the auto refresh period to provide support for future functional features. The auto refresh period begins when the AUTO REFRESH command is registered and ends tRFC later. Notes: 1. PRE = PRECHARGE; AR = AUTO REFRESH. 2. NOP commands are shown for ease of illustration; other commands may be valid at these times. CKE must be active during clock positive transitions. 3. NOP or COMMAND INHIBIT are the only commands supported until after tRFC time; CKE must be active during clock positive transitions. 4. Bank x at T1 is “Don’t Care”, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active. 5. DM, DQ, and DQS signals are all “Don’t Care”, High-Z for operations shown. 6. The second AUTO PRECHARGE is not required and is only shown as an example of two back-toback AUTO REFRESH commands. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 120 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 SELF REFRESH SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without external clocking. The Mobile DDR SDRAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. During SELF REFRESH, the device is refreshed as identified in the extended mode register. Once the SELF REFRESH command is registered, the external clock can be halted after one clock later. CKE must be held low to keep the device in Self Refresh mode, and internal clock also disabled to save power. The minimum time that the device must remain in Self Refresh mode is tRFC. In the Self Refresh mode, two additional power-saving options exist: Temperature Compensated Self Refresh and Partial Array Self Refresh. During this mode, the device is refreshed as identified in the extended mode register. An internal temperature sensor will adjust the refresh rate to optimize device power consumption while ensuring data integrity. During SELF REFRESH operation, refresh intervals are scheduled internally and may vary. These refresh intervals may be different then the specified tREFI time. For this reason, the SELF REFRESH command must not be used as a substitute for the AUTO REFRESH command. The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. When CKE is HIGH, the Mobile DDR SDRAM must have NOP commands issued for tXSR time to complete any internal refresh already in progress. Self Refresh is to be supported for full AT temperature range up to 105℃. A temperature trip point should be provided to achieve 4x refresh rate above 85℃. Notes: 1. Clock must be stable, cycling within specifications by Ta0, before exiting self refresh mode. 2. Device must be in the all banks idle state prior to entering self refresh mode. 3. NOPs or DESELECTs is required for tXSR time with at least two clock pulses. 4. AR = AUTO REFRESH. 5. CKE must remain LOW to remain in self refresh. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 121 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Power-Down Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Power-down mode deactivates all input and output buffers, excluding CLK, CLK# and CKE. CKE keep Low to maintain device in the power-down mode, and all other inputs signals are “Don’t Care”. The minimum power-down duration is specified by tCKE. The device can not stay in this mode for longer than the refresh requirements of the device, without losing data. The power-down state is synchronously existed when CKE is registered High (along with a NOP or DESELECT command). A valid command can be issued after tXP after exist from power-down. Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode is active power-down. 2. No column accesses can be in progress, when power-down is entered. 3. tCKE applies if CKE goes LOW at Ta2 (entering power-down); tXP applies if CKE remains HIGH at Ta2 (exit power-down). This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 122 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Deep-Power-Down The Deep Power-Down (DPD) mode is an operating mode used to achieve maximum power reduction by eliminating the power of the memory array. All internal voltage generators inside the Mobile DDR SDRAM are stopped and all memory data, MRS and EMRS information is lost in this mode. The DPD command is the same as a BURST TERMINATE command with CKE LOW. All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this mode, CKE must be held in a constant Low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands must be maintained for at least 200us. After 200us a complete re-initialization is required. Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPD = Deep Power-Down. 3. Upon exit of power-down mode, a full DRAM initialization sequence is required. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 123 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Clock Stop One method of controlling the power efficiency in applications is to throttle the clock that controls the Mobile DDR SDRAM. The clock may be controlled in two ways: ● Change the clock frequency. ● Stop the clock. The Mobile DDR SDRAM enables the clock to change frequency during operation only if all the timing parameters are met, and all refresh requirements are satisfied. The clock can be stopped altogether if there are no DRAM operations in progress that would be affected by this change. Any DRAM operation already in process must be completed before entering clock stop mode; this includes the following timings: tRCD, tRP, tRFC, tMRD, tWR, and tRPST. In addition, any READ or WRITE burst in progress must complete. CKE must be held HIGH, with CLK = LOW and CLK# = HIGH, for the full duration of the clock stop mode. One clock cycle and at least one NOP or DESELECT is required after the clock is restarted before a valid command can be issued. Notes: 1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before any valid command. 2. Any valid command is supported; device is not in clock suspend mode. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 124 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29 EN71SN2BGD11 Revisions List Revision No Description Date A B Initial Release Correct the typo on page 2. (1Gb = 4 Banks X 8M X 32 bits) 2013/11/21 2013/11/29 This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 125 ©2013 Eon Silicon Solution, Inc., www.eonssi.com Rev. B, Issue Date: 2013/11/29